debug lk

hc

2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077

 kernel/include/dt-bindings/clock/tegra210-car.h
..
..
@@ -262,6 +262,8 @@
262
262
 #define TEGRA210_CLK_CLK_M 233
263
263
 #define TEGRA210_CLK_CLK_M_DIV2 234
264
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 #define TEGRA210_CLK_CLK_M_DIV4 235
265
+#define TEGRA210_CLK_OSC_DIV2 234
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+#define TEGRA210_CLK_OSC_DIV4 235
265
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 #define TEGRA210_CLK_PLL_REF 236
266
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 #define TEGRA210_CLK_PLL_C 237
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269
 #define TEGRA210_CLK_PLL_C_OUT1 238
..
..
@@ -304,12 +306,12 @@
304
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 #define TEGRA210_CLK_AUDIO3 274
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 #define TEGRA210_CLK_AUDIO4 275
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 #define TEGRA210_CLK_SPDIF 276
307
-#define TEGRA210_CLK_CLK_OUT_1 277
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-#define TEGRA210_CLK_CLK_OUT_2 278
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-#define TEGRA210_CLK_CLK_OUT_3 279
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-#define TEGRA210_CLK_BLINK 280
311
-/* 281 */
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-#define TEGRA210_CLK_SOR1_SRC 282
309
+/* 277 */
310
+/* 278 */
311
+/* 279 */
312
+/* 280 */
313
+#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
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+#define TEGRA210_CLK_SOR0_OUT 281
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 #define TEGRA210_CLK_SOR1_OUT 282
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 /* 283 */
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 #define TEGRA210_CLK_XUSB_HOST_SRC 284
..
..
@@ -349,14 +351,14 @@
349
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 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317
350
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 #define TEGRA210_CLK_XUSB_SSP_SRC 318
351
353
 #define TEGRA210_CLK_PLL_RE_OUT1 319
352
-/* 320 */
353
-/* 321 */
354
+#define TEGRA210_CLK_PLL_MB_UD 320
355
+#define TEGRA210_CLK_PLL_P_UD 321
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 #define TEGRA210_CLK_ISP 322
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 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323
356
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 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
357
359
 /* 325 */
358
-/* 326 */
359
-/* 327 */
360
+#define TEGRA210_CLK_OSC 326
361
+#define TEGRA210_CLK_CSI_TPG 327
360
362
 /* 328 */
361
363
 /* 329 */
362
364
 /* 330 */
..
..
@@ -386,12 +388,12 @@
386
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 #define TEGRA210_CLK_AUDIO3_MUX 353
387
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 #define TEGRA210_CLK_AUDIO4_MUX 354
388
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 #define TEGRA210_CLK_SPDIF_MUX 355
389
-#define TEGRA210_CLK_CLK_OUT_1_MUX 356
390
-#define TEGRA210_CLK_CLK_OUT_2_MUX 357
391
-#define TEGRA210_CLK_CLK_OUT_3_MUX 358
391
+/* 356 */
392
+/* 357 */
393
+/* 358 */
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 #define TEGRA210_CLK_DSIA_MUX 359
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 #define TEGRA210_CLK_DSIB_MUX 360
394
-#define TEGRA210_CLK_SOR0_LVDS 361
396
+/* 361 */
395
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 #define TEGRA210_CLK_XUSB_SS_DIV2 362
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398
 
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 #define TEGRA210_CLK_PLL_M_UD 363