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| 26 | 26 | #define MMP2_CLK_VCTCXO_4 25 |
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| 27 | 27 | #define MMP2_CLK_UART_PLL 26 |
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| 28 | 28 | #define MMP2_CLK_USB_PLL 27 |
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| 29 | +#define MMP3_CLK_PLL1_P 28 |
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| 30 | +#define MMP3_CLK_PLL2_P 29 |
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| 31 | +#define MMP3_CLK_PLL3 30 |
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| 32 | +#define MMP2_CLK_I2S0 31 |
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| 33 | +#define MMP2_CLK_I2S1 32 |
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| 29 | 34 | |
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| 30 | 35 | /* apb periphrals */ |
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| 31 | 36 | #define MMP2_CLK_TWSI0 60 |
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| 50 | 55 | #define MMP2_CLK_SSP2 79 |
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| 51 | 56 | #define MMP2_CLK_SSP3 80 |
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| 52 | 57 | #define MMP2_CLK_TIMER 81 |
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| 58 | +#define MMP2_CLK_THERMAL0 82 |
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| 59 | +#define MMP3_CLK_THERMAL1 83 |
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| 60 | +#define MMP3_CLK_THERMAL2 84 |
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| 61 | +#define MMP3_CLK_THERMAL3 85 |
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| 53 | 62 | |
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| 54 | 63 | /* axi periphrals */ |
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| 55 | 64 | #define MMP2_CLK_SDH0 101 |
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| 71 | 80 | #define MMP2_CLK_CCIC1_MIX 117 |
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| 72 | 81 | #define MMP2_CLK_CCIC1_PHY 118 |
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| 73 | 82 | #define MMP2_CLK_CCIC1_SPHY 119 |
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| 83 | +#define MMP2_CLK_DISP0_LCDC 120 |
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| 84 | +#define MMP2_CLK_USBHSIC0 121 |
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| 85 | +#define MMP2_CLK_USBHSIC1 122 |
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| 86 | +#define MMP2_CLK_GPU_BUS 123 |
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| 87 | +#define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS |
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| 88 | +#define MMP2_CLK_GPU_3D 124 |
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| 89 | +#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D |
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| 90 | +#define MMP3_CLK_GPU_2D 125 |
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| 91 | +#define MMP3_CLK_SDH4 126 |
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| 92 | +#define MMP2_CLK_AUDIO 127 |
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| 74 | 93 | |
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| 75 | 94 | #define MMP2_NR_CLKS 200 |
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| 76 | 95 | #endif |
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