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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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| 3 | 4 | * Copyright (c) 2016 Krzysztof Kozlowski |
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| 4 | 5 | * |
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| 5 | | - * This program is free software; you can redistribute it and/or modify |
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| 6 | | - * it under the terms of the GNU General Public License version 2 as |
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| 7 | | - * published by the Free Software Foundation. |
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| 8 | | - * |
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| 9 | 6 | * Device Tree binding constants for Exynos5421 clock controller. |
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| 10 | | -*/ |
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| 7 | + */ |
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| 11 | 8 | |
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| 12 | 9 | #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H |
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| 13 | 10 | #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H |
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| .. | .. |
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| 39 | 36 | #define CLK_UART0 257 |
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| 40 | 37 | #define CLK_UART1 258 |
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| 41 | 38 | #define CLK_UART2 259 |
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| 39 | +#define CLK_UART3 260 |
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| 42 | 40 | #define CLK_I2C0 261 |
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| 43 | 41 | #define CLK_I2C1 262 |
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| 44 | 42 | #define CLK_I2C2 263 |
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| .. | .. |
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| 47 | 45 | #define CLK_USI1 266 |
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| 48 | 46 | #define CLK_USI2 267 |
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| 49 | 47 | #define CLK_USI3 268 |
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| 50 | | -#define CLK_UART3 260 |
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| 48 | +#define CLK_TSADC 270 |
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| 51 | 49 | #define CLK_PWM 279 |
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| 52 | 50 | #define CLK_MCT 315 |
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| 53 | 51 | #define CLK_WDT 316 |
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