debug lk

hc

2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077

 kernel/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
..
..
@@ -11,8 +11,10 @@
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11
 #include <linux/bitfield.h>
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 #include <linux/regmap.h>
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 #include <linux/mfd/syscon.h>
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+#include <linux/of_device.h>
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 #include <linux/reset.h>
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 #include <linux/clk.h>
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+#include <linux/module.h>
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18
 
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 /* AO Offsets */
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20
 
..
..
@@ -26,6 +28,7 @@
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 #define HHI_MEM_PD_REG0			(0x40 << 2)
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 #define HHI_VPU_MEM_PD_REG0		(0x41 << 2)
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 #define HHI_VPU_MEM_PD_REG1		(0x42 << 2)
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+#define HHI_VPU_MEM_PD_REG2		(0x4d << 2)
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32
 
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 struct meson_gx_pwrc_vpu {
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 	struct generic_pm_domain genpd;
..
..
@@ -59,6 +62,49 @@
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 	}
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 	for (i = 0; i < 32; i += 2) {
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 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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+				   0x3 << i, 0x3 << i);
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+		udelay(5);
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+	}
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+	for (i = 8; i < 16; i++) {
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+		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
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+				   BIT(i), BIT(i));
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+		udelay(5);
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+	}
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+	udelay(20);
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+
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+	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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+			   GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
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+
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+	msleep(20);
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+
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+	clk_disable_unprepare(pd->vpu_clk);
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+	clk_disable_unprepare(pd->vapb_clk);
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+
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+	return 0;
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+}
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+
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+static int meson_g12a_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
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+{
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+	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
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+	int i;
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+
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+	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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+			   GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
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+	udelay(20);
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+
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+	/* Power Down Memories */
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+	for (i = 0; i < 32; i += 2) {
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+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
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+				   0x3 << i, 0x3 << i);
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+		udelay(5);
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+	}
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+	for (i = 0; i < 32; i += 2) {
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+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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+				   0x3 << i, 0x3 << i);
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+		udelay(5);
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+	}
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+	for (i = 0; i < 32; i += 2) {
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+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
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 				   0x3 << i, 0x3 << i);
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 		udelay(5);
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 	}
..
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@@ -143,6 +189,60 @@
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 	return 0;
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 }
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191
 
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+static int meson_g12a_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
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+{
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+	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
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+	int ret;
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+	int i;
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+
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+	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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+			   GEN_PWR_VPU_HDMI, 0);
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+	udelay(20);
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+
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+	/* Power Up Memories */
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+	for (i = 0; i < 32; i += 2) {
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+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
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+				   0x3 << i, 0);
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+		udelay(5);
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+	}
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+
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+	for (i = 0; i < 32; i += 2) {
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+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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+				   0x3 << i, 0);
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+		udelay(5);
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+	}
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+
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+	for (i = 0; i < 32; i += 2) {
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+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
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+				   0x3 << i, 0);
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+		udelay(5);
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+	}
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+
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+	for (i = 8; i < 16; i++) {
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+		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
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+				   BIT(i), 0);
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+		udelay(5);
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+	}
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+	udelay(20);
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+
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+	ret = reset_control_assert(pd->rstc);
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+	if (ret)
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+		return ret;
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+
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+	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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+			   GEN_PWR_VPU_HDMI_ISO, 0);
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+
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+	ret = reset_control_deassert(pd->rstc);
236
+	if (ret)
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+		return ret;
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+
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+	ret = meson_gx_pwrc_vpu_setup_clk(pd);
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+	if (ret)
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+		return ret;
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+
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+	return 0;
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+}
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+
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 static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
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 {
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 	u32 reg;
..
..
@@ -160,14 +260,36 @@
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 	},
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 };
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262
 
263
+static struct meson_gx_pwrc_vpu vpu_hdmi_pd_g12a = {
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+	.genpd = {
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+		.name = "vpu_hdmi",
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+		.power_off = meson_g12a_pwrc_vpu_power_off,
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+		.power_on = meson_g12a_pwrc_vpu_power_on,
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+	},
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+};
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+
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 static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
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 {
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+	const struct meson_gx_pwrc_vpu *vpu_pd_match;
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 	struct regmap *regmap_ao, *regmap_hhi;
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+	struct meson_gx_pwrc_vpu *vpu_pd;
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 	struct reset_control *rstc;
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 	struct clk *vpu_clk;
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 	struct clk *vapb_clk;
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 	bool powered_off;
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 	int ret;
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+
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+	vpu_pd_match = of_device_get_match_data(&pdev->dev);
283
+	if (!vpu_pd_match) {
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+		dev_err(&pdev->dev, "failed to get match data\n");
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+		return -ENODEV;
286
+	}
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+
288
+	vpu_pd = devm_kzalloc(&pdev->dev, sizeof(*vpu_pd), GFP_KERNEL);
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+	if (!vpu_pd)
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+		return -ENOMEM;
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+
292
+	memcpy(vpu_pd, vpu_pd_match, sizeof(*vpu_pd));
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293
 
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 	regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
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 	if (IS_ERR(regmap_ao)) {
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@@ -201,41 +323,49 @@
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 		return PTR_ERR(vapb_clk);
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324
 	}
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325
 
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-	vpu_hdmi_pd.regmap_ao = regmap_ao;
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-	vpu_hdmi_pd.regmap_hhi = regmap_hhi;
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-	vpu_hdmi_pd.rstc = rstc;
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-	vpu_hdmi_pd.vpu_clk = vpu_clk;
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-	vpu_hdmi_pd.vapb_clk = vapb_clk;
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+	vpu_pd->regmap_ao = regmap_ao;
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+	vpu_pd->regmap_hhi = regmap_hhi;
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+	vpu_pd->rstc = rstc;
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+	vpu_pd->vpu_clk = vpu_clk;
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+	vpu_pd->vapb_clk = vapb_clk;
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331
 
210
-	powered_off = meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd);
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+	platform_set_drvdata(pdev, vpu_pd);
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+
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+	powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
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335
 
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 	/* If already powered, sync the clock states */
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 	if (!powered_off) {
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-		ret = meson_gx_pwrc_vpu_setup_clk(&vpu_hdmi_pd);
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+		ret = meson_gx_pwrc_vpu_setup_clk(vpu_pd);
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339
 		if (ret)
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 			return ret;
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 	}
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342
 
219
-	pm_genpd_init(&vpu_hdmi_pd.genpd, &pm_domain_always_on_gov,
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-		      powered_off);
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+	vpu_pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
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+	pm_genpd_init(&vpu_pd->genpd, NULL, powered_off);
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345
 
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 	return of_genpd_add_provider_simple(pdev->dev.of_node,
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-					    &vpu_hdmi_pd.genpd);
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+					    &vpu_pd->genpd);
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 }
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349
 
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 static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
227
351
 {
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+	struct meson_gx_pwrc_vpu *vpu_pd = platform_get_drvdata(pdev);
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353
 	bool powered_off;
229
354
 
230
-	powered_off = meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd);
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+	powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
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 	if (!powered_off)
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-		meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
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+		vpu_pd->genpd.power_off(&vpu_pd->genpd);
233
358
 }
234
359
 
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360
 static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
236
-	{ .compatible = "amlogic,meson-gx-pwrc-vpu" },
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+	{ .compatible = "amlogic,meson-gx-pwrc-vpu", .data = &vpu_hdmi_pd },
362
+	{
363
+	  .compatible = "amlogic,meson-g12a-pwrc-vpu",
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+	  .data = &vpu_hdmi_pd_g12a
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+	},
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 	{ /* sentinel */ }
238
367
 };
368
+MODULE_DEVICE_TABLE(of, meson_gx_pwrc_vpu_match_table);
239
369
 
240
370
 static struct platform_driver meson_gx_pwrc_vpu_driver = {
241
371
 	.probe	= meson_gx_pwrc_vpu_probe,
..
..
@@ -245,4 +375,5 @@
245
375
 		.of_match_table	= meson_gx_pwrc_vpu_match_table,
246
376
 	},
247
377
 };
248
-builtin_platform_driver(meson_gx_pwrc_vpu_driver);
378
+module_platform_driver(meson_gx_pwrc_vpu_driver);
379
+MODULE_LICENSE("GPL v2");