| .. | .. |
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| 49 | 49 | REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */ |
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| 50 | 50 | REG_TSCU_TSUCTRL = 0x2000, /* TSCU control register */ |
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| 51 | 51 | REG_TSCU_TSCUSTAT = 0x2004, /* TSCU status register */ |
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| 52 | + |
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| 53 | + /* Common Capture Sequencer (CTS) registers */ |
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| 54 | + REG_CTS_C0S0_EN = 0x30c0, /* clause_event_enable_c0s0 */ |
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| 55 | + REG_CTS_C0S0_ACT = 0x3180, /* clause_action_control_c0s0 */ |
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| 56 | + REG_CTS_STAT = 0x32a0, /* cts_status */ |
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| 57 | + REG_CTS_CTL = 0x32a4, /* cts_control */ |
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| 52 | 58 | }; |
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| 53 | 59 | |
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| 54 | 60 | /* waiting for Pipeline Empty bit(s) to assert for GTH */ |
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| .. | .. |
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| 57 | 63 | #define TSUCTRL_CTCRESYNC BIT(0) |
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| 58 | 64 | #define TSCUSTAT_CTCSYNCING BIT(1) |
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| 59 | 65 | |
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| 66 | +/* waiting for Trigger status to assert for CTS */ |
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| 67 | +#define CTS_TRIG_WAITLOOP_DEPTH 10000 |
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| 68 | + |
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| 69 | +#define CTS_EVENT_ENABLE_IF_ANYTHING BIT(31) |
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| 70 | +#define CTS_ACTION_CONTROL_STATE_OFF 27 |
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| 71 | +#define CTS_ACTION_CONTROL_SET_STATE(x) \ |
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| 72 | + (((x) & 0x1f) << CTS_ACTION_CONTROL_STATE_OFF) |
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| 73 | +#define CTS_ACTION_CONTROL_TRIGGER BIT(4) |
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| 74 | + |
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| 75 | +#define CTS_STATE_IDLE 0x10u |
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| 76 | + |
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| 77 | +#define CTS_CTL_SEQUENCER_ENABLE BIT(0) |
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| 78 | + |
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| 60 | 79 | #endif /* __INTEL_TH_GTH_H__ */ |
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