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2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077 
 kernel/drivers/gpu/arm/bifrost/ipa/backend/mali_kbase_ipa_counter_csf.c
....@@ -1,7 +1,7 @@
11 // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
22 /*
33  *
4
- * (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
4
+ * (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
55  *
66  * This program is free software and is provided to you under the terms of the
77  * GNU General Public License version 2 as published by the Free Software
....@@ -23,27 +23,42 @@
2323 #include "mali_kbase.h"
2424 
2525 /* MEMSYS counter block offsets */
26
+#define L2_RD_MSG_IN_CU         (13)
2627 #define L2_RD_MSG_IN            (16)
2728 #define L2_WR_MSG_IN            (18)
29
+#define L2_SNP_MSG_IN           (20)
30
+#define L2_RD_MSG_OUT           (22)
2831 #define L2_READ_LOOKUP          (26)
32
+#define L2_EXT_READ_NOSNP       (30)
2933 #define L2_EXT_WRITE_NOSNP_FULL (43)
3034 
3135 /* SC counter block offsets */
36
+#define FRAG_STARVING           (8)
37
+#define FRAG_PARTIAL_QUADS_RAST (10)
3238 #define FRAG_QUADS_EZS_UPDATE   (13)
3339 #define FULL_QUAD_WARPS         (21)
3440 #define EXEC_INSTR_FMA          (27)
3541 #define EXEC_INSTR_CVT          (28)
42
+#define EXEC_INSTR_SFU          (29)
43
+#define EXEC_INSTR_MSG          (30)
3644 #define TEX_FILT_NUM_OPS        (39)
3745 #define LS_MEM_READ_SHORT       (45)
3846 #define LS_MEM_WRITE_SHORT      (47)
3947 #define VARY_SLOT_16            (51)
48
+#define BEATS_RD_LSC_EXT        (57)
49
+#define BEATS_RD_TEX            (58)
50
+#define BEATS_RD_TEX_EXT        (59)
51
+#define FRAG_QUADS_COARSE       (68)
4052 
4153 /* Tiler counter block offsets */
4254 #define IDVS_POS_SHAD_STALL     (23)
4355 #define PREFETCH_STALL          (25)
4456 #define VFETCH_POS_READ_WAIT    (29)
4557 #define VFETCH_VERTEX_WAIT      (30)
58
+#define PRIMASSY_STALL          (32)
4659 #define IDVS_VAR_SHAD_STALL     (38)
60
+#define ITER_STALL              (40)
61
+#define PMGR_PTR_RD_STALL       (48)
4762 
4863 #define COUNTER_DEF(cnt_name, coeff, cnt_idx, block_type)	\
4964 	{							\
....@@ -52,9 +67,6 @@
5267 		.counter_block_offset = cnt_idx,		\
5368 		.counter_block_type = block_type,		\
5469 	}
55
-
56
-#define CSHW_COUNTER_DEF(cnt_name, coeff, cnt_idx)	\
57
-	COUNTER_DEF(cnt_name, coeff, cnt_idx, KBASE_IPA_CORE_TYPE_CSHW)
5870 
5971 #define MEMSYS_COUNTER_DEF(cnt_name, coeff, cnt_idx)	\
6072 	COUNTER_DEF(cnt_name, coeff, cnt_idx, KBASE_IPA_CORE_TYPE_MEMSYS)
....@@ -80,10 +92,46 @@
8092 	TILER_COUNTER_DEF("vfetch_pos_read_wait", -119118, VFETCH_POS_READ_WAIT),
8193 };
8294 
95
+static const struct kbase_ipa_counter ipa_top_level_cntrs_def_tgrx[] = {
96
+	MEMSYS_COUNTER_DEF("l2_rd_msg_in", 295631, L2_RD_MSG_IN),
97
+	MEMSYS_COUNTER_DEF("l2_ext_write_nosnp_ull", 325168, L2_EXT_WRITE_NOSNP_FULL),
98
+
99
+	TILER_COUNTER_DEF("prefetch_stall", 145435, PREFETCH_STALL),
100
+	TILER_COUNTER_DEF("idvs_var_shad_stall", -171917, IDVS_VAR_SHAD_STALL),
101
+	TILER_COUNTER_DEF("idvs_pos_shad_stall", 109980, IDVS_POS_SHAD_STALL),
102
+	TILER_COUNTER_DEF("vfetch_pos_read_wait", -119118, VFETCH_POS_READ_WAIT),
103
+};
104
+
105
+static const struct kbase_ipa_counter ipa_top_level_cntrs_def_tvax[] = {
106
+	MEMSYS_COUNTER_DEF("l2_rd_msg_out", 491414, L2_RD_MSG_OUT),
107
+	MEMSYS_COUNTER_DEF("l2_wr_msg_in", 408645, L2_WR_MSG_IN),
108
+
109
+	TILER_COUNTER_DEF("iter_stall", 893324, ITER_STALL),
110
+	TILER_COUNTER_DEF("pmgr_ptr_rd_stall", -975117, PMGR_PTR_RD_STALL),
111
+	TILER_COUNTER_DEF("idvs_pos_shad_stall", 22555, IDVS_POS_SHAD_STALL),
112
+};
113
+
114
+static const struct kbase_ipa_counter ipa_top_level_cntrs_def_ttux[] = {
115
+	MEMSYS_COUNTER_DEF("l2_rd_msg_in", 800836, L2_RD_MSG_IN),
116
+	MEMSYS_COUNTER_DEF("l2_wr_msg_in", 415579, L2_WR_MSG_IN),
117
+	MEMSYS_COUNTER_DEF("l2_read_lookup", -198124, L2_READ_LOOKUP),
118
+
119
+	TILER_COUNTER_DEF("idvs_pos_shad_stall", 117358, IDVS_POS_SHAD_STALL),
120
+	TILER_COUNTER_DEF("vfetch_vertex_wait", -391964, VFETCH_VERTEX_WAIT),
121
+};
122
+
123
+static const struct kbase_ipa_counter ipa_top_level_cntrs_def_ttix[] = {
124
+	TILER_COUNTER_DEF("primassy_stall", 471953, PRIMASSY_STALL),
125
+	TILER_COUNTER_DEF("idvs_var_shad_stall", -460559, IDVS_VAR_SHAD_STALL),
126
+
127
+	MEMSYS_COUNTER_DEF("l2_rd_msg_in_cu", -6189604, L2_RD_MSG_IN_CU),
128
+	MEMSYS_COUNTER_DEF("l2_snp_msg_in", 6289609, L2_SNP_MSG_IN),
129
+	MEMSYS_COUNTER_DEF("l2_ext_read_nosnp", 512341, L2_EXT_READ_NOSNP),
130
+};
83131 
84132 /* These tables provide a description of each performance counter
85
-  * used by the shader cores counter model for energy estimation.
86
-  */
133
+ * used by the shader cores counter model for energy estimation.
134
+ */
87135 static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_todx[] = {
88136 	SC_COUNTER_DEF("exec_instr_fma", 505449, EXEC_INSTR_FMA),
89137 	SC_COUNTER_DEF("tex_filt_num_operations", 574869, TEX_FILT_NUM_OPS),
....@@ -93,6 +141,43 @@
93141 	SC_COUNTER_DEF("vary_slot_16", 181069, VARY_SLOT_16),
94142 };
95143 
144
+static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_tgrx[] = {
145
+	SC_COUNTER_DEF("exec_instr_fma", 505449, EXEC_INSTR_FMA),
146
+	SC_COUNTER_DEF("tex_filt_num_operations", 574869, TEX_FILT_NUM_OPS),
147
+	SC_COUNTER_DEF("ls_mem_read_short", 60917, LS_MEM_READ_SHORT),
148
+	SC_COUNTER_DEF("frag_quads_ezs_update", 694555, FRAG_QUADS_EZS_UPDATE),
149
+	SC_COUNTER_DEF("ls_mem_write_short", 698290, LS_MEM_WRITE_SHORT),
150
+	SC_COUNTER_DEF("vary_slot_16", 181069, VARY_SLOT_16),
151
+};
152
+
153
+static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_tvax[] = {
154
+	SC_COUNTER_DEF("tex_filt_num_operations", 142536, TEX_FILT_NUM_OPS),
155
+	SC_COUNTER_DEF("exec_instr_fma", 243497, EXEC_INSTR_FMA),
156
+	SC_COUNTER_DEF("exec_instr_msg", 1344410, EXEC_INSTR_MSG),
157
+	SC_COUNTER_DEF("vary_slot_16", -119612, VARY_SLOT_16),
158
+	SC_COUNTER_DEF("frag_partial_quads_rast", 676201, FRAG_PARTIAL_QUADS_RAST),
159
+	SC_COUNTER_DEF("frag_starving", 62421, FRAG_STARVING),
160
+};
161
+
162
+static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_ttux[] = {
163
+	SC_COUNTER_DEF("exec_instr_fma", 457012, EXEC_INSTR_FMA),
164
+	SC_COUNTER_DEF("tex_filt_num_operations", 441911, TEX_FILT_NUM_OPS),
165
+	SC_COUNTER_DEF("ls_mem_read_short", 322525, LS_MEM_READ_SHORT),
166
+	SC_COUNTER_DEF("full_quad_warps", 844124, FULL_QUAD_WARPS),
167
+	SC_COUNTER_DEF("exec_instr_cvt", 226411, EXEC_INSTR_CVT),
168
+	SC_COUNTER_DEF("frag_quads_ezs_update", 372032, FRAG_QUADS_EZS_UPDATE),
169
+};
170
+
171
+static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_ttix[] = {
172
+	SC_COUNTER_DEF("exec_instr_fma", 192642, EXEC_INSTR_FMA),
173
+	SC_COUNTER_DEF("exec_instr_msg", 1326465, EXEC_INSTR_MSG),
174
+	SC_COUNTER_DEF("beats_rd_tex", 163518, BEATS_RD_TEX),
175
+	SC_COUNTER_DEF("beats_rd_lsc_ext", 127475, BEATS_RD_LSC_EXT),
176
+	SC_COUNTER_DEF("frag_quads_coarse", -36247, FRAG_QUADS_COARSE),
177
+	SC_COUNTER_DEF("ls_mem_write_short", 51547, LS_MEM_WRITE_SHORT),
178
+	SC_COUNTER_DEF("beats_rd_tex_ext", -43370, BEATS_RD_TEX_EXT),
179
+	SC_COUNTER_DEF("exec_instr_sfu", 31583, EXEC_INSTR_SFU),
180
+};
96181 
97182 #define IPA_POWER_MODEL_OPS(gpu, init_token) \
98183 	const struct kbase_ipa_model_ops kbase_ ## gpu ## _ipa_model_ops = { \
....@@ -125,16 +210,28 @@
125210 #define ALIAS_POWER_MODEL(gpu, as_gpu) \
126211 	IPA_POWER_MODEL_OPS(gpu, as_gpu)
127212 
128
-/* Reference voltage value is 750 mV.
129
- */
213
+/* Reference voltage value is 750 mV. */
130214 STANDARD_POWER_MODEL(todx, 750);
131
-
215
+STANDARD_POWER_MODEL(tgrx, 750);
216
+STANDARD_POWER_MODEL(tvax, 750);
217
+STANDARD_POWER_MODEL(ttux, 750);
218
+/* Reference voltage value is 550 mV. */
219
+STANDARD_POWER_MODEL(ttix, 550);
132220 
133221 /* Assuming LODX is an alias of TODX for IPA */
134222 ALIAS_POWER_MODEL(lodx, todx);
135223 
224
+/* Assuming LTUX is an alias of TTUX for IPA */
225
+ALIAS_POWER_MODEL(ltux, ttux);
226
+
227
+/* Assuming LTUX is an alias of TTUX for IPA */
228
+ALIAS_POWER_MODEL(ltix, ttix);
229
+
136230 static const struct kbase_ipa_model_ops *ipa_counter_model_ops[] = {
137231 	&kbase_todx_ipa_model_ops, &kbase_lodx_ipa_model_ops,
232
+	&kbase_tgrx_ipa_model_ops, &kbase_tvax_ipa_model_ops,
233
+	&kbase_ttux_ipa_model_ops, &kbase_ltux_ipa_model_ops,
234
+	&kbase_ttix_ipa_model_ops, &kbase_ltix_ipa_model_ops,
138235 };
139236 
140237 const struct kbase_ipa_model_ops *kbase_ipa_counter_model_ops_find(
....@@ -157,14 +254,26 @@
157254 
158255 const char *kbase_ipa_counter_model_name_from_id(u32 gpu_id)
159256 {
160
-	const u32 prod_id = (gpu_id & GPU_ID_VERSION_PRODUCT_ID) >>
161
-			GPU_ID_VERSION_PRODUCT_ID_SHIFT;
257
+	const u32 prod_id =
258
+		(gpu_id & GPU_ID_VERSION_PRODUCT_ID) >> KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT;
162259 
163260 	switch (GPU_ID2_MODEL_MATCH_VALUE(prod_id)) {
164261 	case GPU_ID2_PRODUCT_TODX:
165262 		return "mali-todx-power-model";
166263 	case GPU_ID2_PRODUCT_LODX:
167264 		return "mali-lodx-power-model";
265
+	case GPU_ID2_PRODUCT_TGRX:
266
+		return "mali-tgrx-power-model";
267
+	case GPU_ID2_PRODUCT_TVAX:
268
+		return "mali-tvax-power-model";
269
+	case GPU_ID2_PRODUCT_TTUX:
270
+		return "mali-ttux-power-model";
271
+	case GPU_ID2_PRODUCT_LTUX:
272
+		return "mali-ltux-power-model";
273
+	case GPU_ID2_PRODUCT_TTIX:
274
+		return "mali-ttix-power-model";
275
+	case GPU_ID2_PRODUCT_LTIX:
276
+		return "mali-ltix-power-model";
168277 	default:
169278 		return NULL;
170279 	}