forked from ~ljy/RK356X_SDK_RELEASE

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2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077 
 kernel/drivers/gpio/gpio-pch.c
....@@ -1,33 +1,22 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License as published by
6
- * the Free Software Foundation; version 2 of the License.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
12
- *
13
- * You should have received a copy of the GNU General Public License
14
- * along with this program; if not, write to the Free Software
15
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
164  */
17
-#include <linux/module.h>
18
-#include <linux/kernel.h>
19
-#include <linux/pci.h>
5
+#include <linux/bits.h>
206 #include <linux/gpio/driver.h>
217 #include <linux/interrupt.h>
228 #include <linux/irq.h>
9
+#include <linux/kernel.h>
10
+#include <linux/module.h>
11
+#include <linux/pci.h>
2312 #include <linux/slab.h>
2413 
2514 #define PCH_EDGE_FALLING	0
26
-#define PCH_EDGE_RISING		BIT(0)
27
-#define PCH_LEVEL_L		BIT(1)
28
-#define PCH_LEVEL_H		(BIT(0) | BIT(1))
29
-#define PCH_EDGE_BOTH		BIT(2)
30
-#define PCH_IM_MASK		(BIT(0) | BIT(1) | BIT(2))
15
+#define PCH_EDGE_RISING		1
16
+#define PCH_LEVEL_L		2
17
+#define PCH_LEVEL_H		3
18
+#define PCH_EDGE_BOTH		4
19
+#define PCH_IM_MASK		GENMASK(2, 0)
3120 
3221 #define PCH_IRQ_BASE		24
3322 
....@@ -106,7 +95,7 @@
10695 	spinlock_t spinlock;
10796 };
10897 
109
-static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
98
+static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
11099 {
111100 	u32 reg_val;
112101 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
....@@ -115,22 +104,22 @@
115104 	spin_lock_irqsave(&chip->spinlock, flags);
116105 	reg_val = ioread32(&chip->reg->po);
117106 	if (val)
118
-		reg_val |= (1 << nr);
107
+		reg_val |= BIT(nr);
119108 	else
120
-		reg_val &= ~(1 << nr);
109
+		reg_val &= ~BIT(nr);
121110 
122111 	iowrite32(reg_val, &chip->reg->po);
123112 	spin_unlock_irqrestore(&chip->spinlock, flags);
124113 }
125114 
126
-static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
115
+static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
127116 {
128117 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
129118 
130
-	return (ioread32(&chip->reg->pi) >> nr) & 1;
119
+	return !!(ioread32(&chip->reg->pi) & BIT(nr));
131120 }
132121 
133
-static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
122
+static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
134123 				     int val)
135124 {
136125 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
....@@ -142,13 +131,14 @@
142131 
143132 	reg_val = ioread32(&chip->reg->po);
144133 	if (val)
145
-		reg_val |= (1 << nr);
134
+		reg_val |= BIT(nr);
146135 	else
147
-		reg_val &= ~(1 << nr);
136
+		reg_val &= ~BIT(nr);
148137 	iowrite32(reg_val, &chip->reg->po);
149138 
150
-	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
151
-	pm |= (1 << nr);
139
+	pm = ioread32(&chip->reg->pm);
140
+	pm &= BIT(gpio_pins[chip->ioh]) - 1;
141
+	pm |= BIT(nr);
152142 	iowrite32(pm, &chip->reg->pm);
153143 
154144 	spin_unlock_irqrestore(&chip->spinlock, flags);
....@@ -156,26 +146,26 @@
156146 	return 0;
157147 }
158148 
159
-static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
149
+static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
160150 {
161151 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
162152 	u32 pm;
163153 	unsigned long flags;
164154 
165155 	spin_lock_irqsave(&chip->spinlock, flags);
166
-	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
167
-	pm &= ~(1 << nr);
156
+	pm = ioread32(&chip->reg->pm);
157
+	pm &= BIT(gpio_pins[chip->ioh]) - 1;
158
+	pm &= ~BIT(nr);
168159 	iowrite32(pm, &chip->reg->pm);
169160 	spin_unlock_irqrestore(&chip->spinlock, flags);
170161 
171162 	return 0;
172163 }
173164 
174
-#ifdef CONFIG_PM
175165 /*
176166  * Save register configuration and disable interrupts.
177167  */
178
-static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
168
+static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
179169 {
180170 	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
181171 	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
....@@ -185,14 +175,13 @@
185175 	if (chip->ioh == INTEL_EG20T_PCH)
186176 		chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
187177 	if (chip->ioh == OKISEMI_ML7223n_IOH)
188
-		chip->pch_gpio_reg.gpio_use_sel_reg =\
189
-					    ioread32(&chip->reg->gpio_use_sel);
178
+		chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
190179 }
191180 
192181 /*
193182  * This function restores the register configuration of the GPIO device.
194183  */
195
-static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
184
+static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
196185 {
197186 	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
198187 	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
....@@ -204,14 +193,13 @@
204193 	if (chip->ioh == INTEL_EG20T_PCH)
205194 		iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
206195 	if (chip->ioh == OKISEMI_ML7223n_IOH)
207
-		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
208
-			  &chip->reg->gpio_use_sel);
196
+		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
209197 }
210
-#endif
211198 
212
-static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
199
+static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
213200 {
214201 	struct pch_gpio *chip = gpiochip_get_data(gpio);
202
+
215203 	return chip->irq_base + offset;
216204 }
217205 
....@@ -226,7 +214,6 @@
226214 	gpio->get = pch_gpio_get;
227215 	gpio->direction_output = pch_gpio_direction_output;
228216 	gpio->set = pch_gpio_set;
229
-	gpio->dbg_show = NULL;
230217 	gpio->base = -1;
231218 	gpio->ngpio = gpio_pins[chip->ioh];
232219 	gpio->can_sleep = false;
....@@ -243,17 +230,14 @@
243230 	int ch, irq = d->irq;
244231 
245232 	ch = irq - chip->irq_base;
246
-	if (irq <= chip->irq_base + 7) {
233
+	if (irq < chip->irq_base + 8) {
247234 		im_reg = &chip->reg->im0;
248
-		im_pos = ch;
235
+		im_pos = ch - 0;
249236 	} else {
250237 		im_reg = &chip->reg->im1;
251238 		im_pos = ch - 8;
252239 	}
253
-	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
254
-		__func__, irq, type, ch, im_pos);
255
-
256
-	spin_lock_irqsave(&chip->spinlock, flags);
240
+	dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
257241 
258242 	switch (type) {
259243 	case IRQ_TYPE_EDGE_RISING:
....@@ -272,20 +256,21 @@
272256 		val = PCH_LEVEL_L;
273257 		break;
274258 	default:
275
-		goto unlock;
259
+		return 0;
276260 	}
261
+
262
+	spin_lock_irqsave(&chip->spinlock, flags);
277263 
278264 	/* Set interrupt mode */
279265 	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
280266 	iowrite32(im | (val << (im_pos * 4)), im_reg);
281267 
282268 	/* And the handler */
283
-	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
269
+	if (type & IRQ_TYPE_LEVEL_MASK)
284270 		irq_set_handler_locked(d, handle_level_irq);
285
-	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
271
+	else if (type & IRQ_TYPE_EDGE_BOTH)
286272 		irq_set_handler_locked(d, handle_edge_irq);
287273 
288
-unlock:
289274 	spin_unlock_irqrestore(&chip->spinlock, flags);
290275 	return 0;
291276 }
....@@ -295,7 +280,7 @@
295280 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
296281 	struct pch_gpio *chip = gc->private;
297282 
298
-	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
283
+	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
299284 }
300285 
301286 static void pch_irq_mask(struct irq_data *d)
....@@ -303,7 +288,7 @@
303288 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
304289 	struct pch_gpio *chip = gc->private;
305290 
306
-	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
291
+	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
307292 }
308293 
309294 static void pch_irq_ack(struct irq_data *d)
....@@ -311,24 +296,23 @@
311296 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
312297 	struct pch_gpio *chip = gc->private;
313298 
314
-	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
299
+	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
315300 }
316301 
317302 static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
318303 {
319304 	struct pch_gpio *chip = dev_id;
320
-	u32 reg_val = ioread32(&chip->reg->istatus);
321
-	int i, ret = IRQ_NONE;
305
+	unsigned long reg_val = ioread32(&chip->reg->istatus);
306
+	int i;
322307 
323
-	for (i = 0; i < gpio_pins[chip->ioh]; i++) {
324
-		if (reg_val & BIT(i)) {
325
-			dev_dbg(chip->dev, "%s:[%d]:irq=%d  status=0x%x\n",
326
-				__func__, i, irq, reg_val);
327
-			generic_handle_irq(chip->irq_base + i);
328
-			ret = IRQ_HANDLED;
329
-		}
330
-	}
331
-	return ret;
308
+	dev_vdbg(chip->dev, "irq=%d  status=0x%lx\n", irq, reg_val);
309
+
310
+	reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
311
+
312
+	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])
313
+		generic_handle_irq(chip->irq_base + i);
314
+
315
+	return IRQ_RETVAL(reg_val);
332316 }
333317 
334318 static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
....@@ -365,31 +349,25 @@
365349 	s32 ret;
366350 	struct pch_gpio *chip;
367351 	int irq_base;
368
-	u32 msk;
369352 
370
-	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
353
+	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
371354 	if (chip == NULL)
372355 		return -ENOMEM;
373356 
374357 	chip->dev = &pdev->dev;
375
-	ret = pci_enable_device(pdev);
358
+	ret = pcim_enable_device(pdev);
376359 	if (ret) {
377
-		dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
378
-		goto err_pci_enable;
360
+		dev_err(&pdev->dev, "pci_enable_device FAILED");
361
+		return ret;
379362 	}
380363 
381
-	ret = pci_request_regions(pdev, KBUILD_MODNAME);
364
+	ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
382365 	if (ret) {
383366 		dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
384
-		goto err_request_regions;
367
+		return ret;
385368 	}
386369 
387
-	chip->base = pci_iomap(pdev, 1, 0);
388
-	if (!chip->base) {
389
-		dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
390
-		ret = -ENOMEM;
391
-		goto err_iomap;
392
-	}
370
+	chip->base = pcim_iomap_table(pdev)[1];
393371 
394372 	if (pdev->device == 0x8803)
395373 		chip->ioh = INTEL_EG20T_PCH;
....@@ -402,13 +380,11 @@
402380 	pci_set_drvdata(pdev, chip);
403381 	spin_lock_init(&chip->spinlock);
404382 	pch_gpio_setup(chip);
405
-#ifdef CONFIG_OF_GPIO
406
-	chip->gpio.of_node = pdev->dev.of_node;
407
-#endif
408
-	ret = gpiochip_add_data(&chip->gpio, chip);
383
+
384
+	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
409385 	if (ret) {
410386 		dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
411
-		goto err_gpiochip_add;
387
+		return ret;
412388 	}
413389 
414390 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
....@@ -416,100 +392,40 @@
416392 	if (irq_base < 0) {
417393 		dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
418394 		chip->irq_base = -1;
419
-		goto end;
395
+		return 0;
420396 	}
421397 	chip->irq_base = irq_base;
422398 
423399 	/* Mask all interrupts, but enable them */
424
-	msk = (1 << gpio_pins[chip->ioh]) - 1;
425
-	iowrite32(msk, &chip->reg->imask);
426
-	iowrite32(msk, &chip->reg->ien);
400
+	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
401
+	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
427402 
428403 	ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
429404 			       IRQF_SHARED, KBUILD_MODNAME, chip);
430
-	if (ret != 0) {
431
-		dev_err(&pdev->dev,
432
-			"%s request_irq failed\n", __func__);
433
-		goto err_request_irq;
405
+	if (ret) {
406
+		dev_err(&pdev->dev, "request_irq failed\n");
407
+		return ret;
434408 	}
435409 
436
-	ret = pch_gpio_alloc_generic_chip(chip, irq_base,
437
-					  gpio_pins[chip->ioh]);
438
-	if (ret)
439
-		goto err_request_irq;
440
-
441
-end:
442
-	return 0;
443
-
444
-err_request_irq:
445
-	gpiochip_remove(&chip->gpio);
446
-
447
-err_gpiochip_add:
448
-	pci_iounmap(pdev, chip->base);
449
-
450
-err_iomap:
451
-	pci_release_regions(pdev);
452
-
453
-err_request_regions:
454
-	pci_disable_device(pdev);
455
-
456
-err_pci_enable:
457
-	kfree(chip);
458
-	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
459
-	return ret;
410
+	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
460411 }
461412 
462
-static void pch_gpio_remove(struct pci_dev *pdev)
413
+static int __maybe_unused pch_gpio_suspend(struct device *dev)
463414 {
464
-	struct pch_gpio *chip = pci_get_drvdata(pdev);
465
-
466
-	gpiochip_remove(&chip->gpio);
467
-	pci_iounmap(pdev, chip->base);
468
-	pci_release_regions(pdev);
469
-	pci_disable_device(pdev);
470
-	kfree(chip);
471
-}
472
-
473
-#ifdef CONFIG_PM
474
-static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
475
-{
476
-	s32 ret;
477
-	struct pch_gpio *chip = pci_get_drvdata(pdev);
415
+	struct pch_gpio *chip = dev_get_drvdata(dev);
478416 	unsigned long flags;
479417 
480418 	spin_lock_irqsave(&chip->spinlock, flags);
481419 	pch_gpio_save_reg_conf(chip);
482420 	spin_unlock_irqrestore(&chip->spinlock, flags);
483421 
484
-	ret = pci_save_state(pdev);
485
-	if (ret) {
486
-		dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
487
-		return ret;
488
-	}
489
-	pci_disable_device(pdev);
490
-	pci_set_power_state(pdev, PCI_D0);
491
-	ret = pci_enable_wake(pdev, PCI_D0, 1);
492
-	if (ret)
493
-		dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
494
-
495422 	return 0;
496423 }
497424 
498
-static int pch_gpio_resume(struct pci_dev *pdev)
425
+static int __maybe_unused pch_gpio_resume(struct device *dev)
499426 {
500
-	s32 ret;
501
-	struct pch_gpio *chip = pci_get_drvdata(pdev);
427
+	struct pch_gpio *chip = dev_get_drvdata(dev);
502428 	unsigned long flags;
503
-
504
-	ret = pci_enable_wake(pdev, PCI_D0, 0);
505
-
506
-	pci_set_power_state(pdev, PCI_D0);
507
-	ret = pci_enable_device(pdev);
508
-	if (ret) {
509
-		dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
510
-		return ret;
511
-	}
512
-	pci_restore_state(pdev);
513429 
514430 	spin_lock_irqsave(&chip->spinlock, flags);
515431 	iowrite32(0x01, &chip->reg->reset);
....@@ -519,10 +435,8 @@
519435 
520436 	return 0;
521437 }
522
-#else
523
-#define pch_gpio_suspend NULL
524
-#define pch_gpio_resume NULL
525
-#endif
438
+
439
+static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
526440 
527441 static const struct pci_device_id pch_gpio_pcidev_id[] = {
528442 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
....@@ -537,12 +451,12 @@
537451 	.name = "pch_gpio",
538452 	.id_table = pch_gpio_pcidev_id,
539453 	.probe = pch_gpio_probe,
540
-	.remove = pch_gpio_remove,
541
-	.suspend = pch_gpio_suspend,
542
-	.resume = pch_gpio_resume
454
+	.driver = {
455
+		.pm = &pch_gpio_pm_ops,
456
+	},
543457 };
544458 
545459 module_pci_driver(pch_gpio_driver);
546460 
547461 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
548
-MODULE_LICENSE("GPL");
462
+MODULE_LICENSE("GPL v2");