debug lk

hc

2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077

 kernel/drivers/clk/socfpga/clk-pll.c
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@@ -70,17 +70,18 @@
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 	.get_parent = clk_pll_get_parent,
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 };
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-static __init struct clk *__socfpga_pll_init(struct device_node *node,
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+static __init struct clk_hw *__socfpga_pll_init(struct device_node *node,
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 	const struct clk_ops *ops)
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 {
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 	u32 reg;
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-	struct clk *clk;
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+	struct clk_hw *hw_clk;
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 	struct socfpga_pll *pll_clk;
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 	const char *clk_name = node->name;
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 	const char *parent_name[SOCFPGA_MAX_PARENTS];
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 	struct clk_init_data init;
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 	struct device_node *clkmgr_np;
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 	int rc;
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+	int err;
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 	of_property_read_u32(node, "reg", &reg);
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..
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@@ -106,13 +107,15 @@
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 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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-	clk = clk_register(NULL, &pll_clk->hw.hw);
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-	if (WARN_ON(IS_ERR(clk))) {
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+	hw_clk = &pll_clk->hw.hw;
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+
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+	err = clk_hw_register(NULL, hw_clk);
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+	if (err) {
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 		kfree(pll_clk);
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-		return NULL;
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+		return ERR_PTR(err);
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 	}
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-	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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-	return clk;
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+	rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
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+	return hw_clk;
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 }
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 void __init socfpga_pll_init(struct device_node *node)