debug lk

hc

2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077

 kernel/drivers/clk/socfpga/clk-pll-s10.c
..
..
@@ -4,6 +4,7 @@
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4
  */
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 #include <linux/slab.h>
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6
 #include <linux/clk-provider.h>
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+#include <linux/io.h>
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8
 
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 #include "stratix10-clk.h"
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 #include "clk.h"
..
..
@@ -17,14 +18,39 @@
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 #define SOCFPGA_PLL_RESET_MASK		0x2
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 #define SOCFPGA_PLL_REFDIV_MASK		0x00003F00
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 #define SOCFPGA_PLL_REFDIV_SHIFT	8
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+#define SOCFPGA_PLL_AREFDIV_MASK	0x00000F00
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+#define SOCFPGA_PLL_DREFDIV_MASK	0x00003000
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+#define SOCFPGA_PLL_DREFDIV_SHIFT	12
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 #define SOCFPGA_PLL_MDIV_MASK		0xFF000000
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 #define SOCFPGA_PLL_MDIV_SHIFT		24
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+#define SOCFPGA_AGILEX_PLL_MDIV_MASK	0x000003FF
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 #define SWCTRLBTCLKSEL_MASK		0x200
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 #define SWCTRLBTCLKSEL_SHIFT		9
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29
 
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 #define SOCFPGA_BOOT_CLK		"boot_clk"
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31
 
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 #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
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+
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+static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
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+						unsigned long parent_rate)
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+{
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+	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
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+	unsigned long arefdiv, reg, mdiv;
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+	unsigned long long vco_freq;
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+
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+	/* read VCO1 reg for numerator and denominator */
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+	reg = readl(socfpgaclk->hw.reg);
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+	arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
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+
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+	vco_freq = (unsigned long long)parent_rate / arefdiv;
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+
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+	/* Read mdiv and fdiv from the fdbck register */
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+	reg = readl(socfpgaclk->hw.reg + 0x24);
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+	mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;
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+
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+	vco_freq = (unsigned long long)vco_freq * mdiv;
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+	return (unsigned long)vco_freq;
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+}
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54
 
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 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
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56
 					 unsigned long parent_rate)
..
..
@@ -97,31 +123,37 @@
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 	return 0;
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 }
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125
 
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-static struct clk_ops clk_pll_ops = {
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+static const struct clk_ops agilex_clk_pll_ops = {
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+	.recalc_rate = agilex_clk_pll_recalc_rate,
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+	.get_parent = clk_pll_get_parent,
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+	.prepare = clk_pll_prepare,
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+};
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+
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+static const struct clk_ops clk_pll_ops = {
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 	.recalc_rate = clk_pll_recalc_rate,
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 	.get_parent = clk_pll_get_parent,
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 	.prepare = clk_pll_prepare,
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136
 };
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137
 
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-static struct clk_ops clk_boot_ops = {
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+static const struct clk_ops clk_boot_ops = {
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 	.recalc_rate = clk_boot_clk_recalc_rate,
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 	.get_parent = clk_boot_get_parent,
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 	.prepare = clk_pll_prepare,
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 };
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143
 
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-struct clk *s10_register_pll(const char *name, const char * const *parent_names,
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-				    u8 num_parents, unsigned long flags,
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-				    void __iomem *reg, unsigned long offset)
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+struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
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+			     void __iomem *reg)
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 {
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 	struct clk *clk;
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 	struct socfpga_pll *pll_clk;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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+	const char *name = clks->name;
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151
 
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 	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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 	if (WARN_ON(!pll_clk))
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 		return NULL;
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-	pll_clk->hw.reg = reg + offset;
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+	pll_clk->hw.reg = reg + clks->offset;
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157
 
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 	if (streq(name, SOCFPGA_BOOT_CLK))
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 		init.ops = &clk_boot_ops;
..
..
@@ -129,15 +161,51 @@
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 		init.ops = &clk_pll_ops;
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162
 
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 	init.name = name;
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-	init.flags = flags;
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+	init.flags = clks->flags;
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165
 
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-	init.num_parents = num_parents;
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-	init.parent_names = parent_names;
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+	init.num_parents = clks->num_parents;
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+	init.parent_names = NULL;
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+	init.parent_data = clks->parent_data;
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 	pll_clk->hw.hw.init = &init;
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170
 
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 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
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-	clk_pll_ops.enable = clk_gate_ops.enable;
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-	clk_pll_ops.disable = clk_gate_ops.disable;
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+
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+	clk = clk_register(NULL, &pll_clk->hw.hw);
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+	if (WARN_ON(IS_ERR(clk))) {
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+		kfree(pll_clk);
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+		return NULL;
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+	}
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+	return clk;
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+}
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+
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+struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
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+				void __iomem *reg)
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+{
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+	struct clk *clk;
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+	struct socfpga_pll *pll_clk;
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+	struct clk_init_data init;
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+	const char *name = clks->name;
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+
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+	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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+	if (WARN_ON(!pll_clk))
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+		return NULL;
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+
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+	pll_clk->hw.reg = reg + clks->offset;
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+
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+	if (streq(name, SOCFPGA_BOOT_CLK))
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+		init.ops = &clk_boot_ops;
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+	else
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+		init.ops = &agilex_clk_pll_ops;
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+
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+	init.name = name;
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+	init.flags = clks->flags;
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+
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+	init.num_parents = clks->num_parents;
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+	init.parent_names = NULL;
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+	init.parent_data = clks->parent_data;
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+	pll_clk->hw.hw.init = &init;
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+
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+	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
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209
 
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 	clk = clk_register(NULL, &pll_clk->hw.hw);
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 	if (WARN_ON(IS_ERR(clk))) {