debug lk

hc

2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077

 kernel/drivers/clk/meson/clk-mpll.c
..
..
@@ -12,7 +12,11 @@
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  */
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 #include <linux/clk-provider.h>
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-#include "clkc.h"
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+#include <linux/module.h>
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+#include <linux/spinlock.h>
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+
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+#include "clk-regmap.h"
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+#include "clk-mpll.h"
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20
 
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 #define SDM_DEN 16384
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 #define N2_MIN	4
..
..
@@ -111,20 +115,11 @@
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 	else
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 		__acquire(mpll->lock);
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-	/* Enable and set the fractional part */
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+	/* Set the fractional part */
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 	meson_parm_write(clk->map, &mpll->sdm, sdm);
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-	meson_parm_write(clk->map, &mpll->sdm_en, 1);
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-
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-	/* Set additional fractional part enable if required */
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-	if (MESON_PARM_APPLICABLE(&mpll->ssen))
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-		meson_parm_write(clk->map, &mpll->ssen, 1);
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 	/* Set the integer divider part */
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 	meson_parm_write(clk->map, &mpll->n2, n2);
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-
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-	/* Set the magic misc bit if required */
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-	if (MESON_PARM_APPLICABLE(&mpll->misc))
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-		meson_parm_write(clk->map, &mpll->misc, 1);
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123
 
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 	if (mpll->lock)
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 		spin_unlock_irqrestore(mpll->lock, flags);
..
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@@ -134,13 +129,46 @@
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 	return 0;
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 }
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+static int mpll_init(struct clk_hw *hw)
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+{
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+	struct clk_regmap *clk = to_clk_regmap(hw);
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+	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
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+
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+	if (mpll->init_count)
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+		regmap_multi_reg_write(clk->map, mpll->init_regs,
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+				       mpll->init_count);
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+
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+	/* Enable the fractional part */
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+	meson_parm_write(clk->map, &mpll->sdm_en, 1);
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+
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+	/* Set spread spectrum if possible */
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+	if (MESON_PARM_APPLICABLE(&mpll->ssen)) {
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+		unsigned int ss =
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+			mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;
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+		meson_parm_write(clk->map, &mpll->ssen, ss);
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+	}
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+
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+	/* Set the magic misc bit if required */
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+	if (MESON_PARM_APPLICABLE(&mpll->misc))
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+		meson_parm_write(clk->map, &mpll->misc, 1);
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+
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+	return 0;
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+}
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+
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 const struct clk_ops meson_clk_mpll_ro_ops = {
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 	.recalc_rate	= mpll_recalc_rate,
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 	.round_rate	= mpll_round_rate,
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 };
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+EXPORT_SYMBOL_GPL(meson_clk_mpll_ro_ops);
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 const struct clk_ops meson_clk_mpll_ops = {
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 	.recalc_rate	= mpll_recalc_rate,
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 	.round_rate	= mpll_round_rate,
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 	.set_rate	= mpll_set_rate,
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+	.init		= mpll_init,
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 };
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+EXPORT_SYMBOL_GPL(meson_clk_mpll_ops);
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+
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+MODULE_DESCRIPTION("Amlogic MPLL driver");
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+MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>");
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+MODULE_LICENSE("GPL v2");