| .. | .. |
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| 7 | 7 | #include <linux/dmi.h> |
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| 8 | 8 | #include <linux/pci.h> |
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| 9 | 9 | #include <linux/vgaarb.h> |
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| 10 | +#include <asm/amd_nb.h> |
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| 10 | 11 | #include <asm/hpet.h> |
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| 11 | 12 | #include <asm/pci_x86.h> |
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| 12 | 13 | |
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| .. | .. |
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| 557 | 558 | * Device [8086:2fc0] |
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| 558 | 559 | * Erratum HSE43 |
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| 559 | 560 | * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset |
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| 560 | | - * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html |
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| 561 | + * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html |
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| 561 | 562 | * |
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| 562 | 563 | * Devices [8086:6f60,6fa0,6fc0] |
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| 563 | 564 | * Erratum BDF2 |
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| 564 | 565 | * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration |
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| 565 | | - * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html |
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| 566 | + * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html |
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| 566 | 567 | */ |
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| 567 | 568 | static void pci_invalid_bar(struct pci_dev *dev) |
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| 568 | 569 | { |
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| .. | .. |
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| 587 | 588 | static void pci_fixup_amd_ehci_pme(struct pci_dev *dev) |
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| 588 | 589 | { |
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| 589 | 590 | dev_info(&dev->dev, "PME# does not work under D3, disabling it\n"); |
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| 590 | | - dev->pme_support &= ~((PCI_PM_CAP_PME_D3 | PCI_PM_CAP_PME_D3cold) |
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| 591 | + dev->pme_support &= ~((PCI_PM_CAP_PME_D3hot | PCI_PM_CAP_PME_D3cold) |
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| 591 | 592 | >> PCI_PM_CAP_PME_SHIFT); |
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| 592 | 593 | } |
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| 593 | 594 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme); |
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| .. | .. |
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| 824 | 825 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma); |
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| 825 | 826 | |
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| 826 | 827 | #endif |
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| 828 | + |
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| 829 | +#ifdef CONFIG_AMD_NB |
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| 830 | + |
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| 831 | +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2 0x10136008 |
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| 832 | +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L |
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| 833 | + |
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| 834 | +static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev) |
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| 835 | +{ |
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| 836 | + u32 data; |
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| 837 | + |
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| 838 | + if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) { |
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| 839 | + data &= ~AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK; |
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| 840 | + if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data)) |
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| 841 | + pci_err(dev, "Failed to write data 0x%x\n", data); |
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| 842 | + } else { |
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| 843 | + pci_err(dev, "Failed to read data\n"); |
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| 844 | + } |
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| 845 | +} |
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| 846 | +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0); |
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| 847 | +#endif |
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