.. | .. |
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1194 | 1194 | HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, |
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1195 | 1195 | |
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1196 | 1196 | /* I2CM_OPERATION field values */ |
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| 1197 | + HDMI_I2CM_OPERATION_BUS_CLEAR = 0x20, |
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1197 | 1198 | HDMI_I2CM_OPERATION_WRITE = 0x10, |
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1198 | 1199 | HDMI_I2CM_OPERATION_READ8_EXT = 0x8, |
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1199 | 1200 | HDMI_I2CM_OPERATION_READ8 = 0x4, |
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.. | .. |
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1411 | 1412 | enum dw_hdmi_devtype dev_type, |
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1412 | 1413 | bool output_bus_format_rgb); |
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1413 | 1414 | void inno_dw_hdmi_set_domain(void *grf, int status); |
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1414 | | -void dw_hdmi_set_iomux(void *grf, int dev_type); |
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| 1415 | +void dw_hdmi_set_iomux(void *grf, void *gpio_base, struct gpio_desc *hpd_gpiod, |
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| 1416 | + int dev_type); |
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1415 | 1417 | |
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1416 | 1418 | #endif /* _ROCKCHIP_HDMI_H_ */ |
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