add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 u-boot/drivers/ram/rockchip/sdram_rv1126.c
..
..
@@ -374,6 +374,8 @@
374
374
 			break;
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375
 		delay--;
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 	}
377
+	if (delay <= 0)
378
+		printascii("ERROR: DPLL lock timeout!\n");
377
379
 
378
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 	writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode);
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381
 }
..
..
@@ -557,11 +559,18 @@
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 {
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 	void __iomem *phy_base = dram->phy;
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 	u32 fbdiv, prediv, postdiv, postdiv_en;
562
+	int delay = 1000;
560
563
 
561
564
 	if (wait) {
562
565
 		clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB);
563
-		while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK))
564
-			continue;
566
+		while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) {
567
+			udelay(1);
568
+			if (delay-- <= 0) {
569
+				printascii("ERROR: phy pll lock timeout!\n");
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+				while (1)
571
+					;
572
+			}
573
+		}
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 	} else {
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 		freq /= MHz;
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 		prediv = 1;
..
..
@@ -2484,13 +2493,13 @@
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 	return 0;
2485
2494
 }
2486
2495
 
2487
-static int sdram_init_(struct dram_info *dram,
2488
-		       struct rv1126_sdram_params *sdram_params, u32 post_init)
2496
+int sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init)
2489
2497
 {
2490
2498
 	void __iomem *pctl_base = dram->pctl;
2491
2499
 	void __iomem *phy_base = dram->phy;
2492
2500
 	u32 ddr4_vref;
2493
2501
 	u32 mr_tmp, tmp;
2502
+	int delay = 1000;
2494
2503
 
2495
2504
 	rkclk_configure_ddr(dram, sdram_params);
2496
2505
 
..
..
@@ -2538,8 +2547,14 @@
2538
2547
 
2539
2548
 	rkclk_ddr_reset(dram, 0, 0, 0, 0);
2540
2549
 
2541
-	while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
2542
-		continue;
2550
+	while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) {
2551
+		udelay(1);
2552
+		if (delay-- <= 0) {
2553
+			printascii("ERROR: Cannot wait dfi_init_done!\n");
2554
+			while (1)
2555
+				;
2556
+		}
2557
+	}
2543
2558
 
2544
2559
 	if (sdram_params->base.dramtype == LPDDR3) {
2545
2560
 		pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3);
..
..
@@ -3300,6 +3315,7 @@
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3315
 	struct rv1126_sdram_params *sdram_params_new;
3301
3316
 	void __iomem *pctl_base = dram->pctl;
3302
3317
 	void __iomem *phy_base = dram->phy;
3318
+	int delay = 1000;
3303
3319
 
3304
3320
 	lp_stat = low_power_update(dram, 0);
3305
3321
 	sdram_params_new = get_default_sdram_config(freq);
..
..
@@ -3388,8 +3404,14 @@
3388
3404
 					(0x0 << ACLK_DDR_UPCTL_EN_SHIFT),
3389
3405
 			BUS_SGRF_BASE_ADDR + SGRF_SOC_CON12);
3390
3406
 	while ((readl(pctl_base + DDR_PCTL2_DFISTAT) &
3391
-	       PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE)
3392
-		continue;
3407
+	       PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE) {
3408
+		udelay(1);
3409
+		if (delay-- <= 0) {
3410
+			printascii("ERROR: Cannot wait DFI_INIT_COMPLETE\n");
3411
+			while (1)
3412
+				;
3413
+		}
3414
+	}
3393
3415
 
3394
3416
 	sw_set_req(dram);
3395
3417
 	setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29);