add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 u-boot/drivers/phy/phy-rockchip-naneng-combphy.c
..
..
@@ -22,7 +22,7 @@
22
22
 struct rockchip_combphy_priv;
23
23
 
24
24
 struct combphy_reg {
25
-	u16 offset;
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+	u32 offset;
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 	u16 bitend;
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 	u16 bitstart;
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28
 	u16 disable;
..
..
@@ -37,6 +37,7 @@
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 	struct combphy_reg pipe_rxterm_set;
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 	struct combphy_reg pipe_txelec_set;
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 	struct combphy_reg pipe_txcomp_set;
40
+	struct combphy_reg pipe_clk_24m;
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 	struct combphy_reg pipe_clk_25m;
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 	struct combphy_reg pipe_clk_100m;
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 	struct combphy_reg pipe_phymode_sel;
..
..
@@ -62,6 +63,7 @@
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 	struct combphy_reg pipe_xpcs_phy_ready;
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 	struct combphy_reg u3otg0_port_en;
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 	struct combphy_reg u3otg1_port_en;
66
+	struct combphy_reg pipe_phy_grf_reset;
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 };
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68
 
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 struct rockchip_combphy_cfg {
..
..
@@ -179,6 +181,7 @@
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 static int rockchip_combphy_init(struct phy *phy)
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 {
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 	struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
184
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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185
 	int ret;
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186
 
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 	ret = clk_enable(&priv->ref_clk);
..
..
@@ -191,6 +194,9 @@
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194
 
192
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 	reset_deassert(&priv->phy_rst);
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196
 
197
+	if (cfg->pipe_phy_grf_reset.enable)
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+		param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false);
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+
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 	return 0;
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201
 
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 err_clk:
..
..
@@ -202,9 +208,13 @@
202
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 static int rockchip_combphy_exit(struct phy *phy)
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 {
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 	struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
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+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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212
 
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-	clk_disable(&priv->ref_clk);
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+	if (cfg->pipe_phy_grf_reset.enable)
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+		param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true);
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+
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 	reset_assert(&priv->phy_rst);
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+	clk_disable(&priv->ref_clk);
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218
 
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 	return 0;
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 }
..
..
@@ -291,6 +301,215 @@
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301
 
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 	return rockchip_combphy_parse_dt(udev, priv);
293
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 }
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+
305
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
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+{
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+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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+	u32 val;
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+
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+	switch (priv->mode) {
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+	case PHY_TYPE_PCIE:
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+		/* Set SSC downward spread spectrum */
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+		val = readl(priv->mmio + 0x18);
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+		val &= ~GENMASK(5, 4);
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+		val |= 0x01 << 4;
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+		writel(val, priv->mmio + 0x18);
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+
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+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
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+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
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+		break;
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+	case PHY_TYPE_USB3:
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+		/* Set SSC downward spread spectrum */
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+		val = readl(priv->mmio + 0x18);
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+		val &= ~GENMASK(5, 4);
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+		val |= 0x01 << 4;
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+		writel(val, priv->mmio + 0x18);
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+
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+		/* Enable adaptive CTLE for USB3.0 Rx */
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+		val = readl(priv->mmio + 0x200);
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+		val &= ~GENMASK(17, 17);
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+		val |= 0x01;
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+		writel(val, priv->mmio + 0x200);
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+
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+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
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+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
338
+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
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+		break;
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+	default:
341
+		dev_err(priv->dev, "incompatible PHY type\n");
342
+		return -EINVAL;
343
+	}
344
+
345
+	param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
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+	if (priv->mode == PHY_TYPE_PCIE) {
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+		/* PLL KVCO tuning fine */
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+		val = readl(priv->mmio + 0x18);
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+		val &= ~(0x7 << 10);
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+		val |= 0x2 << 10;
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+		writel(val, priv->mmio + 0x18);
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+
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+		/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
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+		val = readl(priv->mmio + 0x108);
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+		val &= ~(0x7f7);
356
+		val |= 0x4f0;
357
+		writel(val, priv->mmio + 0x108);
358
+	}
359
+
360
+	return 0;
361
+}
362
+
363
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
364
+	/* pipe-phy-grf */
365
+	.pcie_mode_set		= { 0x48000, 5, 0, 0x00, 0x11 },
366
+	.usb_mode_set		= { 0x48000, 5, 0, 0x00, 0x04 },
367
+	.pipe_rxterm_set	= { 0x48000, 12, 12, 0x00, 0x01 },
368
+	.pipe_txelec_set	= { 0x48004, 1, 1, 0x00, 0x01 },
369
+	.pipe_txcomp_set	= { 0x48004, 4, 4, 0x00, 0x01 },
370
+	.pipe_clk_24m		= { 0x48004, 14, 13, 0x00, 0x00 },
371
+	.pipe_clk_100m		= { 0x48004, 14, 13, 0x00, 0x02 },
372
+	.pipe_rxterm_sel	= { 0x48008, 8, 8, 0x00, 0x01 },
373
+	.pipe_txelec_sel	= { 0x48008, 12, 12, 0x00, 0x01 },
374
+	.pipe_txcomp_sel	= { 0x48008, 15, 15, 0x00, 0x01 },
375
+	.pipe_clk_ext		= { 0x4800c, 9, 8, 0x02, 0x01 },
376
+	.pipe_phy_status	= { 0x48034, 6, 6, 0x01, 0x00 },
377
+	.con0_for_pcie		= { 0x48000, 15, 0, 0x00, 0x110 },
378
+	.con1_for_pcie		= { 0x48004, 15, 0, 0x00, 0x00 },
379
+	.con2_for_pcie		= { 0x48008, 15, 0, 0x00, 0x101 },
380
+	.con3_for_pcie		= { 0x4800c, 15, 0, 0x00, 0x0200 },
381
+	/* pipe-grf */
382
+	.u3otg0_port_en		= { 0x40044, 15, 0, 0x0181, 0x1100 },
383
+};
384
+
385
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
386
+	.grfcfg		= &rk3528_combphy_grfcfgs,
387
+	.combphy_cfg	= rk3528_combphy_cfg,
388
+};
389
+
390
+static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
391
+{
392
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
393
+	u32 val;
394
+
395
+	switch (priv->mode) {
396
+	case PHY_TYPE_PCIE:
397
+		/* Set SSC downward spread spectrum */
398
+		val = readl(priv->mmio + (0x1f << 2));
399
+		val &= ~GENMASK(5, 4);
400
+		val |= 0x01 << 4;
401
+		writel(val, priv->mmio + 0x7c);
402
+
403
+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
404
+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
405
+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
406
+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
407
+		break;
408
+	case PHY_TYPE_USB3:
409
+		/* Set SSC downward spread spectrum */
410
+		val = readl(priv->mmio + (0x1f << 2));
411
+		val &= ~GENMASK(5, 4);
412
+		val |= 0x01 << 4;
413
+		writel(val, priv->mmio + 0x7c);
414
+
415
+		/* Enable adaptive CTLE for USB3.0 Rx */
416
+		val = readl(priv->mmio + (0x0e << 2));
417
+		val &= ~GENMASK(0, 0);
418
+		val |= 0x01;
419
+		writel(val, priv->mmio + (0x0e << 2));
420
+
421
+		/* Set PLL KVCO fine tuning signals */
422
+		val = readl(priv->mmio + (0x20 << 2));
423
+		val &= ~(0x7 << 2);
424
+		val |= 0x2 << 2;
425
+		writel(val, priv->mmio + (0x20 << 2));
426
+
427
+		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
428
+		writel(0x4, priv->mmio + (0xb << 2));
429
+
430
+		/* Set PLL input clock divider 1/2 */
431
+		val = readl(priv->mmio + (0x5 << 2));
432
+		val &= ~(0x3 << 6);
433
+		val |= 0x1 << 6;
434
+		writel(val, priv->mmio + (0x5 << 2));
435
+
436
+		/* Set PLL loop divider */
437
+		writel(0x32, priv->mmio + (0x11 << 2));
438
+
439
+		/* Set PLL KVCO to min and set PLL charge pump current to max */
440
+		writel(0xf0, priv->mmio + (0xa << 2));
441
+
442
+		param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
443
+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
444
+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
445
+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
446
+		break;
447
+	default:
448
+		pr_err("%s, phy-type %d\n", __func__, priv->mode);
449
+		return -EINVAL;
450
+	}
451
+
452
+	clk_set_rate(&priv->ref_clk, 100000000);
453
+	param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
454
+
455
+	if (priv->mode == PHY_TYPE_PCIE) {
456
+		/* PLL KVCO tuning fine */
457
+		val = readl(priv->mmio + (0x20 << 2));
458
+		val &= ~(0x7 << 2);
459
+		val |= 0x2 << 2;
460
+		writel(val, priv->mmio + (0x20 << 2));
461
+
462
+		/* Enable controlling random jitter, aka RMJ */
463
+		writel(0x4, priv->mmio + (0xb << 2));
464
+
465
+		val = readl(priv->mmio + (0x5 << 2));
466
+		val &= ~(0x3 << 6);
467
+		val |= 0x1 << 6;
468
+		writel(val, priv->mmio + (0x5 << 2));
469
+
470
+		writel(0x32, priv->mmio + (0x11 << 2));
471
+		writel(0xf0, priv->mmio + (0xa << 2));
472
+	}
473
+
474
+	if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) {
475
+		val = readl(priv->mmio + (0x7 << 2));
476
+		val |= BIT(4);
477
+		writel(val, priv->mmio + (0x7 << 2));
478
+	}
479
+
480
+	return 0;
481
+}
482
+
483
+static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
484
+	/* pipe-phy-grf */
485
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
486
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
487
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
488
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
489
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
490
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
491
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
492
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
493
+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
494
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
495
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
496
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
497
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
498
+	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
499
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
500
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
501
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
502
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
503
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
504
+	.pipe_phy_grf_reset	= { 0x0014, 1, 0, 0x3, 0x1 },
505
+	/* pipe-grf */
506
+	.u3otg0_port_en		= { 0x0094, 15, 0, 0x0181, 0x1100 },
507
+};
508
+
509
+static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
510
+	.grfcfg		= &rk3562_combphy_grfcfgs,
511
+	.combphy_cfg	= rk3562_combphy_cfg,
512
+};
294
513
 
295
514
 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
296
515
 {
..
..
@@ -565,6 +784,14 @@
565
784
 
566
785
 static const struct udevice_id rockchip_combphy_ids[] = {
567
786
 	{
787
+		.compatible = "rockchip,rk3528-naneng-combphy",
788
+		.data = (ulong)&rk3528_combphy_cfgs
789
+	},
790
+	{
791
+		.compatible = "rockchip,rk3562-naneng-combphy",
792
+		.data = (ulong)&rk3562_combphy_cfgs
793
+	},
794
+	{
568
795
 		.compatible = "rockchip,rk3568-naneng-combphy",
569
796
 		.data = (ulong)&rk3568_combphy_cfgs
570
797
 	},