add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 u-boot/drivers/pci/pcie_dw_rockchip.c
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@@ -18,8 +18,41 @@
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 #include <asm-generic/gpio.h>
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 #include <asm/arch-rockchip/clock.h>
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 #include <linux/iopoll.h>
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+#include <linux/ioport.h>
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22
 
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 DECLARE_GLOBAL_DATA_PTR;
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+
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+#define RK_PCIE_DBG			0
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+
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+#define __pcie_dev_print_emit(fmt, ...) \
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+({ \
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+	printf(fmt, ##__VA_ARGS__); \
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+})
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+
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+#ifdef dev_err
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+#undef dev_err
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+#define dev_err(dev, fmt, ...) \
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+({ \
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+	if (dev) \
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+		__pcie_dev_print_emit("%s: " fmt, dev->name, \
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+				##__VA_ARGS__); \
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+})
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+#endif
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+
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+#ifdef dev_info
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+#undef dev_info
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+#define dev_info dev_err
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+#endif
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+
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+#ifdef DEBUG
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+#define dev_dbg dev_err
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+#else
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+#define dev_dbg(dev, fmt, ...)					\
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+({								\
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+	if (0)							\
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+		__dev_printk(7, dev, fmt, ##__VA_ARGS__);	\
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+})
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+#endif
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56
 
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 struct rk_pcie {
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 	struct udevice	*dev;
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@@ -62,7 +95,6 @@
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 #define PCIE_CLIENT_DBG_FIFO_STATUS	0x350
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 #define PCIE_CLIENT_DBG_TRANSITION_DATA	0xffff0000
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 #define PCIE_CLIENT_DBF_EN		0xffff0003
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-#define RK_PCIE_DBG			0
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98
 
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 /* PCI DBICS registers */
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 #define PCIE_LINK_STATUS_REG		0x80
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@@ -119,6 +151,8 @@
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 #define LINK_WAIT_MAX_IATU_RETRIES	5
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 #define LINK_WAIT_IATU			10000
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153
 
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+#define PCIE_TYPE0_HDR_DBI2_OFFSET      0x100000
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+
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 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
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 {
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 	if ((uintptr_t)addr & (size - 1)) {
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@@ -165,7 +199,7 @@
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 	ret = rk_pcie_read(base + reg, size, &val);
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 	if (ret)
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-		dev_err(rk_pcie->pci->dev, "Read APB address failed\n");
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+		dev_err(rk_pcie->dev, "Read APB address failed\n");
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203
 
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 	return val;
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 }
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@@ -177,7 +211,7 @@
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211
 
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 	ret = rk_pcie_write(base + reg, size, val);
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 	if (ret)
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-		dev_err(rk_pcie->pci->dev, "Write APB address failed\n");
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+		dev_err(rk_pcie->dev, "Write APB address failed\n");
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 }
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216
 
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 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
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@@ -272,6 +306,10 @@
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 	val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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 	val |= PORT_LOGIC_SPEED_CHANGE;
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 	writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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+
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+	/* Disable BAR0 BAR1 */
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+	writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4);
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+	writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4);
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313
 
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 	rk_pcie_dbi_write_enable(rk_pcie, false);
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 }
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@@ -469,10 +507,10 @@
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 #if RK_PCIE_DBG
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 	u32 loop;
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509
 
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-	dev_info(rk_pcie->dev, "ltssm = 0x%x\n",
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+	dev_err(rk_pcie->dev, "ltssm = 0x%x\n",
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 		 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
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 	for (loop = 0; loop < 64; loop++)
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-		dev_info(rk_pcie->dev, "fifo_status = 0x%x\n",
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+		dev_err(rk_pcie->dev, "fifo_status = 0x%x\n",
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 			 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
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 #endif
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 }
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@@ -641,17 +679,18 @@
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 	struct rk_pcie *priv = dev_get_priv(dev);
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 	u32 max_link_speed;
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 	int ret;
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+	struct resource res;
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683
 
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-	priv->dbi_base = (void *)dev_read_addr_index(dev, 0);
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-	if (!priv->dbi_base)
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+	ret = dev_read_resource_byname(dev, "pcie-dbi", &res);
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+	if (ret)
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 		return -ENODEV;
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-
687
+	priv->dbi_base = (void *)(res.start);
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 	dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base);
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689
 
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-	priv->apb_base = (void *)dev_read_addr_index(dev, 1);
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-	if (!priv->apb_base)
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+	ret = dev_read_resource_byname(dev, "pcie-apb", &res);
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+	if (ret)
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 		return -ENODEV;
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-
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+	priv->apb_base = (void *)(res.start);
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 	dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
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695
 
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 	ret = gpio_request_by_name(dev, "reset-gpios", 0,
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@@ -771,6 +810,8 @@
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 };
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811
 
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 static const struct udevice_id rockchip_pcie_ids[] = {
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+	{ .compatible = "rockchip,rk3528-pcie" },
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+	{ .compatible = "rockchip,rk3562-pcie" },
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815
 	{ .compatible = "rockchip,rk3568-pcie" },
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 	{ .compatible = "rockchip,rk3588-pcie" },
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 	{ }