hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
u-boot/arch/arm/dts/rk3128.dtsi
....@@ -222,6 +222,18 @@
222222 reg = <0x20000110 0x24>;
223223 #reset-cells = <1>;
224224 };
225
+
226
+ sfc: sfc@1020c000 {
227
+ compatible ="rockchip,rksfc","rockchip,sfc";
228
+ reg = <0x1020c000 0x8000>;
229
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
230
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
231
+ clock-names = "clk_sfc", "hclk_sfc";
232
+ assigned-clocks = <&cru SCLK_SFC>;
233
+ assigned-clock-rates = <60000000>;
234
+ status = "disabled";
235
+ };
236
+
225237 nandc: nandc@10500000 {
226238 compatible = "rockchip,rk-nandc";
227239 reg = <0x10500000 0x4000>;
....@@ -590,6 +602,8 @@
590602 grf: syscon@20008000 {
591603 compatible = "rockchip,rk3128-grf", "syscon";
592604 reg = <0x20008000 0x1000>;
605
+ #address-cells = <1>;
606
+ #size-cells = <1>;
593607
594608 lvds: lvds {
595609 compatible = "rockchip,rk3126-lvds";