.. | .. |
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222 | 222 | reg = <0x20000110 0x24>; |
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223 | 223 | #reset-cells = <1>; |
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224 | 224 | }; |
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| 225 | + |
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| 226 | + sfc: sfc@1020c000 { |
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| 227 | + compatible ="rockchip,rksfc","rockchip,sfc"; |
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| 228 | + reg = <0x1020c000 0x8000>; |
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| 229 | + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
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| 230 | + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; |
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| 231 | + clock-names = "clk_sfc", "hclk_sfc"; |
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| 232 | + assigned-clocks = <&cru SCLK_SFC>; |
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| 233 | + assigned-clock-rates = <60000000>; |
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| 234 | + status = "disabled"; |
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| 235 | + }; |
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| 236 | + |
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225 | 237 | nandc: nandc@10500000 { |
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226 | 238 | compatible = "rockchip,rk-nandc"; |
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227 | 239 | reg = <0x10500000 0x4000>; |
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.. | .. |
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590 | 602 | grf: syscon@20008000 { |
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591 | 603 | compatible = "rockchip,rk3128-grf", "syscon"; |
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592 | 604 | reg = <0x20008000 0x1000>; |
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| 605 | + #address-cells = <1>; |
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| 606 | + #size-cells = <1>; |
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593 | 607 | |
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594 | 608 | lvds: lvds { |
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595 | 609 | compatible = "rockchip,rk3126-lvds"; |
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