add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
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..
@@ -1,60 +1,5 @@
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 [
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     {
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-        "EventCode": "0xAE",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x1",
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-        "EventName": "ITLB.ITLB_FLUSH",
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-        "SampleAfterValue": "100007",
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-        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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-        "EventCode": "0x4F",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x10",
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-        "EventName": "EPT.WALK_CYCLES",
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-        "SampleAfterValue": "2000003",
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-        "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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-        "EventCode": "0x85",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x1",
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-        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
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-        "SampleAfterValue": "100003",
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-        "BriefDescription": "Misses at all ITLB levels that cause page walks.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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-        "EventCode": "0x85",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x2",
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-        "EventName": "ITLB_MISSES.WALK_COMPLETED",
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-        "SampleAfterValue": "100003",
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-        "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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-        "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
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-        "EventCode": "0x85",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x4",
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-        "EventName": "ITLB_MISSES.WALK_DURATION",
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-        "SampleAfterValue": "2000003",
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-        "BriefDescription": "Cycles when PMH is busy with page walks.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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-        "EventCode": "0x85",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x10",
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-        "EventName": "ITLB_MISSES.STLB_HIT",
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-        "SampleAfterValue": "100003",
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-        "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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         "EventCode": "0x08",
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4
         "Counter": "0,1,2,3",
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         "UMask": "0x1",
..
..
@@ -129,6 +74,61 @@
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         "CounterHTOff": "0,1,2,3,4,5,6,7"
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     },
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     {
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+        "EventCode": "0x4F",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x10",
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+        "EventName": "EPT.WALK_CYCLES",
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+        "SampleAfterValue": "2000003",
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+        "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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+        "EventCode": "0x85",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x1",
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+        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
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+        "SampleAfterValue": "100003",
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+        "BriefDescription": "Misses at all ITLB levels that cause page walks.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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+        "EventCode": "0x85",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x2",
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+        "EventName": "ITLB_MISSES.WALK_COMPLETED",
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+        "SampleAfterValue": "100003",
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+        "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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+        "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
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+        "EventCode": "0x85",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x4",
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+        "EventName": "ITLB_MISSES.WALK_DURATION",
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+        "SampleAfterValue": "2000003",
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+        "BriefDescription": "Cycles when PMH is busy with page walks.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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+        "EventCode": "0x85",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x10",
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+        "EventName": "ITLB_MISSES.STLB_HIT",
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+        "SampleAfterValue": "100003",
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+        "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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+        "EventCode": "0xAE",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x1",
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+        "EventName": "ITLB.ITLB_FLUSH",
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+        "SampleAfterValue": "100007",
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+        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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         "EventCode": "0xBD",
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         "Counter": "0,1,2,3",
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         "UMask": "0x1",