add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/tools/perf/pmu-events/arch/x86/sandybridge/memory.json
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@@ -1,5 +1,32 @@
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 [
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     {
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+        "EventCode": "0x05",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x1",
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+        "EventName": "MISALIGN_MEM_REF.LOADS",
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+        "SampleAfterValue": "2000003",
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+        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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+        "EventCode": "0x05",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x2",
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+        "EventName": "MISALIGN_MEM_REF.STORES",
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+        "SampleAfterValue": "2000003",
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+        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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+        "EventCode": "0xBE",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x1",
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+        "EventName": "PAGE_WALKS.LLC_MISS",
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+        "SampleAfterValue": "100003",
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+        "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
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         "EventCode": "0xC3",
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         "Counter": "0,1,2,3",
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@@ -124,33 +151,6 @@
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         "PRECISE_STORE": "1",
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         "TakenAlone": "1",
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         "CounterHTOff": "3"
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-    },
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-    {
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-        "EventCode": "0xBE",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x1",
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-        "EventName": "PAGE_WALKS.LLC_MISS",
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-        "SampleAfterValue": "100003",
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-        "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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-        "EventCode": "0x05",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x1",
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-        "EventName": "MISALIGN_MEM_REF.LOADS",
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-        "SampleAfterValue": "2000003",
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-        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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-        "EventCode": "0x05",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x2",
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-        "EventName": "MISALIGN_MEM_REF.STORES",
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-        "SampleAfterValue": "2000003",
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-        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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     },
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     {
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         "EventCode": "0xB7, 0xBB",
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@@ -367,7 +367,7 @@
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         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",
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         "MSRIndex": "0x1a6,0x1a7",
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         "SampleAfterValue": "100003",
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-        "BriefDescription": " REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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+        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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         "CounterHTOff": "0,1,2,3"
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     },
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     {
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@@ -379,7 +379,7 @@
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         "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",
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         "MSRIndex": "0x1a6,0x1a7",
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         "SampleAfterValue": "100003",
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-        "BriefDescription": " REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
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+        "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
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         "CounterHTOff": "0,1,2,3"
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     },
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     {
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@@ -391,7 +391,7 @@
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         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",
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         "MSRIndex": "0x1a6,0x1a7",
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         "SampleAfterValue": "100003",
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-        "BriefDescription": " REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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+        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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         "CounterHTOff": "0,1,2,3"
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     },
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     {
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@@ -403,7 +403,7 @@
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         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",
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         "MSRIndex": "0x1a6,0x1a7",
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         "SampleAfterValue": "100003",
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-        "BriefDescription": " REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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+        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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         "CounterHTOff": "0,1,2,3"
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     },
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     {
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@@ -415,7 +415,7 @@
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         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",
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         "MSRIndex": "0x1a6,0x1a7",
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         "SampleAfterValue": "100003",
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-        "BriefDescription": " REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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+        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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         "CounterHTOff": "0,1,2,3"
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     },
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     {
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@@ -427,7 +427,7 @@
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         "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",
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         "MSRIndex": "0x1a6,0x1a7",
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         "SampleAfterValue": "100003",
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-        "BriefDescription": " REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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+        "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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         "CounterHTOff": "0,1,2,3"
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     },
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     {
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@@ -439,7 +439,7 @@
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         "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",
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         "MSRIndex": "0x1a6,0x1a7",
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         "SampleAfterValue": "100003",
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-        "BriefDescription": " REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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+        "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
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         "CounterHTOff": "0,1,2,3"
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     }
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 ]