add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/tools/perf/pmu-events/arch/x86/haswellx/memory.json
..
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@@ -291,7 +291,7 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 4.",
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+        "BriefDescription": "Randomly selected loads with latency value being above 4.",
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         "PEBS": "2",
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         "MSRValue": "0x4",
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         "Counter": "3",
..
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@@ -305,7 +305,7 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 8.",
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+        "BriefDescription": "Randomly selected loads with latency value being above 8.",
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         "PEBS": "2",
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         "MSRValue": "0x8",
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         "Counter": "3",
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@@ -319,7 +319,7 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 16.",
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+        "BriefDescription": "Randomly selected loads with latency value being above 16.",
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         "PEBS": "2",
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         "MSRValue": "0x10",
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         "Counter": "3",
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@@ -333,7 +333,7 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 32.",
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+        "BriefDescription": "Randomly selected loads with latency value being above 32.",
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         "PEBS": "2",
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         "MSRValue": "0x20",
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         "Counter": "3",
..
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@@ -347,7 +347,7 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 64.",
350
+        "BriefDescription": "Randomly selected loads with latency value being above 64.",
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         "PEBS": "2",
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         "MSRValue": "0x40",
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         "Counter": "3",
..
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@@ -361,7 +361,7 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 128.",
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+        "BriefDescription": "Randomly selected loads with latency value being above 128.",
365
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         "PEBS": "2",
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         "MSRValue": "0x80",
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         "Counter": "3",
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@@ -375,7 +375,7 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 256.",
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+        "BriefDescription": "Randomly selected loads with latency value being above 256.",
379
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         "PEBS": "2",
380
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         "MSRValue": "0x100",
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         "Counter": "3",
..
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@@ -389,7 +389,7 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 512.",
392
+        "BriefDescription": "Randomly selected loads with latency value being above 512.",
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         "PEBS": "2",
394
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         "MSRValue": "0x200",
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         "Counter": "3",
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@@ -404,12 +404,12 @@
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         "Offcore": "1",
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         "EventCode": "0xB7, 0xBB",
406
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         "UMask": "0x1",
407
-        "BriefDescription": "Counts demand data reads that miss in the L3",
408
-        "MSRValue": "0x3fbfc00001",
407
+        "BriefDescription": "Counts demand data reads miss in the L3",
408
+        "MSRValue": "0x3FBFC00001",
409
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         "Counter": "0,1,2,3",
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         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
411
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         "MSRIndex": "0x1a6,0x1a7",
412
-        "PublicDescription": "Counts demand data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
412
+        "PublicDescription": "Counts demand data reads miss in the L3",
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         "SampleAfterValue": "100003",
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         "CounterHTOff": "0,1,2,3"
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     },
..
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@@ -417,12 +417,12 @@
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         "Offcore": "1",
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         "EventCode": "0xB7, 0xBB",
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         "UMask": "0x1",
420
-        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram",
420
+        "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
421
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         "MSRValue": "0x0600400001",
422
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         "Counter": "0,1,2,3",
423
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         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
424
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         "MSRIndex": "0x1a6,0x1a7",
425
-        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
425
+        "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
426
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         "SampleAfterValue": "100003",
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         "CounterHTOff": "0,1,2,3"
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     },
..
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@@ -430,12 +430,12 @@
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         "Offcore": "1",
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         "EventCode": "0xB7, 0xBB",
432
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         "UMask": "0x1",
433
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",
434
-        "MSRValue": "0x3fbfc00002",
433
+        "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
434
+        "MSRValue": "0x3FBFC00002",
435
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         "Counter": "0,1,2,3",
436
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         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
437
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         "MSRIndex": "0x1a6,0x1a7",
438
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
438
+        "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
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         "SampleAfterValue": "100003",
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         "CounterHTOff": "0,1,2,3"
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     },
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@@ -443,12 +443,12 @@
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         "Offcore": "1",
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         "EventCode": "0xB7, 0xBB",
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         "UMask": "0x1",
446
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram",
446
+        "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
447
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         "MSRValue": "0x0600400002",
448
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         "Counter": "0,1,2,3",
449
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         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",
450
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         "MSRIndex": "0x1a6,0x1a7",
451
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
451
+        "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
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         "SampleAfterValue": "100003",
453
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         "CounterHTOff": "0,1,2,3"
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     },
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@@ -456,12 +456,12 @@
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         "Offcore": "1",
457
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         "EventCode": "0xB7, 0xBB",
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         "UMask": "0x1",
459
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache",
460
-        "MSRValue": "0x103fc00002",
459
+        "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
460
+        "MSRValue": "0x103FC00002",
461
461
         "Counter": "0,1,2,3",
462
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         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
463
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         "MSRIndex": "0x1a6,0x1a7",
464
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
464
+        "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
465
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         "SampleAfterValue": "100003",
466
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         "CounterHTOff": "0,1,2,3"
467
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     },
..
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@@ -469,12 +469,12 @@
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         "Offcore": "1",
470
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         "EventCode": "0xB7, 0xBB",
471
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         "UMask": "0x1",
472
-        "BriefDescription": "Counts all demand code reads that miss in the L3",
473
-        "MSRValue": "0x3fbfc00004",
472
+        "BriefDescription": "Counts all demand code reads miss in the L3",
473
+        "MSRValue": "0x3FBFC00004",
474
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         "Counter": "0,1,2,3",
475
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         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
476
476
         "MSRIndex": "0x1a6,0x1a7",
477
-        "PublicDescription": "Counts all demand code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
477
+        "PublicDescription": "Counts all demand code reads miss in the L3",
478
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         "SampleAfterValue": "100003",
479
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         "CounterHTOff": "0,1,2,3"
480
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     },
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@@ -482,12 +482,12 @@
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         "Offcore": "1",
483
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         "EventCode": "0xB7, 0xBB",
484
484
         "UMask": "0x1",
485
-        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram",
485
+        "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
486
486
         "MSRValue": "0x0600400004",
487
487
         "Counter": "0,1,2,3",
488
488
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
489
489
         "MSRIndex": "0x1a6,0x1a7",
490
-        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
490
+        "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
491
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         "SampleAfterValue": "100003",
492
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         "CounterHTOff": "0,1,2,3"
493
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     },
..
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@@ -495,12 +495,12 @@
495
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         "Offcore": "1",
496
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         "EventCode": "0xB7, 0xBB",
497
497
         "UMask": "0x1",
498
-        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3",
499
-        "MSRValue": "0x3fbfc00010",
498
+        "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
499
+        "MSRValue": "0x3FBFC00010",
500
500
         "Counter": "0,1,2,3",
501
501
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
502
502
         "MSRIndex": "0x1a6,0x1a7",
503
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
503
+        "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
504
504
         "SampleAfterValue": "100003",
505
505
         "CounterHTOff": "0,1,2,3"
506
506
     },
..
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@@ -508,12 +508,12 @@
508
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         "Offcore": "1",
509
509
         "EventCode": "0xB7, 0xBB",
510
510
         "UMask": "0x1",
511
-        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3",
512
-        "MSRValue": "0x3fbfc00020",
511
+        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
512
+        "MSRValue": "0x3FBFC00020",
513
513
         "Counter": "0,1,2,3",
514
514
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE",
515
515
         "MSRIndex": "0x1a6,0x1a7",
516
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
516
+        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
517
517
         "SampleAfterValue": "100003",
518
518
         "CounterHTOff": "0,1,2,3"
519
519
     },
..
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@@ -521,12 +521,12 @@
521
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         "Offcore": "1",
522
522
         "EventCode": "0xB7, 0xBB",
523
523
         "UMask": "0x1",
524
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3",
525
-        "MSRValue": "0x3fbfc00040",
524
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
525
+        "MSRValue": "0x3FBFC00040",
526
526
         "Counter": "0,1,2,3",
527
527
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
528
528
         "MSRIndex": "0x1a6,0x1a7",
529
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
529
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
530
530
         "SampleAfterValue": "100003",
531
531
         "CounterHTOff": "0,1,2,3"
532
532
     },
..
..
@@ -534,12 +534,12 @@
534
534
         "Offcore": "1",
535
535
         "EventCode": "0xB7, 0xBB",
536
536
         "UMask": "0x1",
537
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3",
538
-        "MSRValue": "0x3fbfc00080",
537
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
538
+        "MSRValue": "0x3FBFC00080",
539
539
         "Counter": "0,1,2,3",
540
540
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
541
541
         "MSRIndex": "0x1a6,0x1a7",
542
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
542
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
543
543
         "SampleAfterValue": "100003",
544
544
         "CounterHTOff": "0,1,2,3"
545
545
     },
..
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@@ -547,12 +547,12 @@
547
547
         "Offcore": "1",
548
548
         "EventCode": "0xB7, 0xBB",
549
549
         "UMask": "0x1",
550
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3",
551
-        "MSRValue": "0x3fbfc00100",
550
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
551
+        "MSRValue": "0x3FBFC00100",
552
552
         "Counter": "0,1,2,3",
553
553
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
554
554
         "MSRIndex": "0x1a6,0x1a7",
555
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
555
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
556
556
         "SampleAfterValue": "100003",
557
557
         "CounterHTOff": "0,1,2,3"
558
558
     },
..
..
@@ -560,12 +560,12 @@
560
560
         "Offcore": "1",
561
561
         "EventCode": "0xB7, 0xBB",
562
562
         "UMask": "0x1",
563
-        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",
564
-        "MSRValue": "0x3fbfc00200",
563
+        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
564
+        "MSRValue": "0x3FBFC00200",
565
565
         "Counter": "0,1,2,3",
566
566
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
567
567
         "MSRIndex": "0x1a6,0x1a7",
568
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
568
+        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
569
569
         "SampleAfterValue": "100003",
570
570
         "CounterHTOff": "0,1,2,3"
571
571
     },
..
..
@@ -573,12 +573,12 @@
573
573
         "Offcore": "1",
574
574
         "EventCode": "0xB7, 0xBB",
575
575
         "UMask": "0x1",
576
-        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",
577
-        "MSRValue": "0x3fbfc00091",
576
+        "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
577
+        "MSRValue": "0x3FBFC00091",
578
578
         "Counter": "0,1,2,3",
579
579
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
580
580
         "MSRIndex": "0x1a6,0x1a7",
581
-        "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
581
+        "PublicDescription": "Counts all demand & prefetch data reads miss in the L3",
582
582
         "SampleAfterValue": "100003",
583
583
         "CounterHTOff": "0,1,2,3"
584
584
     },
..
..
@@ -586,12 +586,12 @@
586
586
         "Offcore": "1",
587
587
         "EventCode": "0xB7, 0xBB",
588
588
         "UMask": "0x1",
589
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",
589
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
590
590
         "MSRValue": "0x0600400091",
591
591
         "Counter": "0,1,2,3",
592
592
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
593
593
         "MSRIndex": "0x1a6,0x1a7",
594
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
594
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
595
595
         "SampleAfterValue": "100003",
596
596
         "CounterHTOff": "0,1,2,3"
597
597
     },
..
..
@@ -599,12 +599,12 @@
599
599
         "Offcore": "1",
600
600
         "EventCode": "0xB7, 0xBB",
601
601
         "UMask": "0x1",
602
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram",
603
-        "MSRValue": "0x063f800091",
602
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
603
+        "MSRValue": "0x063F800091",
604
604
         "Counter": "0,1,2,3",
605
605
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
606
606
         "MSRIndex": "0x1a6,0x1a7",
607
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
607
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
608
608
         "SampleAfterValue": "100003",
609
609
         "CounterHTOff": "0,1,2,3"
610
610
     },
..
..
@@ -612,12 +612,12 @@
612
612
         "Offcore": "1",
613
613
         "EventCode": "0xB7, 0xBB",
614
614
         "UMask": "0x1",
615
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache",
616
-        "MSRValue": "0x103fc00091",
615
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
616
+        "MSRValue": "0x103FC00091",
617
617
         "Counter": "0,1,2,3",
618
618
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
619
619
         "MSRIndex": "0x1a6,0x1a7",
620
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
620
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
621
621
         "SampleAfterValue": "100003",
622
622
         "CounterHTOff": "0,1,2,3"
623
623
     },
..
..
@@ -625,12 +625,12 @@
625
625
         "Offcore": "1",
626
626
         "EventCode": "0xB7, 0xBB",
627
627
         "UMask": "0x1",
628
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache",
629
-        "MSRValue": "0x083fc00091",
628
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
629
+        "MSRValue": "0x083FC00091",
630
630
         "Counter": "0,1,2,3",
631
631
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
632
632
         "MSRIndex": "0x1a6,0x1a7",
633
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
633
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
634
634
         "SampleAfterValue": "100003",
635
635
         "CounterHTOff": "0,1,2,3"
636
636
     },
..
..
@@ -638,12 +638,12 @@
638
638
         "Offcore": "1",
639
639
         "EventCode": "0xB7, 0xBB",
640
640
         "UMask": "0x1",
641
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",
642
-        "MSRValue": "0x3fbfc00122",
641
+        "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
642
+        "MSRValue": "0x3FBFC00122",
643
643
         "Counter": "0,1,2,3",
644
644
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
645
645
         "MSRIndex": "0x1a6,0x1a7",
646
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
646
+        "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3",
647
647
         "SampleAfterValue": "100003",
648
648
         "CounterHTOff": "0,1,2,3"
649
649
     },
..
..
@@ -651,12 +651,12 @@
651
651
         "Offcore": "1",
652
652
         "EventCode": "0xB7, 0xBB",
653
653
         "UMask": "0x1",
654
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",
654
+        "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
655
655
         "MSRValue": "0x0600400122",
656
656
         "Counter": "0,1,2,3",
657
657
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
658
658
         "MSRIndex": "0x1a6,0x1a7",
659
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
659
+        "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
660
660
         "SampleAfterValue": "100003",
661
661
         "CounterHTOff": "0,1,2,3"
662
662
     },
..
..
@@ -664,12 +664,12 @@
664
664
         "Offcore": "1",
665
665
         "EventCode": "0xB7, 0xBB",
666
666
         "UMask": "0x1",
667
-        "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",
668
-        "MSRValue": "0x3fbfc00244",
667
+        "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
668
+        "MSRValue": "0x3FBFC00244",
669
669
         "Counter": "0,1,2,3",
670
670
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
671
671
         "MSRIndex": "0x1a6,0x1a7",
672
-        "PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
672
+        "PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
673
673
         "SampleAfterValue": "100003",
674
674
         "CounterHTOff": "0,1,2,3"
675
675
     },
..
..
@@ -677,12 +677,12 @@
677
677
         "Offcore": "1",
678
678
         "EventCode": "0xB7, 0xBB",
679
679
         "UMask": "0x1",
680
-        "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",
680
+        "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
681
681
         "MSRValue": "0x0600400244",
682
682
         "Counter": "0,1,2,3",
683
683
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
684
684
         "MSRIndex": "0x1a6,0x1a7",
685
-        "PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
685
+        "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
686
686
         "SampleAfterValue": "100003",
687
687
         "CounterHTOff": "0,1,2,3"
688
688
     },
..
..
@@ -690,12 +690,12 @@
690
690
         "Offcore": "1",
691
691
         "EventCode": "0xB7, 0xBB",
692
692
         "UMask": "0x1",
693
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",
694
-        "MSRValue": "0x3fbfc007f7",
693
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
694
+        "MSRValue": "0x3FBFC007F7",
695
695
         "Counter": "0,1,2,3",
696
696
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
697
697
         "MSRIndex": "0x1a6,0x1a7",
698
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
698
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
699
699
         "SampleAfterValue": "100003",
700
700
         "CounterHTOff": "0,1,2,3"
701
701
     },
..
..
@@ -703,12 +703,12 @@
703
703
         "Offcore": "1",
704
704
         "EventCode": "0xB7, 0xBB",
705
705
         "UMask": "0x1",
706
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",
707
-        "MSRValue": "0x06004007f7",
706
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
707
+        "MSRValue": "0x06004007F7",
708
708
         "Counter": "0,1,2,3",
709
709
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
710
710
         "MSRIndex": "0x1a6,0x1a7",
711
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
711
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
712
712
         "SampleAfterValue": "100003",
713
713
         "CounterHTOff": "0,1,2,3"
714
714
     },
..
..
@@ -716,12 +716,12 @@
716
716
         "Offcore": "1",
717
717
         "EventCode": "0xB7, 0xBB",
718
718
         "UMask": "0x1",
719
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram",
720
-        "MSRValue": "0x063f8007f7",
719
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
720
+        "MSRValue": "0x063F8007F7",
721
721
         "Counter": "0,1,2,3",
722
722
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
723
723
         "MSRIndex": "0x1a6,0x1a7",
724
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
724
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
725
725
         "SampleAfterValue": "100003",
726
726
         "CounterHTOff": "0,1,2,3"
727
727
     },
..
..
@@ -729,12 +729,12 @@
729
729
         "Offcore": "1",
730
730
         "EventCode": "0xB7, 0xBB",
731
731
         "UMask": "0x1",
732
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache",
733
-        "MSRValue": "0x103fc007f7",
732
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
733
+        "MSRValue": "0x103FC007F7",
734
734
         "Counter": "0,1,2,3",
735
735
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
736
736
         "MSRIndex": "0x1a6,0x1a7",
737
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
737
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
738
738
         "SampleAfterValue": "100003",
739
739
         "CounterHTOff": "0,1,2,3"
740
740
     },
..
..
@@ -742,12 +742,12 @@
742
742
         "Offcore": "1",
743
743
         "EventCode": "0xB7, 0xBB",
744
744
         "UMask": "0x1",
745
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache",
746
-        "MSRValue": "0x083fc007f7",
745
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
746
+        "MSRValue": "0x083FC007F7",
747
747
         "Counter": "0,1,2,3",
748
748
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
749
749
         "MSRIndex": "0x1a6,0x1a7",
750
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
750
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
751
751
         "SampleAfterValue": "100003",
752
752
         "CounterHTOff": "0,1,2,3"
753
753
     },
..
..
@@ -755,12 +755,12 @@
755
755
         "Offcore": "1",
756
756
         "EventCode": "0xB7, 0xBB",
757
757
         "UMask": "0x1",
758
-        "BriefDescription": "Counts all requests that miss in the L3",
759
-        "MSRValue": "0x3fbfc08fff",
758
+        "BriefDescription": "Counts all requests miss in the L3",
759
+        "MSRValue": "0x3FBFC08FFF",
760
760
         "Counter": "0,1,2,3",
761
761
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
762
762
         "MSRIndex": "0x1a6,0x1a7",
763
-        "PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
763
+        "PublicDescription": "Counts all requests miss in the L3",
764
764
         "SampleAfterValue": "100003",
765
765
         "CounterHTOff": "0,1,2,3"
766
766
     }