add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
..
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@@ -170,11 +170,11 @@
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     {
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         "EventCode": "0xc8",
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         "UMask": "0x4",
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-        "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
173
+        "BriefDescription": "Number of times HLE abort was triggered",
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         "PEBS": "1",
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         "Counter": "0,1,2,3",
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         "EventName": "HLE_RETIRED.ABORTED",
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-        "PublicDescription": "Number of times HLE abort was triggered (PEBS).",
177
+        "PublicDescription": "Number of times HLE abort was triggered.",
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         "SampleAfterValue": "2000003",
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         "CounterHTOff": "0,1,2,3,4,5,6,7"
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     },
..
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@@ -251,11 +251,11 @@
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     {
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         "EventCode": "0xc9",
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         "UMask": "0x4",
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-        "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
254
+        "BriefDescription": "Number of times RTM abort was triggered",
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         "PEBS": "1",
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         "Counter": "0,1,2,3",
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         "EventName": "RTM_RETIRED.ABORTED",
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-        "PublicDescription": "Number of times RTM abort was triggered (PEBS).",
258
+        "PublicDescription": "Number of times RTM abort was triggered .",
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         "SampleAfterValue": "2000003",
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         "CounterHTOff": "0,1,2,3"
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     },
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@@ -312,14 +312,14 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 4",
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+        "BriefDescription": "Randomly selected loads with latency value being above 4",
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         "PEBS": "2",
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         "MSRValue": "0x4",
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         "Counter": "3",
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
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         "MSRIndex": "0x3F6",
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         "Errata": "BDM100, BDM35",
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-        "PublicDescription": "This event counts loads with latency value being above four.",
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+        "PublicDescription": "Counts randomly selected loads with latency value being above four.",
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         "TakenAlone": "1",
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         "SampleAfterValue": "100003",
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         "CounterHTOff": "3"
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@@ -327,14 +327,14 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 8",
330
+        "BriefDescription": "Randomly selected loads with latency value being above 8",
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         "PEBS": "2",
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         "MSRValue": "0x8",
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         "Counter": "3",
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
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         "MSRIndex": "0x3F6",
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         "Errata": "BDM100, BDM35",
337
-        "PublicDescription": "This event counts loads with latency value being above eight.",
337
+        "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
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         "TakenAlone": "1",
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         "SampleAfterValue": "50021",
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         "CounterHTOff": "3"
..
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@@ -342,14 +342,14 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 16",
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+        "BriefDescription": "Randomly selected loads with latency value being above 16",
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         "PEBS": "2",
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         "MSRValue": "0x10",
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         "Counter": "3",
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
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         "MSRIndex": "0x3F6",
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         "Errata": "BDM100, BDM35",
352
-        "PublicDescription": "This event counts loads with latency value being above 16.",
352
+        "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
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         "TakenAlone": "1",
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         "SampleAfterValue": "20011",
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         "CounterHTOff": "3"
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@@ -357,14 +357,14 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 32",
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+        "BriefDescription": "Randomly selected loads with latency value being above 32",
361
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         "PEBS": "2",
362
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         "MSRValue": "0x20",
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         "Counter": "3",
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
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         "MSRIndex": "0x3F6",
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         "Errata": "BDM100, BDM35",
367
-        "PublicDescription": "This event counts loads with latency value being above 32.",
367
+        "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
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         "TakenAlone": "1",
369
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         "SampleAfterValue": "100007",
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         "CounterHTOff": "3"
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@@ -372,14 +372,14 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 64",
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+        "BriefDescription": "Randomly selected loads with latency value being above 64",
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         "PEBS": "2",
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         "MSRValue": "0x40",
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         "Counter": "3",
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
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         "MSRIndex": "0x3F6",
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         "Errata": "BDM100, BDM35",
382
-        "PublicDescription": "This event counts loads with latency value being above 64.",
382
+        "PublicDescription": "Counts randomly selected loads with latency value being above 64.",
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         "TakenAlone": "1",
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         "SampleAfterValue": "2003",
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         "CounterHTOff": "3"
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@@ -387,14 +387,14 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 128",
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+        "BriefDescription": "Randomly selected loads with latency value being above 128",
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         "PEBS": "2",
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         "MSRValue": "0x80",
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         "Counter": "3",
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
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         "MSRIndex": "0x3F6",
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         "Errata": "BDM100, BDM35",
397
-        "PublicDescription": "This event counts loads with latency value being above 128.",
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+        "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
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         "TakenAlone": "1",
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         "SampleAfterValue": "1009",
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         "CounterHTOff": "3"
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@@ -402,14 +402,14 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 256",
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+        "BriefDescription": "Randomly selected loads with latency value being above 256",
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         "PEBS": "2",
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         "MSRValue": "0x100",
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         "Counter": "3",
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
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         "MSRIndex": "0x3F6",
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         "Errata": "BDM100, BDM35",
412
-        "PublicDescription": "This event counts loads with latency value being above 256.",
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+        "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
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         "TakenAlone": "1",
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         "SampleAfterValue": "503",
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         "CounterHTOff": "3"
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@@ -417,14 +417,14 @@
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     {
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         "EventCode": "0xCD",
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         "UMask": "0x1",
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-        "BriefDescription": "Loads with latency value being above 512",
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+        "BriefDescription": "Randomly selected loads with latency value being above 512",
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         "PEBS": "2",
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         "MSRValue": "0x200",
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         "Counter": "3",
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
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         "MSRIndex": "0x3F6",
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         "Errata": "BDM100, BDM35",
427
-        "PublicDescription": "This event counts loads with latency value being above 512.",
427
+        "PublicDescription": "Counts randomly selected loads with latency value being above 512.",
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         "TakenAlone": "1",
429
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         "SampleAfterValue": "101",
430
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         "CounterHTOff": "3"
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@@ -433,12 +433,12 @@
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         "Offcore": "1",
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         "EventCode": "0xB7, 0xBB",
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         "UMask": "0x1",
436
-        "BriefDescription": "Counts all requests that miss in the L3",
437
-        "MSRValue": "0x3fbfc08fff",
436
+        "BriefDescription": "Counts all requests miss in the L3",
437
+        "MSRValue": "0x3FBFC08FFF",
438
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         "Counter": "0,1,2,3",
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         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
440
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         "MSRIndex": "0x1a6,0x1a7",
441
-        "PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
441
+        "PublicDescription": "Counts all requests miss in the L3",
442
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         "SampleAfterValue": "100003",
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         "CounterHTOff": "0,1,2,3"
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     },
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@@ -446,12 +446,12 @@
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         "Offcore": "1",
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         "EventCode": "0xB7, 0xBB",
448
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         "UMask": "0x1",
449
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache",
450
-        "MSRValue": "0x087fc007f7",
449
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
450
+        "MSRValue": "0x087FC007F7",
451
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         "Counter": "0,1,2,3",
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         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
453
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         "MSRIndex": "0x1a6,0x1a7",
454
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
454
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
455
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         "SampleAfterValue": "100003",
456
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         "CounterHTOff": "0,1,2,3"
457
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     },
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@@ -459,12 +459,12 @@
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         "Offcore": "1",
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         "EventCode": "0xB7, 0xBB",
461
461
         "UMask": "0x1",
462
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache",
463
-        "MSRValue": "0x103fc007f7",
462
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
463
+        "MSRValue": "0x103FC007F7",
464
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         "Counter": "0,1,2,3",
465
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         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
466
466
         "MSRIndex": "0x1a6,0x1a7",
467
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
467
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
468
468
         "SampleAfterValue": "100003",
469
469
         "CounterHTOff": "0,1,2,3"
470
470
     },
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@@ -472,12 +472,12 @@
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         "Offcore": "1",
473
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         "EventCode": "0xB7, 0xBB",
474
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         "UMask": "0x1",
475
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram",
476
-        "MSRValue": "0x063bc007f7",
475
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
476
+        "MSRValue": "0x063BC007F7",
477
477
         "Counter": "0,1,2,3",
478
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         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
479
479
         "MSRIndex": "0x1a6,0x1a7",
480
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
480
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
481
481
         "SampleAfterValue": "100003",
482
482
         "CounterHTOff": "0,1,2,3"
483
483
     },
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@@ -485,12 +485,12 @@
485
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         "Offcore": "1",
486
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         "EventCode": "0xB7, 0xBB",
487
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         "UMask": "0x1",
488
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",
489
-        "MSRValue": "0x06040007f7",
488
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
489
+        "MSRValue": "0x06040007F7",
490
490
         "Counter": "0,1,2,3",
491
491
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
492
492
         "MSRIndex": "0x1a6,0x1a7",
493
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
493
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
494
494
         "SampleAfterValue": "100003",
495
495
         "CounterHTOff": "0,1,2,3"
496
496
     },
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@@ -498,12 +498,12 @@
498
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         "Offcore": "1",
499
499
         "EventCode": "0xB7, 0xBB",
500
500
         "UMask": "0x1",
501
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",
502
-        "MSRValue": "0x3fbfc007f7",
501
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
502
+        "MSRValue": "0x3FBFC007F7",
503
503
         "Counter": "0,1,2,3",
504
504
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
505
505
         "MSRIndex": "0x1a6,0x1a7",
506
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
506
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
507
507
         "SampleAfterValue": "100003",
508
508
         "CounterHTOff": "0,1,2,3"
509
509
     },
..
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@@ -511,12 +511,12 @@
511
511
         "Offcore": "1",
512
512
         "EventCode": "0xB7, 0xBB",
513
513
         "UMask": "0x1",
514
-        "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",
514
+        "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
515
515
         "MSRValue": "0x0604000244",
516
516
         "Counter": "0,1,2,3",
517
517
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
518
518
         "MSRIndex": "0x1a6,0x1a7",
519
-        "PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
519
+        "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
520
520
         "SampleAfterValue": "100003",
521
521
         "CounterHTOff": "0,1,2,3"
522
522
     },
..
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@@ -524,12 +524,12 @@
524
524
         "Offcore": "1",
525
525
         "EventCode": "0xB7, 0xBB",
526
526
         "UMask": "0x1",
527
-        "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",
528
-        "MSRValue": "0x3fbfc00244",
527
+        "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
528
+        "MSRValue": "0x3FBFC00244",
529
529
         "Counter": "0,1,2,3",
530
530
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
531
531
         "MSRIndex": "0x1a6,0x1a7",
532
-        "PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
532
+        "PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
533
533
         "SampleAfterValue": "100003",
534
534
         "CounterHTOff": "0,1,2,3"
535
535
     },
..
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@@ -537,12 +537,12 @@
537
537
         "Offcore": "1",
538
538
         "EventCode": "0xB7, 0xBB",
539
539
         "UMask": "0x1",
540
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",
540
+        "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
541
541
         "MSRValue": "0x0604000122",
542
542
         "Counter": "0,1,2,3",
543
543
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
544
544
         "MSRIndex": "0x1a6,0x1a7",
545
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
545
+        "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
546
546
         "SampleAfterValue": "100003",
547
547
         "CounterHTOff": "0,1,2,3"
548
548
     },
..
..
@@ -550,12 +550,12 @@
550
550
         "Offcore": "1",
551
551
         "EventCode": "0xB7, 0xBB",
552
552
         "UMask": "0x1",
553
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",
554
-        "MSRValue": "0x3fbfc00122",
553
+        "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
554
+        "MSRValue": "0x3FBFC00122",
555
555
         "Counter": "0,1,2,3",
556
556
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
557
557
         "MSRIndex": "0x1a6,0x1a7",
558
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
558
+        "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3",
559
559
         "SampleAfterValue": "100003",
560
560
         "CounterHTOff": "0,1,2,3"
561
561
     },
..
..
@@ -563,12 +563,12 @@
563
563
         "Offcore": "1",
564
564
         "EventCode": "0xB7, 0xBB",
565
565
         "UMask": "0x1",
566
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache",
567
-        "MSRValue": "0x087fc00091",
566
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
567
+        "MSRValue": "0x087FC00091",
568
568
         "Counter": "0,1,2,3",
569
569
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
570
570
         "MSRIndex": "0x1a6,0x1a7",
571
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
571
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
572
572
         "SampleAfterValue": "100003",
573
573
         "CounterHTOff": "0,1,2,3"
574
574
     },
..
..
@@ -576,12 +576,12 @@
576
576
         "Offcore": "1",
577
577
         "EventCode": "0xB7, 0xBB",
578
578
         "UMask": "0x1",
579
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache",
580
-        "MSRValue": "0x103fc00091",
579
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
580
+        "MSRValue": "0x103FC00091",
581
581
         "Counter": "0,1,2,3",
582
582
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
583
583
         "MSRIndex": "0x1a6,0x1a7",
584
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
584
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
585
585
         "SampleAfterValue": "100003",
586
586
         "CounterHTOff": "0,1,2,3"
587
587
     },
..
..
@@ -589,12 +589,12 @@
589
589
         "Offcore": "1",
590
590
         "EventCode": "0xB7, 0xBB",
591
591
         "UMask": "0x1",
592
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram",
593
-        "MSRValue": "0x063bc00091",
592
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
593
+        "MSRValue": "0x063BC00091",
594
594
         "Counter": "0,1,2,3",
595
595
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
596
596
         "MSRIndex": "0x1a6,0x1a7",
597
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
597
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
598
598
         "SampleAfterValue": "100003",
599
599
         "CounterHTOff": "0,1,2,3"
600
600
     },
..
..
@@ -602,12 +602,12 @@
602
602
         "Offcore": "1",
603
603
         "EventCode": "0xB7, 0xBB",
604
604
         "UMask": "0x1",
605
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",
605
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
606
606
         "MSRValue": "0x0604000091",
607
607
         "Counter": "0,1,2,3",
608
608
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
609
609
         "MSRIndex": "0x1a6,0x1a7",
610
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
610
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
611
611
         "SampleAfterValue": "100003",
612
612
         "CounterHTOff": "0,1,2,3"
613
613
     },
..
..
@@ -615,12 +615,12 @@
615
615
         "Offcore": "1",
616
616
         "EventCode": "0xB7, 0xBB",
617
617
         "UMask": "0x1",
618
-        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",
619
-        "MSRValue": "0x3fbfc00091",
618
+        "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
619
+        "MSRValue": "0x3FBFC00091",
620
620
         "Counter": "0,1,2,3",
621
621
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
622
622
         "MSRIndex": "0x1a6,0x1a7",
623
-        "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
623
+        "PublicDescription": "Counts all demand & prefetch data reads miss in the L3",
624
624
         "SampleAfterValue": "100003",
625
625
         "CounterHTOff": "0,1,2,3"
626
626
     },
..
..
@@ -628,12 +628,12 @@
628
628
         "Offcore": "1",
629
629
         "EventCode": "0xB7, 0xBB",
630
630
         "UMask": "0x1",
631
-        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",
632
-        "MSRValue": "0x3fbfc00200",
631
+        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
632
+        "MSRValue": "0x3FBFC00200",
633
633
         "Counter": "0,1,2,3",
634
634
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
635
635
         "MSRIndex": "0x1a6,0x1a7",
636
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
636
+        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
637
637
         "SampleAfterValue": "100003",
638
638
         "CounterHTOff": "0,1,2,3"
639
639
     },
..
..
@@ -641,12 +641,12 @@
641
641
         "Offcore": "1",
642
642
         "EventCode": "0xB7, 0xBB",
643
643
         "UMask": "0x1",
644
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3",
645
-        "MSRValue": "0x3fbfc00100",
644
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
645
+        "MSRValue": "0x3FBFC00100",
646
646
         "Counter": "0,1,2,3",
647
647
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
648
648
         "MSRIndex": "0x1a6,0x1a7",
649
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
649
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
650
650
         "SampleAfterValue": "100003",
651
651
         "CounterHTOff": "0,1,2,3"
652
652
     },
..
..
@@ -654,12 +654,12 @@
654
654
         "Offcore": "1",
655
655
         "EventCode": "0xB7, 0xBB",
656
656
         "UMask": "0x1",
657
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache",
658
-        "MSRValue": "0x103fc00002",
657
+        "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
658
+        "MSRValue": "0x103FC00002",
659
659
         "Counter": "0,1,2,3",
660
660
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
661
661
         "MSRIndex": "0x1a6,0x1a7",
662
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
662
+        "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
663
663
         "SampleAfterValue": "100003",
664
664
         "CounterHTOff": "0,1,2,3"
665
665
     },
..
..
@@ -667,12 +667,12 @@
667
667
         "Offcore": "1",
668
668
         "EventCode": "0xB7, 0xBB",
669
669
         "UMask": "0x1",
670
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",
671
-        "MSRValue": "0x3fbfc00002",
670
+        "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
671
+        "MSRValue": "0x3FBFC00002",
672
672
         "Counter": "0,1,2,3",
673
673
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
674
674
         "MSRIndex": "0x1a6,0x1a7",
675
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
675
+        "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
676
676
         "SampleAfterValue": "100003",
677
677
         "CounterHTOff": "0,1,2,3"
678
678
     }