.. | .. |
---|
1 | 1 | [ |
---|
2 | 2 | { |
---|
3 | | - "EventCode": "0x00", |
---|
4 | 3 | "UMask": "0x1", |
---|
5 | 4 | "BriefDescription": "Instructions retired from execution.", |
---|
6 | 5 | "Counter": "Fixed counter 0", |
---|
.. | .. |
---|
10 | 9 | "CounterHTOff": "Fixed counter 0" |
---|
11 | 10 | }, |
---|
12 | 11 | { |
---|
13 | | - "EventCode": "0x00", |
---|
14 | 12 | "UMask": "0x2", |
---|
15 | 13 | "BriefDescription": "Core cycles when the thread is not in halt state", |
---|
16 | 14 | "Counter": "Fixed counter 1", |
---|
.. | .. |
---|
20 | 18 | "CounterHTOff": "Fixed counter 1" |
---|
21 | 19 | }, |
---|
22 | 20 | { |
---|
23 | | - "EventCode": "0x00", |
---|
24 | 21 | "UMask": "0x2", |
---|
25 | 22 | "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", |
---|
26 | 23 | "Counter": "Fixed counter 1", |
---|
.. | .. |
---|
30 | 27 | "CounterHTOff": "Fixed counter 1" |
---|
31 | 28 | }, |
---|
32 | 29 | { |
---|
33 | | - "EventCode": "0x00", |
---|
34 | 30 | "UMask": "0x3", |
---|
35 | 31 | "BriefDescription": "Reference cycles when the core is not in halt state.", |
---|
36 | 32 | "Counter": "Fixed counter 2", |
---|