add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
..
..
@@ -1,122 +1,122 @@
1
1
 [
2
2
     {
3
-        "ArchStdEvent": "L1D_CACHE_RD",
3
+        "ArchStdEvent": "L1D_CACHE_RD"
4
4
     },
5
5
     {
6
-        "ArchStdEvent": "L1D_CACHE_WR",
6
+        "ArchStdEvent": "L1D_CACHE_WR"
7
7
     },
8
8
     {
9
-        "ArchStdEvent": "L1D_CACHE_REFILL_RD",
9
+        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
10
10
     },
11
11
     {
12
-        "ArchStdEvent": "L1D_CACHE_REFILL_WR",
12
+        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
13
13
     },
14
14
     {
15
-        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
15
+        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
16
16
     },
17
17
     {
18
-        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
18
+        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
19
19
     },
20
20
     {
21
-        "ArchStdEvent": "L1D_CACHE_INVAL",
21
+        "ArchStdEvent": "L1D_CACHE_INVAL"
22
22
     },
23
23
     {
24
-        "ArchStdEvent": "L1D_TLB_REFILL_RD",
24
+        "ArchStdEvent": "L1D_TLB_REFILL_RD"
25
25
     },
26
26
     {
27
-        "ArchStdEvent": "L1D_TLB_REFILL_WR",
27
+        "ArchStdEvent": "L1D_TLB_REFILL_WR"
28
28
     },
29
29
     {
30
-        "ArchStdEvent": "L1D_TLB_RD",
30
+        "ArchStdEvent": "L1D_TLB_RD"
31
31
     },
32
32
     {
33
-        "ArchStdEvent": "L1D_TLB_WR",
33
+        "ArchStdEvent": "L1D_TLB_WR"
34
34
     },
35
35
     {
36
-        "ArchStdEvent": "L2D_CACHE_RD",
36
+        "ArchStdEvent": "L2D_CACHE_RD"
37
37
     },
38
38
     {
39
-        "ArchStdEvent": "L2D_CACHE_WR",
39
+        "ArchStdEvent": "L2D_CACHE_WR"
40
40
     },
41
41
     {
42
-        "ArchStdEvent": "L2D_CACHE_REFILL_RD",
42
+        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
43
43
     },
44
44
     {
45
-        "ArchStdEvent": "L2D_CACHE_REFILL_WR",
45
+        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
46
46
     },
47
47
     {
48
-        "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
48
+        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
49
49
     },
50
50
     {
51
-        "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
51
+        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
52
52
     },
53
53
     {
54
-        "ArchStdEvent": "L2D_CACHE_INVAL",
54
+        "ArchStdEvent": "L2D_CACHE_INVAL"
55
55
     },
56
56
     {
57
57
         "PublicDescription": "Level 1 instruction cache prefetch access count",
58
58
         "EventCode": "0x102e",
59
59
         "EventName": "L1I_CACHE_PRF",
60
-        "BriefDescription": "L1I cache prefetch access count",
60
+        "BriefDescription": "L1I cache prefetch access count"
61
61
     },
62
62
     {
63
63
         "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
64
64
         "EventCode": "0x102f",
65
65
         "EventName": "L1I_CACHE_PRF_REFILL",
66
-        "BriefDescription": "L1I cache miss due to prefetch access count",
66
+        "BriefDescription": "L1I cache miss due to prefetch access count"
67
67
     },
68
68
     {
69
69
         "PublicDescription": "Instruction queue is empty",
70
70
         "EventCode": "0x1043",
71
71
         "EventName": "IQ_IS_EMPTY",
72
-        "BriefDescription": "Instruction queue is empty",
72
+        "BriefDescription": "Instruction queue is empty"
73
73
     },
74
74
     {
75
75
         "PublicDescription": "Instruction fetch stall cycles",
76
76
         "EventCode": "0x1044",
77
77
         "EventName": "IF_IS_STALL",
78
-        "BriefDescription": "Instruction fetch stall cycles",
78
+        "BriefDescription": "Instruction fetch stall cycles"
79
79
     },
80
80
     {
81
81
         "PublicDescription": "Instructions can receive, but not send",
82
82
         "EventCode": "0x2014",
83
83
         "EventName": "FETCH_BUBBLE",
84
-        "BriefDescription": "Instructions can receive, but not send",
84
+        "BriefDescription": "Instructions can receive, but not send"
85
85
     },
86
86
     {
87
87
         "PublicDescription": "Prefetch request from LSU",
88
88
         "EventCode": "0x6013",
89
89
         "EventName": "PRF_REQ",
90
-        "BriefDescription": "Prefetch request from LSU",
90
+        "BriefDescription": "Prefetch request from LSU"
91
91
     },
92
92
     {
93
93
         "PublicDescription": "Hit on prefetched data",
94
94
         "EventCode": "0x6014",
95
95
         "EventName": "HIT_ON_PRF",
96
-        "BriefDescription": "Hit on prefetched data",
96
+        "BriefDescription": "Hit on prefetched data"
97
97
     },
98
98
     {
99
99
         "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
100
100
         "EventCode": "0x7001",
101
101
         "EventName": "EXE_STALL_CYCLE",
102
-        "BriefDescription": "Cycles of that the number of issue ups are less than 4",
102
+        "BriefDescription": "Cycles of that the number of issue ups are less than 4"
103
103
     },
104
104
     {
105
105
         "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
106
106
         "EventCode": "0x7004",
107
107
         "EventName": "MEM_STALL_ANYLOAD",
108
-        "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
108
+        "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved"
109
109
     },
110
110
     {
111
111
         "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
112
112
         "EventCode": "0x7006",
113
113
         "EventName": "MEM_STALL_L1MISS",
114
-        "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
114
+        "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill"
115
115
     },
116
116
     {
117
117
         "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
118
118
         "EventCode": "0x7007",
119
119
         "EventName": "MEM_STALL_L2MISS",
120
-        "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
121
-    },
120
+        "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache"
121
+    }
122
122
 ]