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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/sound/soc/qcom/lpass-lpaif-reg.h
....@@ -1,14 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 and
6
- * only version 2 as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
146 #ifndef __LPASS_LPAIF_REG_H__
....@@ -20,65 +12,57 @@
2012 	(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
2113 
2214 #define LPAIF_I2SCTL_REG(v, port)	LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))
23
-#define LPAIF_I2SCTL_LOOPBACK_MASK	0x8000
24
-#define LPAIF_I2SCTL_LOOPBACK_SHIFT	15
25
-#define LPAIF_I2SCTL_LOOPBACK_DISABLE	(0 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
26
-#define LPAIF_I2SCTL_LOOPBACK_ENABLE	(1 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
2715 
28
-#define LPAIF_I2SCTL_SPKEN_MASK		0x4000
29
-#define LPAIF_I2SCTL_SPKEN_SHIFT	14
30
-#define LPAIF_I2SCTL_SPKEN_DISABLE	(0 << LPAIF_I2SCTL_SPKEN_SHIFT)
31
-#define LPAIF_I2SCTL_SPKEN_ENABLE	(1 << LPAIF_I2SCTL_SPKEN_SHIFT)
16
+#define LPAIF_I2SCTL_LOOPBACK_DISABLE	0
17
+#define LPAIF_I2SCTL_LOOPBACK_ENABLE	1
3218 
33
-#define LPAIF_I2SCTL_SPKMODE_MASK	0x3C00
34
-#define LPAIF_I2SCTL_SPKMODE_SHIFT	10
35
-#define LPAIF_I2SCTL_SPKMODE_NONE	(0 << LPAIF_I2SCTL_SPKMODE_SHIFT)
36
-#define LPAIF_I2SCTL_SPKMODE_SD0	(1 << LPAIF_I2SCTL_SPKMODE_SHIFT)
37
-#define LPAIF_I2SCTL_SPKMODE_SD1	(2 << LPAIF_I2SCTL_SPKMODE_SHIFT)
38
-#define LPAIF_I2SCTL_SPKMODE_SD2	(3 << LPAIF_I2SCTL_SPKMODE_SHIFT)
39
-#define LPAIF_I2SCTL_SPKMODE_SD3	(4 << LPAIF_I2SCTL_SPKMODE_SHIFT)
40
-#define LPAIF_I2SCTL_SPKMODE_QUAD01	(5 << LPAIF_I2SCTL_SPKMODE_SHIFT)
41
-#define LPAIF_I2SCTL_SPKMODE_QUAD23	(6 << LPAIF_I2SCTL_SPKMODE_SHIFT)
42
-#define LPAIF_I2SCTL_SPKMODE_6CH	(7 << LPAIF_I2SCTL_SPKMODE_SHIFT)
43
-#define LPAIF_I2SCTL_SPKMODE_8CH	(8 << LPAIF_I2SCTL_SPKMODE_SHIFT)
19
+#define LPAIF_I2SCTL_SPKEN_DISABLE	0
20
+#define LPAIF_I2SCTL_SPKEN_ENABLE	1
4421 
45
-#define LPAIF_I2SCTL_SPKMONO_MASK	0x0200
46
-#define LPAIF_I2SCTL_SPKMONO_SHIFT	9
47
-#define LPAIF_I2SCTL_SPKMONO_STEREO	(0 << LPAIF_I2SCTL_SPKMONO_SHIFT)
48
-#define LPAIF_I2SCTL_SPKMONO_MONO	(1 << LPAIF_I2SCTL_SPKMONO_SHIFT)
22
+#define LPAIF_I2SCTL_MODE_NONE		0
23
+#define LPAIF_I2SCTL_MODE_SD0		1
24
+#define LPAIF_I2SCTL_MODE_SD1		2
25
+#define LPAIF_I2SCTL_MODE_SD2		3
26
+#define LPAIF_I2SCTL_MODE_SD3		4
27
+#define LPAIF_I2SCTL_MODE_QUAD01	5
28
+#define LPAIF_I2SCTL_MODE_QUAD23	6
29
+#define LPAIF_I2SCTL_MODE_6CH		7
30
+#define LPAIF_I2SCTL_MODE_8CH		8
31
+#define LPAIF_I2SCTL_MODE_10CH		9
32
+#define LPAIF_I2SCTL_MODE_12CH		10
33
+#define LPAIF_I2SCTL_MODE_14CH		11
34
+#define LPAIF_I2SCTL_MODE_16CH		12
35
+#define LPAIF_I2SCTL_MODE_SD4		13
36
+#define LPAIF_I2SCTL_MODE_SD5		14
37
+#define LPAIF_I2SCTL_MODE_SD6		15
38
+#define LPAIF_I2SCTL_MODE_SD7		16
39
+#define LPAIF_I2SCTL_MODE_QUAD45	17
40
+#define LPAIF_I2SCTL_MODE_QUAD47	18
41
+#define LPAIF_I2SCTL_MODE_8CH_2		19
4942 
50
-#define LPAIF_I2SCTL_MICEN_MASK		GENMASK(8, 8)
51
-#define LPAIF_I2SCTL_MICEN_SHIFT	8
52
-#define LPAIF_I2SCTL_MICEN_DISABLE	(0 << LPAIF_I2SCTL_MICEN_SHIFT)
53
-#define LPAIF_I2SCTL_MICEN_ENABLE	(1 << LPAIF_I2SCTL_MICEN_SHIFT)
43
+#define LPAIF_I2SCTL_SPKMODE(mode)	mode
5444 
55
-#define LPAIF_I2SCTL_MICMODE_MASK	GENMASK(7, 4)
56
-#define LPAIF_I2SCTL_MICMODE_SHIFT	4
57
-#define LPAIF_I2SCTL_MICMODE_NONE	(0 << LPAIF_I2SCTL_MICMODE_SHIFT)
58
-#define LPAIF_I2SCTL_MICMODE_SD0	(1 << LPAIF_I2SCTL_MICMODE_SHIFT)
59
-#define LPAIF_I2SCTL_MICMODE_SD1	(2 << LPAIF_I2SCTL_MICMODE_SHIFT)
60
-#define LPAIF_I2SCTL_MICMODE_SD2	(3 << LPAIF_I2SCTL_MICMODE_SHIFT)
61
-#define LPAIF_I2SCTL_MICMODE_SD3	(4 << LPAIF_I2SCTL_MICMODE_SHIFT)
62
-#define LPAIF_I2SCTL_MICMODE_QUAD01	(5 << LPAIF_I2SCTL_MICMODE_SHIFT)
63
-#define LPAIF_I2SCTL_MICMODE_QUAD23	(6 << LPAIF_I2SCTL_MICMODE_SHIFT)
64
-#define LPAIF_I2SCTL_MICMODE_6CH	(7 << LPAIF_I2SCTL_MICMODE_SHIFT)
65
-#define LPAIF_I2SCTL_MICMODE_8CH	(8 << LPAIF_I2SCTL_MICMODE_SHIFT)
45
+#define LPAIF_I2SCTL_SPKMONO_STEREO	0
46
+#define LPAIF_I2SCTL_SPKMONO_MONO	1
6647 
67
-#define LPAIF_I2SCTL_MIMONO_MASK	GENMASK(3, 3)
68
-#define LPAIF_I2SCTL_MICMONO_SHIFT	3
69
-#define LPAIF_I2SCTL_MICMONO_STEREO	(0 << LPAIF_I2SCTL_MICMONO_SHIFT)
70
-#define LPAIF_I2SCTL_MICMONO_MONO	(1 << LPAIF_I2SCTL_MICMONO_SHIFT)
48
+#define LPAIF_I2SCTL_MICEN_DISABLE	0
49
+#define LPAIF_I2SCTL_MICEN_ENABLE	1
7150 
72
-#define LPAIF_I2SCTL_WSSRC_MASK		0x0004
73
-#define LPAIF_I2SCTL_WSSRC_SHIFT	2
74
-#define LPAIF_I2SCTL_WSSRC_INTERNAL	(0 << LPAIF_I2SCTL_WSSRC_SHIFT)
75
-#define LPAIF_I2SCTL_WSSRC_EXTERNAL	(1 << LPAIF_I2SCTL_WSSRC_SHIFT)
51
+#define LPAIF_I2SCTL_MICMODE(mode)	mode
7652 
77
-#define LPAIF_I2SCTL_BITWIDTH_MASK	0x0003
78
-#define LPAIF_I2SCTL_BITWIDTH_SHIFT	0
79
-#define LPAIF_I2SCTL_BITWIDTH_16	(0 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
80
-#define LPAIF_I2SCTL_BITWIDTH_24	(1 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
81
-#define LPAIF_I2SCTL_BITWIDTH_32	(2 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
53
+#define LPAIF_I2SCTL_MICMONO_STEREO	0
54
+#define LPAIF_I2SCTL_MICMONO_MONO	1
55
+
56
+#define LPAIF_I2SCTL_WSSRC_INTERNAL	0
57
+#define LPAIF_I2SCTL_WSSRC_EXTERNAL	1
58
+
59
+#define LPAIF_I2SCTL_BITWIDTH_16	0
60
+#define LPAIF_I2SCTL_BITWIDTH_24	1
61
+#define LPAIF_I2SCTL_BITWIDTH_32	2
62
+
63
+#define LPAIF_I2SCTL_RESET_STATE	0x003C0004
64
+#define LPAIF_DMACTL_RESET_STATE	0x00200000
65
+
8266 
8367 /* LPAIF IRQ */
8468 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \
....@@ -90,6 +74,14 @@
9074 #define LPAIF_IRQSTAT_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
9175 #define LPAIF_IRQCLEAR_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
9276 
77
+
78
+#define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr)  \
79
+	((v->hdmi_irq_reg_base) + (addr))
80
+
81
+#define LPASS_HDMITX_APP_IRQEN_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)
82
+#define LPASS_HDMITX_APP_IRQSTAT_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)
83
+#define LPASS_HDMITX_APP_IRQCLEAR_REG(v)		LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)
84
+
9385 #define LPAIF_IRQ_BITSTRIDE		3
9486 
9587 #define LPAIF_IRQ_PER(chan)		(1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
....@@ -97,8 +89,22 @@
9789 #define LPAIF_IRQ_ERR(chan)		(4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
9890 
9991 #define LPAIF_IRQ_ALL(chan)		(7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
92
+#define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan)	(1 << (14 + chan))
93
+#define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan)	(1 << (24 + chan))
94
+#define LPAIF_IRQ_HDMI_METADONE		BIT(23)
10095 
10196 /* LPAIF DMA */
97
+#define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \
98
+	(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
99
+
100
+#define LPAIF_HDMI_RDMACTL_AUDINTF(id)	(id << LPAIF_RDMACTL_AUDINTF_SHIFT)
101
+
102
+#define LPAIF_HDMI_RDMACTL_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))
103
+#define LPAIF_HDMI_RDMABASE_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))
104
+#define	LPAIF_HDMI_RDMABUFF_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))
105
+#define LPAIF_HDMI_RDMACURR_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))
106
+#define	LPAIF_HDMI_RDMAPER_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))
107
+#define	LPAIF_HDMI_RDMAPERCNT_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))
102108 
103109 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
104110 	(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
....@@ -123,54 +129,76 @@
123129 #define	LPAIF_WRDMAPER_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
124130 #define	LPAIF_WRDMAPERCNT_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
125131 
126
-#define __LPAIF_DMA_REG(v, chan, dir, reg)  \
127
-	(dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
128
-		LPAIF_RDMA##reg##_REG(v, chan) : \
129
-		LPAIF_WRDMA##reg##_REG(v, chan)
132
+#define LPAIF_INTFDMA_REG(v, chan, reg, dai_id)  \
133
+	((dai_id ==  LPASS_DP_RX) ? \
134
+		LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
135
+		 LPAIF_RDMA##reg##_REG(v, chan))
130136 
131
-#define LPAIF_DMACTL_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, CTL)
132
-#define LPAIF_DMABASE_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BASE)
133
-#define	LPAIF_DMABUFF_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BUFF)
134
-#define LPAIF_DMACURR_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, CURR)
135
-#define	LPAIF_DMAPER_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, PER)
136
-#define	LPAIF_DMAPERCNT_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, PERCNT)
137
+#define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id)  \
138
+	((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
139
+		(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
140
+		LPAIF_WRDMA##reg##_REG(v, chan))
137141 
138
-#define LPAIF_DMACTL_BURSTEN_MASK	0x800
139
-#define LPAIF_DMACTL_BURSTEN_SHIFT	11
140
-#define LPAIF_DMACTL_BURSTEN_SINGLE	(0 << LPAIF_DMACTL_BURSTEN_SHIFT)
141
-#define LPAIF_DMACTL_BURSTEN_INCR4	(1 << LPAIF_DMACTL_BURSTEN_SHIFT)
142
+#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id)
143
+#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id)
144
+#define	LPAIF_DMABUFF_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)
145
+#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id)
146
+#define	LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PER, dai_id)
147
+#define	LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)
142148 
143
-#define LPAIF_DMACTL_WPSCNT_MASK	0x700
144
-#define LPAIF_DMACTL_WPSCNT_SHIFT	8
145
-#define LPAIF_DMACTL_WPSCNT_ONE	(0 << LPAIF_DMACTL_WPSCNT_SHIFT)
146
-#define LPAIF_DMACTL_WPSCNT_TWO	(1 << LPAIF_DMACTL_WPSCNT_SHIFT)
147
-#define LPAIF_DMACTL_WPSCNT_THREE	(2 << LPAIF_DMACTL_WPSCNT_SHIFT)
148
-#define LPAIF_DMACTL_WPSCNT_FOUR	(3 << LPAIF_DMACTL_WPSCNT_SHIFT)
149
-#define LPAIF_DMACTL_WPSCNT_SIX	(5 << LPAIF_DMACTL_WPSCNT_SHIFT)
150
-#define LPAIF_DMACTL_WPSCNT_EIGHT	(7 << LPAIF_DMACTL_WPSCNT_SHIFT)
149
+#define LPAIF_DMACTL_BURSTEN_SINGLE	0
150
+#define LPAIF_DMACTL_BURSTEN_INCR4	1
151151 
152
-#define LPAIF_DMACTL_AUDINTF_MASK	0x0F0
153
-#define LPAIF_DMACTL_AUDINTF_SHIFT	4
154
-#define LPAIF_DMACTL_AUDINTF(id)	(id << LPAIF_DMACTL_AUDINTF_SHIFT)
152
+#define LPAIF_DMACTL_WPSCNT_ONE		0
153
+#define LPAIF_DMACTL_WPSCNT_TWO		1
154
+#define LPAIF_DMACTL_WPSCNT_THREE	2
155
+#define LPAIF_DMACTL_WPSCNT_FOUR	3
156
+#define LPAIF_DMACTL_WPSCNT_SIX		5
157
+#define LPAIF_DMACTL_WPSCNT_EIGHT	7
158
+#define LPAIF_DMACTL_WPSCNT_TEN		9
159
+#define LPAIF_DMACTL_WPSCNT_TWELVE	11
160
+#define LPAIF_DMACTL_WPSCNT_FOURTEEN	13
161
+#define LPAIF_DMACTL_WPSCNT_SIXTEEN	15
155162 
156
-#define LPAIF_DMACTL_FIFOWM_MASK	0x00E
157
-#define LPAIF_DMACTL_FIFOWM_SHIFT	1
158
-#define LPAIF_DMACTL_FIFOWM_1		(0 << LPAIF_DMACTL_FIFOWM_SHIFT)
159
-#define LPAIF_DMACTL_FIFOWM_2		(1 << LPAIF_DMACTL_FIFOWM_SHIFT)
160
-#define LPAIF_DMACTL_FIFOWM_3		(2 << LPAIF_DMACTL_FIFOWM_SHIFT)
161
-#define LPAIF_DMACTL_FIFOWM_4		(3 << LPAIF_DMACTL_FIFOWM_SHIFT)
162
-#define LPAIF_DMACTL_FIFOWM_5		(4 << LPAIF_DMACTL_FIFOWM_SHIFT)
163
-#define LPAIF_DMACTL_FIFOWM_6		(5 << LPAIF_DMACTL_FIFOWM_SHIFT)
164
-#define LPAIF_DMACTL_FIFOWM_7		(6 << LPAIF_DMACTL_FIFOWM_SHIFT)
165
-#define LPAIF_DMACTL_FIFOWM_8		(7 << LPAIF_DMACTL_FIFOWM_SHIFT)
163
+#define LPAIF_DMACTL_AUDINTF(id)	id
166164 
167
-#define LPAIF_DMACTL_ENABLE_MASK	0x1
168
-#define LPAIF_DMACTL_ENABLE_SHIFT	0
169
-#define LPAIF_DMACTL_ENABLE_OFF	(0 << LPAIF_DMACTL_ENABLE_SHIFT)
170
-#define LPAIF_DMACTL_ENABLE_ON		(1 << LPAIF_DMACTL_ENABLE_SHIFT)
165
+#define LPAIF_DMACTL_FIFOWM_1		0
166
+#define LPAIF_DMACTL_FIFOWM_2		1
167
+#define LPAIF_DMACTL_FIFOWM_3		2
168
+#define LPAIF_DMACTL_FIFOWM_4		3
169
+#define LPAIF_DMACTL_FIFOWM_5		4
170
+#define LPAIF_DMACTL_FIFOWM_6		5
171
+#define LPAIF_DMACTL_FIFOWM_7		6
172
+#define LPAIF_DMACTL_FIFOWM_8		7
173
+#define LPAIF_DMACTL_FIFOWM_9		8
174
+#define LPAIF_DMACTL_FIFOWM_10		9
175
+#define LPAIF_DMACTL_FIFOWM_11		10
176
+#define LPAIF_DMACTL_FIFOWM_12		11
177
+#define LPAIF_DMACTL_FIFOWM_13		12
178
+#define LPAIF_DMACTL_FIFOWM_14		13
179
+#define LPAIF_DMACTL_FIFOWM_15		14
180
+#define LPAIF_DMACTL_FIFOWM_16		15
181
+#define LPAIF_DMACTL_FIFOWM_17		16
182
+#define LPAIF_DMACTL_FIFOWM_18		17
183
+#define LPAIF_DMACTL_FIFOWM_19		18
184
+#define LPAIF_DMACTL_FIFOWM_20		19
185
+#define LPAIF_DMACTL_FIFOWM_21		20
186
+#define LPAIF_DMACTL_FIFOWM_22		21
187
+#define LPAIF_DMACTL_FIFOWM_23		22
188
+#define LPAIF_DMACTL_FIFOWM_24		23
189
+#define LPAIF_DMACTL_FIFOWM_25		24
190
+#define LPAIF_DMACTL_FIFOWM_26		25
191
+#define LPAIF_DMACTL_FIFOWM_27		26
192
+#define LPAIF_DMACTL_FIFOWM_28		27
193
+#define LPAIF_DMACTL_FIFOWM_29		28
194
+#define LPAIF_DMACTL_FIFOWM_30		29
195
+#define LPAIF_DMACTL_FIFOWM_31		30
196
+#define LPAIF_DMACTL_FIFOWM_32		31
171197 
172
-#define LPAIF_DMACTL_DYNCLK_MASK	BIT(12)
173
-#define LPAIF_DMACTL_DYNCLK_SHIFT	12
174
-#define LPAIF_DMACTL_DYNCLK_OFF	(0 << LPAIF_DMACTL_DYNCLK_SHIFT)
175
-#define LPAIF_DMACTL_DYNCLK_ON		(1 << LPAIF_DMACTL_DYNCLK_SHIFT)
198
+#define LPAIF_DMACTL_ENABLE_OFF		0
199
+#define LPAIF_DMACTL_ENABLE_ON		1
200
+
201
+#define LPAIF_DMACTL_DYNCLK_OFF		0
202
+#define LPAIF_DMACTL_DYNCLK_ON		1
203
+
176204 #endif /* __LPASS_LPAIF_REG_H__ */