.. | .. |
---|
56 | 56 | unsigned int next; |
---|
57 | 57 | |
---|
58 | 58 | /* |
---|
59 | | - * The IPI requires a seperate HW irq on each CPU. We require |
---|
| 59 | + * The IPI requires a separate HW irq on each CPU. We require |
---|
60 | 60 | * that the destination mask is consecutive. If an |
---|
61 | 61 | * implementation needs to support holes, it can reserve |
---|
62 | 62 | * several IPI ranges. |
---|
.. | .. |
---|
172 | 172 | |
---|
173 | 173 | /* |
---|
174 | 174 | * Get the real hardware irq number if the underlying implementation |
---|
175 | | - * uses a seperate irq per cpu. If the underlying implementation uses |
---|
| 175 | + * uses a separate irq per cpu. If the underlying implementation uses |
---|
176 | 176 | * a single hardware irq for all cpus then the IPI send mechanism |
---|
177 | 177 | * needs to take care of the cpu destinations. |
---|
178 | 178 | */ |
---|