~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,15 +1,7 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
1	2	/*
2	3	* Definitions for the NVM Express interface
3	4	* Copyright (c) 2011-2014, Intel Corporation.
4		- *
5		- * This program is free software; you can redistribute it and/or modify it
6		- * under the terms and conditions of the GNU General Public License,
7		- * version 2, as published by the Free Software Foundation.
8		- *
9		- * This program is distributed in the hope it will be useful, but WITHOUT
10		- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11		- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12		- * more details.
13	5	*/
14	6
15	7	#ifndef _LINUX_NVME_H
..	..	@@ -46,21 +38,28 @@
46	38	NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47	39	NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48	40	NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
	41	+ NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
	42	+ NVMF_ADDR_FAMILY_MAX,
49	43	};
50	44
51	45	/* Transport Type codes for Discovery Log Page entry TRTYPE field */
52	46	enum {
53	47	NVMF_TRTYPE_RDMA = 1, /* RDMA */
54	48	NVMF_TRTYPE_FC = 2, /* Fibre Channel */
	49	+ NVMF_TRTYPE_TCP = 3, /* TCP/IP */
55	50	NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
56	51	NVMF_TRTYPE_MAX,
57	52	};
58	53
59	54	/* Transport Requirements codes for Discovery Log Page entry TREQ field */
60	55	enum {
61		- NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62		- NVMF_TREQ_REQUIRED = 1, /* Required */
63		- NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
	56	+ NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
	57	+ NVMF_TREQ_REQUIRED = 1, /* Required */
	58	+ NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
	59	+#define NVME_TREQ_SECURE_CHANNEL_MASK \
	60	+ (NVMF_TREQ_REQUIRED \| NVMF_TREQ_NOT_REQUIRED)
	61	+
	62	+ NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
64	63	};
65	64
66	65	/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
..	..	@@ -110,8 +109,25 @@
110	109	NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
111	110	NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
112	111	NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
113		- NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
	112	+ NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
114	113	NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
	114	+ NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
	115	+ NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
	116	+ NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
	117	+ * Location
	118	+ */
	119	+ NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
	120	+ * Space Control
	121	+ */
	122	+ NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
	123	+ NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
	124	+ NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
	125	+ NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
	126	+ * Buffer Size
	127	+ */
	128	+ NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
	129	+ * Write Throughput
	130	+ */
115	131	NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
116	132	};
117	133
..	..	@@ -119,8 +135,10 @@
119	135	#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
120	136	#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
121	137	#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
	138	+#define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
122	139	#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
123	140	#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
	141	+#define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
124	142
125	143	#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
126	144	#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
..	..	@@ -143,12 +161,12 @@
143	161	* Submission and Completion Queue Entry Sizes for the NVM command set.
144	162	* (In bytes and specified as a power of two (2^n)).
145	163	*/
	164	+#define NVME_ADM_SQES 6
146	165	#define NVME_NVM_IOSQES 6
147	166	#define NVME_NVM_IOCQES 4
148	167
149	168	enum {
150	169	NVME_CC_ENABLE = 1 << 0,
151		- NVME_CC_CSS_NVM = 0 << 4,
152	170	NVME_CC_EN_SHIFT = 0,
153	171	NVME_CC_CSS_SHIFT = 4,
154	172	NVME_CC_MPS_SHIFT = 7,
..	..	@@ -156,6 +174,9 @@
156	174	NVME_CC_SHN_SHIFT = 14,
157	175	NVME_CC_IOSQES_SHIFT = 16,
158	176	NVME_CC_IOCQES_SHIFT = 20,
	177	+ NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
	178	+ NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
	179	+ NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
159	180	NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
160	181	NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
161	182	NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
..	..	@@ -165,6 +186,8 @@
165	186	NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
166	187	NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
167	188	NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
	189	+ NVME_CAP_CSS_NVM = 1 << 0,
	190	+ NVME_CAP_CSS_CSI = 1 << 6,
168	191	NVME_CSTS_RDY = 1 << 0,
169	192	NVME_CSTS_CFS = 1 << 1,
170	193	NVME_CSTS_NSSRO = 1 << 4,
..	..	@@ -173,6 +196,8 @@
173	196	NVME_CSTS_SHST_OCCUR = 1 << 2,
174	197	NVME_CSTS_SHST_CMPLT = 2 << 2,
175	198	NVME_CSTS_SHST_MASK = 3 << 2,
	199	+ NVME_CMBMSC_CRE = 1 << 0,
	200	+ NVME_CMBMSC_CMSE = 1 << 1,
176	201	};
177	202
178	203	struct nvme_id_power_state {
..	..	@@ -198,6 +223,11 @@
198	223	NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
199	224	};
200	225
	226	+enum nvme_ctrl_attr {
	227	+ NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
	228	+ NVME_CTRL_ATTR_TBKAS = (1 << 6),
	229	+};
	230	+
201	231	struct nvme_id_ctrl {
202	232	__le16 vid;
203	233	__le16 ssvid;
..	..	@@ -214,7 +244,11 @@
214	244	__le32 rtd3e;
215	245	__le32 oaes;
216	246	__le32 ctratt;
217		- __u8 rsvd100[156];
	247	+ __u8 rsvd100[28];
	248	+ __le16 crdt1;
	249	+ __le16 crdt2;
	250	+ __le16 crdt3;
	251	+ __u8 rsvd134[122];
218	252	__le16 oacs;
219	253	__u8 acl;
220	254	__u8 aerl;
..	..	@@ -278,16 +312,27 @@
278	312	};
279	313
280	314	enum {
	315	+ NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
	316	+ NVME_CTRL_CMIC_ANA = 1 << 3,
281	317	NVME_CTRL_ONCS_COMPARE = 1 << 0,
282	318	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
283	319	NVME_CTRL_ONCS_DSM = 1 << 2,
284	320	NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
	321	+ NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
285	322	NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
286	323	NVME_CTRL_VWC_PRESENT = 1 << 0,
287	324	NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
288	325	NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
289	326	NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
290	327	NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
	328	+ NVME_CTRL_CTRATT_128_ID = 1 << 0,
	329	+ NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
	330	+ NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
	331	+ NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
	332	+ NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
	333	+ NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
	334	+ NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
	335	+ NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
291	336	};
292	337
293	338	struct nvme_lbaf {
..	..	@@ -309,7 +354,7 @@
309	354	__u8 nmic;
310	355	__u8 rescap;
311	356	__u8 fpi;
312		- __u8 rsvd33;
	357	+ __u8 dlfeat;
313	358	__le16 nawun;
314	359	__le16 nawupf;
315	360	__le16 nacwu;
..	..	@@ -318,11 +363,17 @@
318	363	__le16 nabspf;
319	364	__le16 noiob;
320	365	__u8 nvmcap[16];
321		- __u8 rsvd64[28];
	366	+ __le16 npwg;
	367	+ __le16 npwa;
	368	+ __le16 npdg;
	369	+ __le16 npda;
	370	+ __le16 nows;
	371	+ __u8 rsvd74[18];
322	372	__le32 anagrpid;
323	373	__u8 rsvd96[3];
324	374	__u8 nsattr;
325		- __u8 rsvd100[4];
	375	+ __le16 nvmsetid;
	376	+ __le16 endgid;
326	377	__u8 nguid[16];
327	378	__u8 eui64[8];
328	379	struct nvme_lbaf lbaf[16];
..	..	@@ -330,15 +381,49 @@
330	381	__u8 vs[3712];
331	382	};
332	383
	384	+struct nvme_zns_lbafe {
	385	+ __le64 zsze;
	386	+ __u8 zdes;
	387	+ __u8 rsvd9[7];
	388	+};
	389	+
	390	+struct nvme_id_ns_zns {
	391	+ __le16 zoc;
	392	+ __le16 ozcs;
	393	+ __le32 mar;
	394	+ __le32 mor;
	395	+ __le32 rrl;
	396	+ __le32 frl;
	397	+ __u8 rsvd20[2796];
	398	+ struct nvme_zns_lbafe lbafe[16];
	399	+ __u8 rsvd3072[768];
	400	+ __u8 vs[256];
	401	+};
	402	+
	403	+struct nvme_id_ctrl_zns {
	404	+ __u8 zasl;
	405	+ __u8 rsvd1[4095];
	406	+};
	407	+
333	408	enum {
334	409	NVME_ID_CNS_NS = 0x00,
335	410	NVME_ID_CNS_CTRL = 0x01,
336	411	NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
337	412	NVME_ID_CNS_NS_DESC_LIST = 0x03,
	413	+ NVME_ID_CNS_CS_NS = 0x05,
	414	+ NVME_ID_CNS_CS_CTRL = 0x06,
338	415	NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
339	416	NVME_ID_CNS_NS_PRESENT = 0x11,
340	417	NVME_ID_CNS_CTRL_NS_LIST = 0x12,
341	418	NVME_ID_CNS_CTRL_LIST = 0x13,
	419	+ NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
	420	+ NVME_ID_CNS_NS_GRANULARITY = 0x16,
	421	+ NVME_ID_CNS_UUID_LIST = 0x17,
	422	+};
	423	+
	424	+enum {
	425	+ NVME_CSI_NVM = 0,
	426	+ NVME_CSI_ZNS = 2,
342	427	};
343	428
344	429	enum {
..	..	@@ -356,8 +441,12 @@
356	441
357	442	enum {
358	443	NVME_NS_FEAT_THIN = 1 << 0,
	444	+ NVME_NS_FEAT_ATOMICS = 1 << 1,
	445	+ NVME_NS_FEAT_IO_OPT = 1 << 4,
	446	+ NVME_NS_ATTR_RO = 1 << 0,
359	447	NVME_NS_FLBAS_LBA_MASK = 0xf,
360	448	NVME_NS_FLBAS_META_EXT = 0x10,
	449	+ NVME_NS_NMIC_SHARED = 1 << 0,
361	450	NVME_LBAF_RP_BEST = 0,
362	451	NVME_LBAF_RP_BETTER = 1,
363	452	NVME_LBAF_RP_GOOD = 2,
..	..	@@ -374,6 +463,12 @@
374	463	NVME_NS_DPS_PI_TYPE3 = 3,
375	464	};
376	465
	466	+/* Identify Namespace Metadata Capabilities (MC): */
	467	+enum {
	468	+ NVME_MC_EXTENDED_LBA = (1 << 0),
	469	+ NVME_MC_METADATA_PTR = (1 << 1),
	470	+};
	471	+
377	472	struct nvme_ns_id_desc {
378	473	__u8 nidt;
379	474	__u8 nidl;
..	..	@@ -383,11 +478,13 @@
383	478	#define NVME_NIDT_EUI64_LEN 8
384	479	#define NVME_NIDT_NGUID_LEN 16
385	480	#define NVME_NIDT_UUID_LEN 16
	481	+#define NVME_NIDT_CSI_LEN 1
386	482
387	483	enum {
388	484	NVME_NIDT_EUI64 = 0x01,
389	485	NVME_NIDT_NGUID = 0x02,
390	486	NVME_NIDT_UUID = 0x03,
	487	+ NVME_NIDT_CSI = 0x04,
391	488	};
392	489
393	490	struct nvme_smart_log {
..	..	@@ -396,7 +493,8 @@
396	493	__u8 avail_spare;
397	494	__u8 spare_thresh;
398	495	__u8 percent_used;
399		- __u8 rsvd6[26];
	496	+ __u8 endu_grp_crit_warn_sumry;
	497	+ __u8 rsvd7[25];
400	498	__u8 data_units_read[16];
401	499	__u8 data_units_written[16];
402	500	__u8 host_reads[16];
..	..	@@ -410,7 +508,11 @@
410	508	__le32 warning_temp_time;
411	509	__le32 critical_comp_time;
412	510	__le16 temp_sensor[8];
413		- __u8 rsvd216[296];
	511	+ __le32 thm_temp1_trans_count;
	512	+ __le32 thm_temp2_trans_count;
	513	+ __le32 thm_temp1_total_time;
	514	+ __le32 thm_temp2_total_time;
	515	+ __u8 rsvd232[280];
414	516	};
415	517
416	518	struct nvme_fw_slot_info_log {
..	..	@@ -427,6 +529,7 @@
427	529	NVME_CMD_EFFECTS_NIC = 1 << 3,
428	530	NVME_CMD_EFFECTS_CCC = 1 << 4,
429	531	NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
	532	+ NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
430	533	};
431	534
432	535	struct nvme_effects_log {
..	..	@@ -461,6 +564,27 @@
461	564	__le16 rsvd10[3];
462	565	};
463	566
	567	+struct nvme_zone_descriptor {
	568	+ __u8 zt;
	569	+ __u8 zs;
	570	+ __u8 za;
	571	+ __u8 rsvd3[5];
	572	+ __le64 zcap;
	573	+ __le64 zslba;
	574	+ __le64 wp;
	575	+ __u8 rsvd32[32];
	576	+};
	577	+
	578	+enum {
	579	+ NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
	580	+};
	581	+
	582	+struct nvme_zone_report {
	583	+ __le64 nr_zones;
	584	+ __u8 resv8[56];
	585	+ struct nvme_zone_descriptor entries[];
	586	+};
	587	+
464	588	enum {
465	589	NVME_SMART_CRIT_SPARE = 1 << 0,
466	590	NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
..	..	@@ -481,12 +605,21 @@
481	605	NVME_AER_NOTICE_NS_CHANGED = 0x00,
482	606	NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
483	607	NVME_AER_NOTICE_ANA = 0x03,
	608	+ NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
484	609	};
485	610
486	611	enum {
487		- NVME_AEN_CFG_NS_ATTR = 1 << 8,
488		- NVME_AEN_CFG_FW_ACT = 1 << 9,
489		- NVME_AEN_CFG_ANA_CHANGE = 1 << 11,
	612	+ NVME_AEN_BIT_NS_ATTR = 8,
	613	+ NVME_AEN_BIT_FW_ACT = 9,
	614	+ NVME_AEN_BIT_ANA_CHANGE = 11,
	615	+ NVME_AEN_BIT_DISC_CHANGE = 31,
	616	+};
	617	+
	618	+enum {
	619	+ NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
	620	+ NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
	621	+ NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
	622	+ NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
490	623	};
491	624
492	625	struct nvme_lba_range_type {
..	..	@@ -541,11 +674,31 @@
541	674	nvme_cmd_compare = 0x05,
542	675	nvme_cmd_write_zeroes = 0x08,
543	676	nvme_cmd_dsm = 0x09,
	677	+ nvme_cmd_verify = 0x0c,
544	678	nvme_cmd_resv_register = 0x0d,
545	679	nvme_cmd_resv_report = 0x0e,
546	680	nvme_cmd_resv_acquire = 0x11,
547	681	nvme_cmd_resv_release = 0x15,
	682	+ nvme_cmd_zone_mgmt_send = 0x79,
	683	+ nvme_cmd_zone_mgmt_recv = 0x7a,
	684	+ nvme_cmd_zone_append = 0x7d,
548	685	};
	686	+
	687	+#define nvme_opcode_name(opcode) { opcode, #opcode }
	688	+#define show_nvm_opcode_name(val) \
	689	+ __print_symbolic(val, \
	690	+ nvme_opcode_name(nvme_cmd_flush), \
	691	+ nvme_opcode_name(nvme_cmd_write), \
	692	+ nvme_opcode_name(nvme_cmd_read), \
	693	+ nvme_opcode_name(nvme_cmd_write_uncor), \
	694	+ nvme_opcode_name(nvme_cmd_compare), \
	695	+ nvme_opcode_name(nvme_cmd_write_zeroes), \
	696	+ nvme_opcode_name(nvme_cmd_dsm), \
	697	+ nvme_opcode_name(nvme_cmd_resv_register), \
	698	+ nvme_opcode_name(nvme_cmd_resv_report), \
	699	+ nvme_opcode_name(nvme_cmd_resv_acquire), \
	700	+ nvme_opcode_name(nvme_cmd_resv_release))
	701	+
549	702
550	703	/*
551	704	* Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
..	..	@@ -639,7 +792,12 @@
639	792	__le32 cdw2[2];
640	793	__le64 metadata;
641	794	union nvme_data_ptr dptr;
642		- __le32 cdw10[6];
	795	+ __le32 cdw10;
	796	+ __le32 cdw11;
	797	+ __le32 cdw12;
	798	+ __le32 cdw13;
	799	+ __le32 cdw14;
	800	+ __le32 cdw15;
643	801	};
644	802
645	803	struct nvme_rw_command {
..	..	@@ -662,6 +820,7 @@
662	820	enum {
663	821	NVME_RW_LR = 1 << 15,
664	822	NVME_RW_FUA = 1 << 14,
	823	+ NVME_RW_APPEND_PIREMAP = 1 << 9,
665	824	NVME_RW_DSM_FREQ_UNSPEC = 0,
666	825	NVME_RW_DSM_FREQ_TYPICAL = 1,
667	826	NVME_RW_DSM_FREQ_RARE = 2,
..	..	@@ -727,7 +886,60 @@
727	886	__le16 appmask;
728	887	};
729	888
	889	+enum nvme_zone_mgmt_action {
	890	+ NVME_ZONE_CLOSE = 0x1,
	891	+ NVME_ZONE_FINISH = 0x2,
	892	+ NVME_ZONE_OPEN = 0x3,
	893	+ NVME_ZONE_RESET = 0x4,
	894	+ NVME_ZONE_OFFLINE = 0x5,
	895	+ NVME_ZONE_SET_DESC_EXT = 0x10,
	896	+};
	897	+
	898	+struct nvme_zone_mgmt_send_cmd {
	899	+ __u8 opcode;
	900	+ __u8 flags;
	901	+ __u16 command_id;
	902	+ __le32 nsid;
	903	+ __le32 cdw2[2];
	904	+ __le64 metadata;
	905	+ union nvme_data_ptr dptr;
	906	+ __le64 slba;
	907	+ __le32 cdw12;
	908	+ __u8 zsa;
	909	+ __u8 select_all;
	910	+ __u8 rsvd13[2];
	911	+ __le32 cdw14[2];
	912	+};
	913	+
	914	+struct nvme_zone_mgmt_recv_cmd {
	915	+ __u8 opcode;
	916	+ __u8 flags;
	917	+ __u16 command_id;
	918	+ __le32 nsid;
	919	+ __le64 rsvd2[2];
	920	+ union nvme_data_ptr dptr;
	921	+ __le64 slba;
	922	+ __le32 numd;
	923	+ __u8 zra;
	924	+ __u8 zrasf;
	925	+ __u8 pr;
	926	+ __u8 rsvd13;
	927	+ __le32 cdw14[2];
	928	+};
	929	+
	930	+enum {
	931	+ NVME_ZRA_ZONE_REPORT = 0,
	932	+ NVME_ZRASF_ZONE_REPORT_ALL = 0,
	933	+ NVME_REPORT_ZONE_PARTIAL = 1,
	934	+};
	935	+
730	936	/* Features */
	937	+
	938	+enum {
	939	+ NVME_TEMP_THRESH_MASK = 0xffff,
	940	+ NVME_TEMP_THRESH_SELECT_SHIFT = 16,
	941	+ NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
	942	+};
731	943
732	944	struct nvme_feat_auto_pst {
733	945	__le64 entries[32];
..	..	@@ -736,6 +948,15 @@
736	948	enum {
737	949	NVME_HOST_MEM_ENABLE = (1 << 0),
738	950	NVME_HOST_MEM_RETURN = (1 << 1),
	951	+};
	952	+
	953	+struct nvme_feat_host_behavior {
	954	+ __u8 acre;
	955	+ __u8 resv1[511];
	956	+};
	957	+
	958	+enum {
	959	+ NVME_ENABLE_ACRE = 1,
739	960	};
740	961
741	962	/* Admin commands */
..	..	@@ -754,16 +975,49 @@
754	975	nvme_admin_ns_mgmt = 0x0d,
755	976	nvme_admin_activate_fw = 0x10,
756	977	nvme_admin_download_fw = 0x11,
	978	+ nvme_admin_dev_self_test = 0x14,
757	979	nvme_admin_ns_attach = 0x15,
758	980	nvme_admin_keep_alive = 0x18,
759	981	nvme_admin_directive_send = 0x19,
760	982	nvme_admin_directive_recv = 0x1a,
	983	+ nvme_admin_virtual_mgmt = 0x1c,
	984	+ nvme_admin_nvme_mi_send = 0x1d,
	985	+ nvme_admin_nvme_mi_recv = 0x1e,
761	986	nvme_admin_dbbuf = 0x7C,
762	987	nvme_admin_format_nvm = 0x80,
763	988	nvme_admin_security_send = 0x81,
764	989	nvme_admin_security_recv = 0x82,
765	990	nvme_admin_sanitize_nvm = 0x84,
	991	+ nvme_admin_get_lba_status = 0x86,
	992	+ nvme_admin_vendor_start = 0xC0,
766	993	};
	994	+
	995	+#define nvme_admin_opcode_name(opcode) { opcode, #opcode }
	996	+#define show_admin_opcode_name(val) \
	997	+ __print_symbolic(val, \
	998	+ nvme_admin_opcode_name(nvme_admin_delete_sq), \
	999	+ nvme_admin_opcode_name(nvme_admin_create_sq), \
	1000	+ nvme_admin_opcode_name(nvme_admin_get_log_page), \
	1001	+ nvme_admin_opcode_name(nvme_admin_delete_cq), \
	1002	+ nvme_admin_opcode_name(nvme_admin_create_cq), \
	1003	+ nvme_admin_opcode_name(nvme_admin_identify), \
	1004	+ nvme_admin_opcode_name(nvme_admin_abort_cmd), \
	1005	+ nvme_admin_opcode_name(nvme_admin_set_features), \
	1006	+ nvme_admin_opcode_name(nvme_admin_get_features), \
	1007	+ nvme_admin_opcode_name(nvme_admin_async_event), \
	1008	+ nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
	1009	+ nvme_admin_opcode_name(nvme_admin_activate_fw), \
	1010	+ nvme_admin_opcode_name(nvme_admin_download_fw), \
	1011	+ nvme_admin_opcode_name(nvme_admin_ns_attach), \
	1012	+ nvme_admin_opcode_name(nvme_admin_keep_alive), \
	1013	+ nvme_admin_opcode_name(nvme_admin_directive_send), \
	1014	+ nvme_admin_opcode_name(nvme_admin_directive_recv), \
	1015	+ nvme_admin_opcode_name(nvme_admin_dbbuf), \
	1016	+ nvme_admin_opcode_name(nvme_admin_format_nvm), \
	1017	+ nvme_admin_opcode_name(nvme_admin_security_send), \
	1018	+ nvme_admin_opcode_name(nvme_admin_security_recv), \
	1019	+ nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
	1020	+ nvme_admin_opcode_name(nvme_admin_get_lba_status))
767	1021
768	1022	enum {
769	1023	NVME_QUEUE_PHYS_CONTIG = (1 << 0),
..	..	@@ -792,16 +1046,24 @@
792	1046	NVME_FEAT_RRL = 0x12,
793	1047	NVME_FEAT_PLM_CONFIG = 0x13,
794	1048	NVME_FEAT_PLM_WINDOW = 0x14,
	1049	+ NVME_FEAT_HOST_BEHAVIOR = 0x16,
	1050	+ NVME_FEAT_SANITIZE = 0x17,
795	1051	NVME_FEAT_SW_PROGRESS = 0x80,
796	1052	NVME_FEAT_HOST_ID = 0x81,
797	1053	NVME_FEAT_RESV_MASK = 0x82,
798	1054	NVME_FEAT_RESV_PERSIST = 0x83,
799	1055	NVME_FEAT_WRITE_PROTECT = 0x84,
	1056	+ NVME_FEAT_VENDOR_START = 0xC0,
	1057	+ NVME_FEAT_VENDOR_END = 0xFF,
800	1058	NVME_LOG_ERROR = 0x01,
801	1059	NVME_LOG_SMART = 0x02,
802	1060	NVME_LOG_FW_SLOT = 0x03,
803	1061	NVME_LOG_CHANGED_NS = 0x04,
804	1062	NVME_LOG_CMD_EFFECTS = 0x05,
	1063	+ NVME_LOG_DEVICE_SELF_TEST = 0x06,
	1064	+ NVME_LOG_TELEMETRY_HOST = 0x07,
	1065	+ NVME_LOG_TELEMETRY_CTRL = 0x08,
	1066	+ NVME_LOG_ENDURANCE_GROUP = 0x09,
805	1067	NVME_LOG_ANA = 0x0c,
806	1068	NVME_LOG_DISC = 0x70,
807	1069	NVME_LOG_RESERVATION = 0x80,
..	..	@@ -830,7 +1092,9 @@
830	1092	__u8 cns;
831	1093	__u8 rsvd3;
832	1094	__le16 ctrlid;
833		- __u32 rsvd11[5];
	1095	+ __u8 rsvd11[3];
	1096	+ __u8 csi;
	1097	+ __u32 rsvd12[4];
834	1098	};
835	1099
836	1100	#define NVME_IDENTIFY_DATA_SIZE 4096
..	..	@@ -937,9 +1201,16 @@
937	1201	__le16 numdl;
938	1202	__le16 numdu;
939	1203	__u16 rsvd11;
940		- __le32 lpol;
941		- __le32 lpou;
942		- __u32 rsvd14[2];
	1204	+ union {
	1205	+ struct {
	1206	+ __le32 lpol;
	1207	+ __le32 lpou;
	1208	+ };
	1209	+ __le64 lpo;
	1210	+ };
	1211	+ __u8 rsvd14[3];
	1212	+ __u8 csi;
	1213	+ __u32 rsvd15;
943	1214	};
944	1215
945	1216	struct nvme_directive_cmd {
..	..	@@ -972,6 +1243,23 @@
972	1243	nvme_fabrics_type_connect = 0x01,
973	1244	nvme_fabrics_type_property_get = 0x04,
974	1245	};
	1246	+
	1247	+#define nvme_fabrics_type_name(type) { type, #type }
	1248	+#define show_fabrics_type_name(type) \
	1249	+ __print_symbolic(type, \
	1250	+ nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
	1251	+ nvme_fabrics_type_name(nvme_fabrics_type_connect), \
	1252	+ nvme_fabrics_type_name(nvme_fabrics_type_property_get))
	1253	+
	1254	+/*
	1255	+ * If not fabrics command, fctype will be ignored.
	1256	+ */
	1257	+#define show_opcode_name(qid, opcode, fctype) \
	1258	+ ((opcode) == nvme_fabrics_command ? \
	1259	+ show_fabrics_type_name(fctype) : \
	1260	+ ((qid) ? \
	1261	+ show_nvm_opcode_name(opcode) : \
	1262	+ show_admin_opcode_name(opcode)))
975	1263
976	1264	struct nvmf_common_command {
977	1265	__u8 opcode;
..	..	@@ -1027,7 +1315,11 @@
1027	1315	__le64 numrec;
1028	1316	__le16 recfmt;
1029	1317	__u8 resv14[1006];
1030		- struct nvmf_disc_rsp_page_entry entries[0];
	1318	+ struct nvmf_disc_rsp_page_entry entries[];
	1319	+};
	1320	+
	1321	+enum {
	1322	+ NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1031	1323	};
1032	1324
1033	1325	struct nvmf_connect_command {
..	..	@@ -1115,6 +1407,8 @@
1115	1407	struct nvme_format_cmd format;
1116	1408	struct nvme_dsm_cmd dsm;
1117	1409	struct nvme_write_zeroes_cmd write_zeroes;
	1410	+ struct nvme_zone_mgmt_send_cmd zms;
	1411	+ struct nvme_zone_mgmt_recv_cmd zmr;
1118	1412	struct nvme_abort_cmd abort;
1119	1413	struct nvme_get_log_page_command get_log_page;
1120	1414	struct nvmf_common_command fabrics;
..	..	@@ -1126,6 +1420,25 @@
1126	1420	};
1127	1421	};
1128	1422
	1423	+static inline bool nvme_is_fabrics(struct nvme_command *cmd)
	1424	+{
	1425	+ return cmd->common.opcode == nvme_fabrics_command;
	1426	+}
	1427	+
	1428	+struct nvme_error_slot {
	1429	+ __le64 error_count;
	1430	+ __le16 sqid;
	1431	+ __le16 cmdid;
	1432	+ __le16 status_field;
	1433	+ __le16 param_error_location;
	1434	+ __le64 lba;
	1435	+ __le32 nsid;
	1436	+ __u8 vs;
	1437	+ __u8 resv[3];
	1438	+ __le64 cs;
	1439	+ __u8 resv2[24];
	1440	+};
	1441	+
1129	1442	static inline bool nvme_is_write(struct nvme_command *cmd)
1130	1443	{
1131	1444	/*
..	..	@@ -1133,7 +1446,7 @@
1133	1446	*
1134	1447	* Why can't we simply have a Fabrics In and Fabrics out command?
1135	1448	*/
1136		- if (unlikely(cmd->common.opcode == nvme_fabrics_command))
	1449	+ if (unlikely(nvme_is_fabrics(cmd)))
1137	1450	return cmd->fabrics.fctype & 1;
1138	1451	return cmd->common.opcode & 1;
1139	1452	}
..	..	@@ -1164,7 +1477,11 @@
1164	1477	NVME_SC_SGL_INVALID_OFFSET = 0x16,
1165	1478	NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1166	1479
	1480	+ NVME_SC_SANITIZE_FAILED = 0x1C,
	1481	+ NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
	1482	+
1167	1483	NVME_SC_NS_WRITE_PROTECTED = 0x20,
	1484	+ NVME_SC_CMD_INTERRUPTED = 0x21,
1168	1485
1169	1486	NVME_SC_LBA_RANGE = 0x80,
1170	1487	NVME_SC_CAP_EXCEEDED = 0x81,
..	..	@@ -1193,15 +1510,17 @@
1193	1510	NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1194	1511	NVME_SC_FW_NEEDS_RESET = 0x111,
1195	1512	NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1196		- NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
	1513	+ NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1197	1514	NVME_SC_OVERLAPPING_RANGE = 0x114,
1198		- NVME_SC_NS_INSUFFICENT_CAP = 0x115,
	1515	+ NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1199	1516	NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1200	1517	NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1201	1518	NVME_SC_NS_IS_PRIVATE = 0x119,
1202	1519	NVME_SC_NS_NOT_ATTACHED = 0x11a,
1203	1520	NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1204	1521	NVME_SC_CTRL_LIST_INVALID = 0x11c,
	1522	+ NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
	1523	+ NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1205	1524
1206	1525	/*
1207	1526	* I/O Command Set Specific - NVM commands:
..	..	@@ -1224,6 +1543,18 @@
1224	1543	NVME_SC_AUTH_REQUIRED = 0x191,
1225	1544
1226	1545	/*
	1546	+ * I/O Command Set Specific - Zoned commands:
	1547	+ */
	1548	+ NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
	1549	+ NVME_SC_ZONE_FULL = 0x1b9,
	1550	+ NVME_SC_ZONE_READ_ONLY = 0x1ba,
	1551	+ NVME_SC_ZONE_OFFLINE = 0x1bb,
	1552	+ NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
	1553	+ NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
	1554	+ NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
	1555	+ NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
	1556	+
	1557	+ /*
1227	1558	* Media and Data Integrity Errors:
1228	1559	*/
1229	1560	NVME_SC_WRITE_FAULT = 0x280,
..	..	@@ -1242,7 +1573,9 @@
1242	1573	NVME_SC_ANA_INACCESSIBLE = 0x302,
1243	1574	NVME_SC_ANA_TRANSITION = 0x303,
1244	1575	NVME_SC_HOST_PATH_ERROR = 0x370,
	1576	+ NVME_SC_HOST_ABORTED_CMD = 0x371,
1245	1577
	1578	+ NVME_SC_CRD = 0x1800,
1246	1579	NVME_SC_DNR = 0x4000,
1247	1580	};
1248	1581