.. | .. |
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2 | 2 | #ifndef _DT_BINDINGS_SAMSUNG_I2S_H |
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3 | 3 | #define _DT_BINDINGS_SAMSUNG_I2S_H |
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4 | 4 | |
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5 | | -#define CLK_I2S_CDCLK 0 |
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6 | | -#define CLK_I2S_RCLK_SRC 1 |
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7 | | -#define CLK_I2S_RCLK_PSR 2 |
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| 5 | +#define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ |
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| 6 | + |
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| 7 | +#define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to |
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| 8 | + * RCLKSRC bit in IISMOD register) |
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| 9 | + */ |
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| 10 | + |
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| 11 | +#define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock |
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| 12 | + * (corresponding to the IISPSR register) |
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| 13 | + */ |
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8 | 14 | |
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9 | 15 | #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ |
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