add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/include/dt-bindings/clock/qcom,gcc-msm8998.h
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@@ -1,14 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
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@@ -180,6 +172,18 @@
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 #define USB30_MASTER_CLK_SRC					163
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 #define USB30_MOCK_UTMI_CLK_SRC					164
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 #define USB3_PHY_AUX_CLK_SRC					165
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+#define GCC_USB3_CLKREF_CLK					166
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+#define GCC_HDMI_CLKREF_CLK					167
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+#define GCC_UFS_CLKREF_CLK					168
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+#define GCC_PCIE_CLKREF_CLK					169
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+#define GCC_RX1_USB2_CLKREF_CLK					170
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+#define GCC_MSS_CFG_AHB_CLK					171
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+#define GCC_BOOT_ROM_AHB_CLK					172
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+#define GCC_MSS_GPLL0_DIV_CLK_SRC				173
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+#define GCC_MSS_SNOC_AXI_CLK					174
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+#define GCC_MSS_MNOC_BIMC_AXI_CLK				175
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+#define GCC_BIMC_GFX_CLK					176
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+#define UFS_UNIPRO_CORE_CLK_SRC					177
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 #define PCIE_0_GDSC						0
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 #define UFS_GDSC						1
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@@ -204,5 +208,95 @@
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 #define GCC_TSIF_BCR						16
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 #define GCC_UFS_BCR						17
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 #define GCC_USB_30_BCR						18
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+#define GCC_SYSTEM_NOC_BCR					19
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+#define GCC_CONFIG_NOC_BCR					20
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+#define GCC_AHB2PHY_EAST_BCR					21
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+#define GCC_IMEM_BCR						22
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+#define GCC_PIMEM_BCR						23
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+#define GCC_MMSS_BCR						24
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+#define GCC_QDSS_BCR						25
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+#define GCC_WCSS_BCR						26
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+#define GCC_BLSP1_BCR						27
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+#define GCC_BLSP1_UART1_BCR					28
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+#define GCC_BLSP1_UART2_BCR					29
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+#define GCC_BLSP1_UART3_BCR					30
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+#define GCC_CM_PHY_REFGEN1_BCR					31
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+#define GCC_CM_PHY_REFGEN2_BCR					32
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+#define GCC_BLSP2_BCR						33
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+#define GCC_BLSP2_UART1_BCR					34
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+#define GCC_BLSP2_UART2_BCR					35
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+#define GCC_BLSP2_UART3_BCR					36
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+#define GCC_SRAM_SENSOR_BCR					37
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+#define GCC_PRNG_BCR						38
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+#define GCC_TSIF_0_RESET					39
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+#define GCC_TSIF_1_RESET					40
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+#define GCC_TCSR_BCR						41
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+#define GCC_BOOT_ROM_BCR					42
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+#define GCC_MSG_RAM_BCR						43
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+#define GCC_TLMM_BCR						44
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+#define GCC_MPM_BCR						45
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+#define GCC_SEC_CTRL_BCR					46
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+#define GCC_SPMI_BCR						47
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+#define GCC_SPDM_BCR						48
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+#define GCC_CE1_BCR						49
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+#define GCC_BIMC_BCR						50
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+#define GCC_SNOC_BUS_TIMEOUT0_BCR				51
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+#define GCC_SNOC_BUS_TIMEOUT1_BCR				52
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+#define GCC_SNOC_BUS_TIMEOUT3_BCR				53
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+#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				54
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+#define GCC_PNOC_BUS_TIMEOUT0_BCR				55
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+#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR			56
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+#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR			57
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+#define GCC_CNOC_BUS_TIMEOUT0_BCR				58
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+#define GCC_CNOC_BUS_TIMEOUT1_BCR				59
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+#define GCC_CNOC_BUS_TIMEOUT2_BCR				60
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+#define GCC_CNOC_BUS_TIMEOUT3_BCR				61
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+#define GCC_CNOC_BUS_TIMEOUT4_BCR				62
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+#define GCC_CNOC_BUS_TIMEOUT5_BCR				63
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+#define GCC_CNOC_BUS_TIMEOUT6_BCR				64
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+#define GCC_CNOC_BUS_TIMEOUT7_BCR				65
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+#define GCC_APB2JTAG_BCR					66
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+#define GCC_RBCPR_CX_BCR					67
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+#define GCC_RBCPR_MX_BCR					68
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+#define GCC_USB3_PHY_BCR					69
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+#define GCC_USB3PHY_PHY_BCR					70
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+#define GCC_USB3_DP_PHY_BCR					71
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+#define GCC_SSC_BCR						72
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+#define GCC_SSC_RESET						73
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+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				74
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+#define GCC_PCIE_0_LINK_DOWN_BCR				75
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+#define GCC_PCIE_0_PHY_BCR					76
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+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				77
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+#define GCC_PCIE_PHY_BCR					78
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+#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				79
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+#define GCC_PCIE_PHY_CFG_AHB_BCR				80
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+#define GCC_PCIE_PHY_COM_BCR					81
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+#define GCC_GPU_BCR						82
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+#define GCC_SPSS_BCR						83
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+#define GCC_OBT_ODT_BCR						84
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+#define GCC_VS_BCR						85
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+#define GCC_MSS_VS_RESET					86
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+#define GCC_GPU_VS_RESET					87
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+#define GCC_APC0_VS_RESET					88
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+#define GCC_APC1_VS_RESET					89
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+#define GCC_CNOC_BUS_TIMEOUT8_BCR				90
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+#define GCC_CNOC_BUS_TIMEOUT9_BCR				91
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+#define GCC_CNOC_BUS_TIMEOUT10_BCR				92
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+#define GCC_CNOC_BUS_TIMEOUT11_BCR				93
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+#define GCC_CNOC_BUS_TIMEOUT12_BCR				94
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+#define GCC_CNOC_BUS_TIMEOUT13_BCR				95
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+#define GCC_CNOC_BUS_TIMEOUT14_BCR				96
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+#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				97
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+#define GCC_AGGRE1_NOC_BCR					98
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+#define GCC_AGGRE2_NOC_BCR					99
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+#define GCC_DCC_BCR						100
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+#define GCC_QREFS_VBG_CAL_BCR					101
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+#define GCC_IPA_BCR						102
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+#define GCC_GLM_BCR						103
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+#define GCC_SKL_BCR						104
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+#define GCC_MSMPU_BCR						105
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+#define GCC_QUSB2PHY_PRIM_BCR					106
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+#define GCC_QUSB2PHY_SEC_BCR					107
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+#define GCC_MSS_RESTART						108
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 #endif