add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/usb/mtu3/mtu3_hw_regs.h
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@@ -1,4 +1,4 @@
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-// SPDX-License-Identifier: GPL-2.0
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
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  *
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@@ -49,6 +49,7 @@
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 #define U3D_QCR1		(SSUSB_DEV_BASE + 0x0404)
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 #define U3D_QCR2		(SSUSB_DEV_BASE + 0x0408)
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 #define U3D_QCR3		(SSUSB_DEV_BASE + 0x040C)
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+#define U3D_QFCR		(SSUSB_DEV_BASE + 0x0428)
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 #define U3D_TXQHIAR1		(SSUSB_DEV_BASE + 0x0484)
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 #define U3D_RXQHIAR1		(SSUSB_DEV_BASE + 0x04C4)
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@@ -104,6 +105,7 @@
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 /* U3D_EPISR */
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 #define EPRISR(x)		(BIT(16) << (x))
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+#define SETUPENDISR		BIT(16)
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 #define EPTISR(x)		(BIT(0) << (x))
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 #define EP0ISR			BIT(0)
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@@ -132,11 +134,23 @@
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 #define TX_W1C_BITS		(~(TX_SENTSTALL))
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 /* U3D_TX1CSR1 */
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-#define TX_MULT(x)		(((x) & 0x3) << 22)
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-#define TX_MAX_PKT(x)		(((x) & 0x3f) << 16)
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+#define TX_MAX_PKT_G2(x)	(((x) & 0xff) << 24)
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+#define TX_MULT_G2(x)		(((x) & 0x7) << 21)
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+#define TX_MULT_OG(x)		(((x) & 0x3) << 22)
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+#define TX_MAX_PKT_OG(x)	(((x) & 0x3f) << 16)
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 #define TX_SLOT(x)		(((x) & 0x3f) << 8)
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 #define TX_TYPE(x)		(((x) & 0x3) << 4)
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 #define TX_SS_BURST(x)		(((x) & 0xf) << 0)
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+#define TX_MULT(g2c, x)		\
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+({				\
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+	typeof(x) x_ = (x);	\
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+	(g2c) ? TX_MULT_G2(x_) : TX_MULT_OG(x_);	\
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+})
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+#define TX_MAX_PKT(g2c, x)	\
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+({				\
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+	typeof(x) x_ = (x);	\
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+	(g2c) ? TX_MAX_PKT_G2(x_) : TX_MAX_PKT_OG(x_);	\
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+})
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 /* for TX_TYPE & RX_TYPE */
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 #define TYPE_BULK		(0x0)
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@@ -159,11 +173,23 @@
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 #define RX_W1C_BITS		(~(RX_SENTSTALL | RX_RXPKTRDY))
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 /* U3D_RX1CSR1 */
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-#define RX_MULT(x)		(((x) & 0x3) << 22)
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-#define RX_MAX_PKT(x)		(((x) & 0x3f) << 16)
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+#define RX_MAX_PKT_G2(x)	(((x) & 0xff) << 24)
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+#define RX_MULT_G2(x)		(((x) & 0x7) << 21)
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+#define RX_MULT_OG(x)		(((x) & 0x3) << 22)
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+#define RX_MAX_PKT_OG(x)	(((x) & 0x3f) << 16)
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 #define RX_SLOT(x)		(((x) & 0x3f) << 8)
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 #define RX_TYPE(x)		(((x) & 0x3) << 4)
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 #define RX_SS_BURST(x)		(((x) & 0xf) << 0)
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+#define RX_MULT(g2c, x)		\
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+({				\
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+	typeof(x) x_ = (x);	\
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+	(g2c) ? RX_MULT_G2(x_) : RX_MULT_OG(x_);	\
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+})
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+#define RX_MAX_PKT(g2c, x)	\
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+({				\
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+	typeof(x) x_ = (x);	\
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+	(g2c) ? RX_MAX_PKT_G2(x_) : RX_MAX_PKT_OG(x_);	\
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+})
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 /* U3D_RX1CSR2 */
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 #define RX_BINTERVAL(x)		(((x) & 0xff) << 24)
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@@ -264,8 +290,11 @@
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 #define U3D_LTSSM_CTRL		(SSUSB_USB3_MAC_CSR_BASE + 0x0010)
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 #define U3D_USB3_CONFIG		(SSUSB_USB3_MAC_CSR_BASE + 0x001C)
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+#define U3D_LINK_STATE_MACHINE	(SSUSB_USB3_MAC_CSR_BASE + 0x0134)
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 #define U3D_LTSSM_INTR_ENABLE	(SSUSB_USB3_MAC_CSR_BASE + 0x013C)
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 #define U3D_LTSSM_INTR		(SSUSB_USB3_MAC_CSR_BASE + 0x0140)
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+
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+#define U3D_U3U2_SWITCH_CTRL	(SSUSB_USB3_MAC_CSR_BASE + 0x0170)
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 /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
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@@ -278,6 +307,9 @@
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 /* U3D_USB3_CONFIG */
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 #define USB3_EN			BIT(0)
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+
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+/* U3D_LINK_STATE_MACHINE */
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+#define LTSSM_STATE(x)	((x) & 0x1f)
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 /* U3D_LTSSM_INTR_ENABLE */
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 /* U3D_LTSSM_INTR */
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@@ -300,6 +332,9 @@
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 #define COMPLIANCE_INTR		BIT(2)
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 #define SS_DISABLE_INTR		BIT(1)
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 #define SS_INACTIVE_INTR	BIT(0)
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+
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+/* U3D_U3U2_SWITCH_CTRL */
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+#define SOFTCON_CLR_AUTO_EN	BIT(0)
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 /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
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@@ -341,6 +376,7 @@
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 #define U3D_USB20_FRAME_NUM		(SSUSB_USB2_CSR_BASE + 0x003C)
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 #define U3D_USB20_LPM_PARAMETER		(SSUSB_USB2_CSR_BASE + 0x0044)
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 #define U3D_USB20_MISC_CONTROL		(SSUSB_USB2_CSR_BASE + 0x004C)
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+#define U3D_USB20_OPSTATE		(SSUSB_USB2_CSR_BASE + 0x0060)
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 /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/
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@@ -413,6 +449,13 @@
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 #define U3D_SSUSB_DEV_RST_CTRL	(SSUSB_SIFSLV_IPPC_BASE + 0x0098)
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 #define U3D_SSUSB_HW_ID		(SSUSB_SIFSLV_IPPC_BASE + 0x00A0)
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 #define U3D_SSUSB_HW_SUB_ID	(SSUSB_SIFSLV_IPPC_BASE + 0x00A4)
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+#define U3D_SSUSB_IP_TRUNK_VERS	(U3D_SSUSB_HW_SUB_ID)
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+#define U3D_SSUSB_PRB_CTRL0	(SSUSB_SIFSLV_IPPC_BASE + 0x00B0)
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+#define U3D_SSUSB_PRB_CTRL1	(SSUSB_SIFSLV_IPPC_BASE + 0x00B4)
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+#define U3D_SSUSB_PRB_CTRL2	(SSUSB_SIFSLV_IPPC_BASE + 0x00B8)
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+#define U3D_SSUSB_PRB_CTRL3	(SSUSB_SIFSLV_IPPC_BASE + 0x00BC)
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+#define U3D_SSUSB_PRB_CTRL4	(SSUSB_SIFSLV_IPPC_BASE + 0x00C0)
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+#define U3D_SSUSB_PRB_CTRL5	(SSUSB_SIFSLV_IPPC_BASE + 0x00C4)
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 #define U3D_SSUSB_IP_SPARE0	(SSUSB_SIFSLV_IPPC_BASE + 0x00C8)
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 /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/
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@@ -477,4 +520,7 @@
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 /* U3D_SSUSB_DEV_RST_CTRL */
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 #define SSUSB_DEV_SW_RST		BIT(0)
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+/* U3D_SSUSB_IP_TRUNK_VERS */
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+#define IP_TRUNK_VERS(x)		(((x) >> 16) & 0xffff)
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+
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 #endif	/* _SSUSB_HW_REGS_H_ */