~hc/RK356X_SDK_RELEASE.git

..	..	@@ -24,6 +24,7 @@
24	24	#include <linux/moduleparam.h>
25	25	#include <linux/dma-mapping.h>
26	26	#include <linux/io.h>
	27	+#include <linux/iopoll.h>
27	28
28	29	#include <asm/irq.h>
29	30	#include <asm/unaligned.h>
..	..	@@ -31,9 +32,448 @@
31	32	#include <linux/irq.h>
32	33	#include <linux/platform_device.h>
33	34
34		-#include "oxu210hp.h"
35		-
36	35	#define DRIVER_VERSION "0.0.50"
	36	+
	37	+#define OXU_DEVICEID 0x00
	38	+ #define OXU_REV_MASK 0xffff0000
	39	+ #define OXU_REV_SHIFT 16
	40	+ #define OXU_REV_2100 0x2100
	41	+ #define OXU_BO_SHIFT 8
	42	+ #define OXU_BO_MASK (0x3 << OXU_BO_SHIFT)
	43	+ #define OXU_MAJ_REV_SHIFT 4
	44	+ #define OXU_MAJ_REV_MASK (0xf << OXU_MAJ_REV_SHIFT)
	45	+ #define OXU_MIN_REV_SHIFT 0
	46	+ #define OXU_MIN_REV_MASK (0xf << OXU_MIN_REV_SHIFT)
	47	+#define OXU_HOSTIFCONFIG 0x04
	48	+#define OXU_SOFTRESET 0x08
	49	+ #define OXU_SRESET (1 << 0)
	50	+
	51	+#define OXU_PIOBURSTREADCTRL 0x0C
	52	+
	53	+#define OXU_CHIPIRQSTATUS 0x10
	54	+#define OXU_CHIPIRQEN_SET 0x14
	55	+#define OXU_CHIPIRQEN_CLR 0x18
	56	+ #define OXU_USBSPHLPWUI 0x00000080
	57	+ #define OXU_USBOTGLPWUI 0x00000040
	58	+ #define OXU_USBSPHI 0x00000002
	59	+ #define OXU_USBOTGI 0x00000001
	60	+
	61	+#define OXU_CLKCTRL_SET 0x1C
	62	+ #define OXU_SYSCLKEN 0x00000008
	63	+ #define OXU_USBSPHCLKEN 0x00000002
	64	+ #define OXU_USBOTGCLKEN 0x00000001
	65	+
	66	+#define OXU_ASO 0x68
	67	+ #define OXU_SPHPOEN 0x00000100
	68	+ #define OXU_OVRCCURPUPDEN 0x00000800
	69	+ #define OXU_ASO_OP (1 << 10)
	70	+ #define OXU_COMPARATOR 0x000004000
	71	+
	72	+#define OXU_USBMODE 0x1A8
	73	+ #define OXU_VBPS 0x00000020
	74	+ #define OXU_ES_LITTLE 0x00000000
	75	+ #define OXU_CM_HOST_ONLY 0x00000003
	76	+
	77	+/*
	78	+ * Proper EHCI structs & defines
	79	+ */
	80	+
	81	+/* Magic numbers that can affect system performance */
	82	+#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
	83	+#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
	84	+#define EHCI_TUNE_RL_TT 0
	85	+#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
	86	+#define EHCI_TUNE_MULT_TT 1
	87	+#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
	88	+
	89	+struct oxu_hcd;
	90	+
	91	+/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
	92	+
	93	+/* Section 2.2 Host Controller Capability Registers */
	94	+struct ehci_caps {
	95	+ /* these fields are specified as 8 and 16 bit registers,
	96	+ * but some hosts can't perform 8 or 16 bit PCI accesses.
	97	+ */
	98	+ u32 hc_capbase;
	99	+#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
	100	+#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
	101	+ u32 hcs_params; /* HCSPARAMS - offset 0x4 */
	102	+#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
	103	+#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
	104	+#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
	105	+#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
	106	+#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
	107	+#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
	108	+#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
	109	+
	110	+ u32 hcc_params; /* HCCPARAMS - offset 0x8 */
	111	+#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
	112	+#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
	113	+#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
	114	+#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
	115	+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
	116	+#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
	117	+ u8 portroute[8]; /* nibbles for routing - offset 0xC */
	118	+} __packed;
	119	+
	120	+
	121	+/* Section 2.3 Host Controller Operational Registers */
	122	+struct ehci_regs {
	123	+ /* USBCMD: offset 0x00 */
	124	+ u32 command;
	125	+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
	126	+#define CMD_PARK (1<<11) /* enable "park" on async qh */
	127	+#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
	128	+#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
	129	+#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
	130	+#define CMD_ASE (1<<5) /* async schedule enable */
	131	+#define CMD_PSE (1<<4) /* periodic schedule enable */
	132	+/* 3:2 is periodic frame list size */
	133	+#define CMD_RESET (1<<1) /* reset HC not bus */
	134	+#define CMD_RUN (1<<0) /* start/stop HC */
	135	+
	136	+ /* USBSTS: offset 0x04 */
	137	+ u32 status;
	138	+#define STS_ASS (1<<15) /* Async Schedule Status */
	139	+#define STS_PSS (1<<14) /* Periodic Schedule Status */
	140	+#define STS_RECL (1<<13) /* Reclamation */
	141	+#define STS_HALT (1<<12) /* Not running (any reason) */
	142	+/* some bits reserved */
	143	+ /* these STS_* flags are also intr_enable bits (USBINTR) */
	144	+#define STS_IAA (1<<5) /* Interrupted on async advance */
	145	+#define STS_FATAL (1<<4) /* such as some PCI access errors */
	146	+#define STS_FLR (1<<3) /* frame list rolled over */
	147	+#define STS_PCD (1<<2) /* port change detect */
	148	+#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
	149	+#define STS_INT (1<<0) /* "normal" completion (short, ...) */
	150	+
	151	+#define INTR_MASK (STS_IAA \| STS_FATAL \| STS_PCD \| STS_ERR \| STS_INT)
	152	+
	153	+ /* USBINTR: offset 0x08 */
	154	+ u32 intr_enable;
	155	+
	156	+ /* FRINDEX: offset 0x0C */
	157	+ u32 frame_index; /* current microframe number */
	158	+ /* CTRLDSSEGMENT: offset 0x10 */
	159	+ u32 segment; /* address bits 63:32 if needed */
	160	+ /* PERIODICLISTBASE: offset 0x14 */
	161	+ u32 frame_list; /* points to periodic list */
	162	+ /* ASYNCLISTADDR: offset 0x18 */
	163	+ u32 async_next; /* address of next async queue head */
	164	+
	165	+ u32 reserved[9];
	166	+
	167	+ /* CONFIGFLAG: offset 0x40 */
	168	+ u32 configured_flag;
	169	+#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
	170	+
	171	+ /* PORTSC: offset 0x44 */
	172	+ u32 port_status[0]; /* up to N_PORTS */
	173	+/* 31:23 reserved */
	174	+#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
	175	+#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
	176	+#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
	177	+/* 19:16 for port testing */
	178	+#define PORT_LED_OFF (0<<14)
	179	+#define PORT_LED_AMBER (1<<14)
	180	+#define PORT_LED_GREEN (2<<14)
	181	+#define PORT_LED_MASK (3<<14)
	182	+#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
	183	+#define PORT_POWER (1<<12) /* true: has power (see PPC) */
	184	+#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
	185	+/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
	186	+/* 9 reserved */
	187	+#define PORT_RESET (1<<8) /* reset port */
	188	+#define PORT_SUSPEND (1<<7) /* suspend port */
	189	+#define PORT_RESUME (1<<6) /* resume it */
	190	+#define PORT_OCC (1<<5) /* over current change */
	191	+#define PORT_OC (1<<4) /* over current active */
	192	+#define PORT_PEC (1<<3) /* port enable change */
	193	+#define PORT_PE (1<<2) /* port enable */
	194	+#define PORT_CSC (1<<1) /* connect status change */
	195	+#define PORT_CONNECT (1<<0) /* device connected */
	196	+#define PORT_RWC_BITS (PORT_CSC \| PORT_PEC \| PORT_OCC)
	197	+} __packed;
	198	+
	199	+/* Appendix C, Debug port ... intended for use with special "debug devices"
	200	+ * that can help if there's no serial console. (nonstandard enumeration.)
	201	+ */
	202	+struct ehci_dbg_port {
	203	+ u32 control;
	204	+#define DBGP_OWNER (1<<30)
	205	+#define DBGP_ENABLED (1<<28)
	206	+#define DBGP_DONE (1<<16)
	207	+#define DBGP_INUSE (1<<10)
	208	+#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
	209	+# define DBGP_ERR_BAD 1
	210	+# define DBGP_ERR_SIGNAL 2
	211	+#define DBGP_ERROR (1<<6)
	212	+#define DBGP_GO (1<<5)
	213	+#define DBGP_OUT (1<<4)
	214	+#define DBGP_LEN(x) (((x)>>0)&0x0f)
	215	+ u32 pids;
	216	+#define DBGP_PID_GET(x) (((x)>>16)&0xff)
	217	+#define DBGP_PID_SET(data, tok) (((data)<<8)\|(tok))
	218	+ u32 data03;
	219	+ u32 data47;
	220	+ u32 address;
	221	+#define DBGP_EPADDR(dev, ep) (((dev)<<8)\|(ep))
	222	+} __packed;
	223	+
	224	+#define QTD_NEXT(dma) cpu_to_le32((u32)dma)
	225	+
	226	+/*
	227	+ * EHCI Specification 0.95 Section 3.5
	228	+ * QTD: describe data transfer components (buffer, direction, ...)
	229	+ * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
	230	+ *
	231	+ * These are associated only with "QH" (Queue Head) structures,
	232	+ * used with control, bulk, and interrupt transfers.
	233	+ */
	234	+struct ehci_qtd {
	235	+ /* first part defined by EHCI spec */
	236	+ __le32 hw_next; /* see EHCI 3.5.1 */
	237	+ __le32 hw_alt_next; /* see EHCI 3.5.2 */
	238	+ __le32 hw_token; /* see EHCI 3.5.3 */
	239	+#define QTD_TOGGLE (1 << 31) /* data toggle */
	240	+#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
	241	+#define QTD_IOC (1 << 15) /* interrupt on complete */
	242	+#define QTD_CERR(tok) (((tok)>>10) & 0x3)
	243	+#define QTD_PID(tok) (((tok)>>8) & 0x3)
	244	+#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
	245	+#define QTD_STS_HALT (1 << 6) /* halted on error */
	246	+#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
	247	+#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
	248	+#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
	249	+#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
	250	+#define QTD_STS_STS (1 << 1) /* split transaction state */
	251	+#define QTD_STS_PING (1 << 0) /* issue PING? */
	252	+ __le32 hw_buf[5]; /* see EHCI 3.5.4 */
	253	+ __le32 hw_buf_hi[5]; /* Appendix B */
	254	+
	255	+ /* the rest is HCD-private */
	256	+ dma_addr_t qtd_dma; /* qtd address */
	257	+ struct list_head qtd_list; /* sw qtd list */
	258	+ struct urb urb; / qtd's urb */
	259	+ size_t length; /* length of buffer */
	260	+
	261	+ u32 qtd_buffer_len;
	262	+ void *buffer;
	263	+ dma_addr_t buffer_dma;
	264	+ void *transfer_buffer;
	265	+ void *transfer_dma;
	266	+} __aligned(32);
	267	+
	268	+/* mask NakCnt+T in qh->hw_alt_next */
	269	+#define QTD_MASK cpu_to_le32 (~0x1f)
	270	+
	271	+#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
	272	+
	273	+/* Type tag from {qh, itd, sitd, fstn}->hw_next */
	274	+#define Q_NEXT_TYPE(dma) ((dma) & cpu_to_le32 (3 << 1))
	275	+
	276	+/* values for that type tag */
	277	+#define Q_TYPE_QH cpu_to_le32 (1 << 1)
	278	+
	279	+/* next async queue entry, or pointer to interrupt/periodic QH */
	280	+#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)\|Q_TYPE_QH)
	281	+
	282	+/* for periodic/async schedules and qtd lists, mark end of list */
	283	+#define EHCI_LIST_END cpu_to_le32(1) /* "null pointer" to hw */
	284	+
	285	+/*
	286	+ * Entries in periodic shadow table are pointers to one of four kinds
	287	+ * of data structure. That's dictated by the hardware; a type tag is
	288	+ * encoded in the low bits of the hardware's periodic schedule. Use
	289	+ * Q_NEXT_TYPE to get the tag.
	290	+ *
	291	+ * For entries in the async schedule, the type tag always says "qh".
	292	+ */
	293	+union ehci_shadow {
	294	+ struct ehci_qh qh; / Q_TYPE_QH */
	295	+ __le32 hw_next; / (all types) */
	296	+ void *ptr;
	297	+};
	298	+
	299	+/*
	300	+ * EHCI Specification 0.95 Section 3.6
	301	+ * QH: describes control/bulk/interrupt endpoints
	302	+ * See Fig 3-7 "Queue Head Structure Layout".
	303	+ *
	304	+ * These appear in both the async and (for interrupt) periodic schedules.
	305	+ */
	306	+
	307	+struct ehci_qh {
	308	+ /* first part defined by EHCI spec */
	309	+ __le32 hw_next; /* see EHCI 3.6.1 */
	310	+ __le32 hw_info1; /* see EHCI 3.6.2 */
	311	+#define QH_HEAD 0x00008000
	312	+ __le32 hw_info2; /* see EHCI 3.6.2 */
	313	+#define QH_SMASK 0x000000ff
	314	+#define QH_CMASK 0x0000ff00
	315	+#define QH_HUBADDR 0x007f0000
	316	+#define QH_HUBPORT 0x3f800000
	317	+#define QH_MULT 0xc0000000
	318	+ __le32 hw_current; /* qtd list - see EHCI 3.6.4 */
	319	+
	320	+ /* qtd overlay (hardware parts of a struct ehci_qtd) */
	321	+ __le32 hw_qtd_next;
	322	+ __le32 hw_alt_next;
	323	+ __le32 hw_token;
	324	+ __le32 hw_buf[5];
	325	+ __le32 hw_buf_hi[5];
	326	+
	327	+ /* the rest is HCD-private */
	328	+ dma_addr_t qh_dma; /* address of qh */
	329	+ union ehci_shadow qh_next; /* ptr to qh; or periodic */
	330	+ struct list_head qtd_list; /* sw qtd list */
	331	+ struct ehci_qtd *dummy;
	332	+ struct ehci_qh reclaim; / next to reclaim */
	333	+
	334	+ struct oxu_hcd *oxu;
	335	+ struct kref kref;
	336	+ unsigned int stamp;
	337	+
	338	+ u8 qh_state;
	339	+#define QH_STATE_LINKED 1 /* HC sees this */
	340	+#define QH_STATE_UNLINK 2 /* HC may still see this */
	341	+#define QH_STATE_IDLE 3 /* HC doesn't see this */
	342	+#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
	343	+#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
	344	+
	345	+ /* periodic schedule info */
	346	+ u8 usecs; /* intr bandwidth */
	347	+ u8 gap_uf; /* uframes split/csplit gap */
	348	+ u8 c_usecs; /* ... split completion bw */
	349	+ u16 tt_usecs; /* tt downstream bandwidth */
	350	+ unsigned short period; /* polling interval */
	351	+ unsigned short start; /* where polling starts */
	352	+#define NO_FRAME ((unsigned short)~0) /* pick new start */
	353	+ struct usb_device dev; / access to TT */
	354	+} __aligned(32);
	355	+
	356	+/*
	357	+ * Proper OXU210HP structs
	358	+ */
	359	+
	360	+#define OXU_OTG_CORE_OFFSET 0x00400
	361	+#define OXU_OTG_CAP_OFFSET (OXU_OTG_CORE_OFFSET + 0x100)
	362	+#define OXU_SPH_CORE_OFFSET 0x00800
	363	+#define OXU_SPH_CAP_OFFSET (OXU_SPH_CORE_OFFSET + 0x100)
	364	+
	365	+#define OXU_OTG_MEM 0xE000
	366	+#define OXU_SPH_MEM 0x16000
	367	+
	368	+/* Only how many elements & element structure are specifies here. */
	369	+/* 2 host controllers are enabled - total size <= 28 kbytes */
	370	+#define DEFAULT_I_TDPS 1024
	371	+#define QHEAD_NUM 16
	372	+#define QTD_NUM 32
	373	+#define SITD_NUM 8
	374	+#define MURB_NUM 8
	375	+
	376	+#define BUFFER_NUM 8
	377	+#define BUFFER_SIZE 512
	378	+
	379	+struct oxu_info {
	380	+ struct usb_hcd *hcd[2];
	381	+};
	382	+
	383	+struct oxu_buf {
	384	+ u8 buffer[BUFFER_SIZE];
	385	+} __aligned(BUFFER_SIZE);
	386	+
	387	+struct oxu_onchip_mem {
	388	+ struct oxu_buf db_pool[BUFFER_NUM];
	389	+
	390	+ u32 frame_list[DEFAULT_I_TDPS];
	391	+ struct ehci_qh qh_pool[QHEAD_NUM];
	392	+ struct ehci_qtd qtd_pool[QTD_NUM];
	393	+} __aligned(4 << 10);
	394	+
	395	+#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
	396	+
	397	+struct oxu_murb {
	398	+ struct urb urb;
	399	+ struct urb *main;
	400	+ u8 last;
	401	+};
	402	+
	403	+struct oxu_hcd { /* one per controller */
	404	+ unsigned int is_otg:1;
	405	+
	406	+ u8 qh_used[QHEAD_NUM];
	407	+ u8 qtd_used[QTD_NUM];
	408	+ u8 db_used[BUFFER_NUM];
	409	+ u8 murb_used[MURB_NUM];
	410	+
	411	+ struct oxu_onchip_mem __iomem *mem;
	412	+ spinlock_t mem_lock;
	413	+
	414	+ struct timer_list urb_timer;
	415	+
	416	+ struct ehci_caps __iomem *caps;
	417	+ struct ehci_regs __iomem *regs;
	418	+
	419	+ u32 hcs_params; /* cached register copy */
	420	+ spinlock_t lock;
	421	+
	422	+ /* async schedule support */
	423	+ struct ehci_qh *async;
	424	+ struct ehci_qh *reclaim;
	425	+ unsigned int reclaim_ready:1;
	426	+ unsigned int scanning:1;
	427	+
	428	+ /* periodic schedule support */
	429	+ unsigned int periodic_size;
	430	+ __le32 periodic; / hw periodic table */
	431	+ dma_addr_t periodic_dma;
	432	+ unsigned int i_thresh; /* uframes HC might cache */
	433	+
	434	+ union ehci_shadow pshadow; / mirror hw periodic table */
	435	+ int next_uframe; /* scan periodic, start here */
	436	+ unsigned int periodic_sched; /* periodic activity count */
	437	+
	438	+ /* per root hub port */
	439	+ unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
	440	+ /* bit vectors (one bit per port) */
	441	+ unsigned long bus_suspended; /* which ports were
	442	+ * already suspended at the
	443	+ * start of a bus suspend
	444	+ */
	445	+ unsigned long companion_ports;/* which ports are dedicated
	446	+ * to the companion controller
	447	+ */
	448	+
	449	+ struct timer_list watchdog;
	450	+ unsigned long actions;
	451	+ unsigned int stamp;
	452	+ unsigned long next_statechange;
	453	+ u32 command;
	454	+
	455	+ /* SILICON QUIRKS */
	456	+ struct list_head urb_list; /* this is the head to urb
	457	+ * queue that didn't get enough
	458	+ * resources
	459	+ */
	460	+ struct oxu_murb murb_pool; / murb per split big urb */
	461	+ unsigned int urb_len;
	462	+
	463	+ u8 sbrn; /* packed release number */
	464	+};
	465	+
	466	+#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
	467	+#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
	468	+#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
	469	+#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
	470	+
	471	+enum ehci_timer_action {
	472	+ TIMER_IO_WATCHDOG,
	473	+ TIMER_IAA_WATCHDOG,
	474	+ TIMER_ASYNC_SHRINK,
	475	+ TIMER_ASYNC_OFF,
	476	+};
37	477
38	478	/*
39	479	* Main defines
..	..	@@ -237,12 +677,12 @@
237	677	*/
238	678
239	679	/* Low level read/write registers functions */
240		-static inline u32 oxu_readl(void *base, u32 reg)
	680	+static inline u32 oxu_readl(void __iomem *base, u32 reg)
241	681	{
242	682	return readl(base + reg);
243	683	}
244	684
245		-static inline void oxu_writel(void *base, u32 reg, u32 val)
	685	+static inline void oxu_writel(void __iomem *base, u32 reg, u32 val)
246	686	{
247	687	writel(val, base + reg);
248	688	}
..	..	@@ -309,18 +749,16 @@
309	749	u32 mask, u32 done, int usec)
310	750	{
311	751	u32 result;
	752	+ int ret;
312	753
313		- do {
314		- result = readl(ptr);
315		- if (result == ~(u32)0) /* card removed */
316		- return -ENODEV;
317		- result &= mask;
318		- if (result == done)
319		- return 0;
320		- udelay(1);
321		- usec--;
322		- } while (usec > 0);
323		- return -ETIMEDOUT;
	754	+ ret = readl_poll_timeout_atomic(ptr, result,
	755	+ ((result & mask) == done \|\|
	756	+ result == U32_MAX),
	757	+ 1, usec);
	758	+ if (result == U32_MAX) /* card removed */
	759	+ return -ENODEV;
	760	+
	761	+ return ret;
324	762	}
325	763
326	764	/* Force HC to halt state from unknown (EHCI spec section 2.3) */
..	..	@@ -1323,7 +1761,7 @@
1323	1761	}
1324	1762
1325	1763	/* by default, enable interrupt on urb completion */
1326		- qtd->hw_token \|= cpu_to_le32(QTD_IOC);
	1764	+ qtd->hw_token \|= cpu_to_le32(QTD_IOC);
1327	1765	return head;
1328	1766
1329	1767	cleanup:
..	..	@@ -1419,7 +1857,7 @@
1419	1857	switch (urb->dev->speed) {
1420	1858	case USB_SPEED_LOW:
1421	1859	info1 \|= (1 << 12); /* EPS "low" */
1422		- /* FALL THROUGH */
	1860	+ fallthrough;
1423	1861
1424	1862	case USB_SPEED_FULL:
1425	1863	/* EPS 0 means "full" */
..	..	@@ -1598,16 +2036,15 @@
1598	2036	static int submit_async(struct oxu_hcd oxu, struct urb urb,
1599	2037	struct list_head *qtd_list, gfp_t mem_flags)
1600	2038	{
1601		- struct ehci_qtd *qtd;
1602		- int epnum;
	2039	+ int epnum = urb->ep->desc.bEndpointAddress;
1603	2040	unsigned long flags;
1604	2041	struct ehci_qh *qh = NULL;
1605	2042	int rc = 0;
	2043	+#ifdef OXU_URB_TRACE
	2044	+ struct ehci_qtd *qtd;
1606	2045
1607	2046	qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
1608		- epnum = urb->ep->desc.bEndpointAddress;
1609	2047
1610		-#ifdef OXU_URB_TRACE
1611	2048	oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
1612	2049	__func__, urb->dev->devpath, urb,
1613	2050	epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
..	..	@@ -2253,16 +2690,12 @@
2253	2690	for (;;) {
2254	2691	union ehci_shadow q, *q_p;
2255	2692	__le32 type, *hw_p;
2256		- unsigned uframes;
2257	2693
2258	2694	/* don't scan past the live uframe */
2259	2695	frame = now_uframe >> 3;
2260		- if (frame == (clock >> 3))
2261		- uframes = now_uframe & 0x07;
2262		- else {
	2696	+ if (frame != (clock >> 3)) {
2263	2697	/* safe to scan the whole frame at once */
2264	2698	now_uframe \|= 0x07;
2265		- uframes = 8;
2266	2699	}
2267	2700
2268	2701	restart:
..	..	@@ -2348,11 +2781,15 @@
2348	2781	return;
2349	2782
2350	2783	oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down");
2351		- for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; )
2352		- (void) oxu_hub_control(oxu_to_hcd(oxu),
2353		- is_on ? SetPortFeature : ClearPortFeature,
2354		- USB_PORT_FEAT_POWER,
2355		- port--, NULL, 0);
	2784	+ for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; ) {
	2785	+ if (is_on)
	2786	+ oxu_hub_control(oxu_to_hcd(oxu), SetPortFeature,
	2787	+ USB_PORT_FEAT_POWER, port--, NULL, 0);
	2788	+ else
	2789	+ oxu_hub_control(oxu_to_hcd(oxu), ClearPortFeature,
	2790	+ USB_PORT_FEAT_POWER, port--, NULL, 0);
	2791	+ }
	2792	+
2356	2793	msleep(20);
2357	2794	}
2358	2795
..	..	@@ -2653,9 +3090,6 @@
2653	3090	INIT_LIST_HEAD(&oxu->urb_list);
2654	3091	oxu->urb_len = 0;
2655	3092
2656		- /* FIMXE */
2657		- hcd->self.controller->dma_mask = NULL;
2658		-
2659	3093	if (oxu->is_otg) {
2660	3094	oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET;
2661	3095	oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \
..	..	@@ -2832,7 +3266,6 @@
2832	3266	{
2833	3267	struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2834	3268	int num, rem;
2835		- int transfer_buffer_length;
2836	3269	void *transfer_buffer;
2837	3270	struct urb *murb;
2838	3271	int i, ret;
..	..	@@ -2843,7 +3276,6 @@
2843	3276
2844	3277	/* Otherwise we should verify the USB transfer buffer size! */
2845	3278	transfer_buffer = urb->transfer_buffer;
2846		- transfer_buffer_length = urb->transfer_buffer_length;
2847	3279
2848	3280	num = urb->transfer_buffer_length / 4096;
2849	3281	rem = urb->transfer_buffer_length % 4096;
..	..	@@ -2944,7 +3376,7 @@
2944	3376	switch (qh->qh_state) {
2945	3377	case QH_STATE_LINKED:
2946	3378	intr_deschedule(oxu, qh);
2947		- /* FALL THROUGH */
	3379	+ fallthrough;
2948	3380	case QH_STATE_IDLE:
2949	3381	qh_completions(oxu, qh);
2950	3382	break;
..	..	@@ -3016,7 +3448,7 @@
3016	3448	if (!tmp)
3017	3449	goto nogood;
3018	3450	unlink_async(oxu, qh);
3019		- /* FALL THROUGH */
	3451	+ fallthrough;
3020	3452	case QH_STATE_UNLINK: /* wait for hw to finish? */
3021	3453	idle_timeout:
3022	3454	spin_unlock_irqrestore(&oxu->lock, flags);
..	..	@@ -3027,7 +3459,7 @@
3027	3459	qh_put(qh);
3028	3460	break;
3029	3461	}
3030		- /* fall through */
	3462	+ fallthrough;
3031	3463	default:
3032	3464	nogood:
3033	3465	/* caller was supposed to have unlinked any requests;
..	..	@@ -3476,8 +3908,10 @@
3476	3908	}
3477	3909	}
3478	3910
	3911	+ spin_unlock_irq(&oxu->lock);
3479	3912	/* turn off now-idle HC */
3480	3913	del_timer_sync(&oxu->watchdog);
	3914	+ spin_lock_irq(&oxu->lock);
3481	3915	ehci_halt(oxu);
3482	3916	hcd->state = HC_STATE_SUSPENDED;
3483	3917
..	..	@@ -3633,7 +4067,7 @@
3633	4067	* Module stuff
3634	4068	*/
3635	4069
3636		-static void oxu_configuration(struct platform_device pdev, void base)
	4070	+static void oxu_configuration(struct platform_device pdev, void __iomem base)
3637	4071	{
3638	4072	u32 tmp;
3639	4073
..	..	@@ -3663,7 +4097,7 @@
3663	4097	oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI \| OXU_USBOTGLPWUI);
3664	4098	}
3665	4099
3666		-static int oxu_verify_id(struct platform_device pdev, void base)
	4100	+static int oxu_verify_id(struct platform_device pdev, void __iomem base)
3667	4101	{
3668	4102	u32 id;
3669	4103	static const char * const bo[] = {
..	..	@@ -3691,7 +4125,7 @@
3691	4125	static const struct hc_driver oxu_hc_driver;
3692	4126	static struct usb_hcd oxu_create(struct platform_device pdev,
3693	4127	unsigned long memstart, unsigned long memlen,
3694		- void *base, int irq, int otg)
	4128	+ void __iomem *base, int irq, int otg)
3695	4129	{
3696	4130	struct device *dev = &pdev->dev;
3697	4131
..	..	@@ -3730,7 +4164,7 @@
3730	4164
3731	4165	static int oxu_init(struct platform_device *pdev,
3732	4166	unsigned long memstart, unsigned long memlen,
3733		- void *base, int irq)
	4167	+ void __iomem *base, int irq)
3734	4168	{
3735	4169	struct oxu_info *info = platform_get_drvdata(pdev);
3736	4170	struct usb_hcd *hcd;
..	..	@@ -3779,7 +4213,7 @@
3779	4213	static int oxu_drv_probe(struct platform_device *pdev)
3780	4214	{
3781	4215	struct resource *res;
3782		- void *base;
	4216	+ void __iomem *base;
3783	4217	unsigned long memstart, memlen;
3784	4218	int irq, ret;
3785	4219	struct oxu_info *info;