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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/usb/dwc3/core.h
....@@ -1,8 +1,8 @@
1
-// SPDX-License-Identifier: GPL-2.0
1
+/* SPDX-License-Identifier: GPL-2.0 */
22 /*
33  * core.h - DesignWare USB3 DRD Core Header
44  *
5
- * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5
+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
66  *
77  * Authors: Felipe Balbi <balbi@ti.com>,
88  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
....@@ -13,6 +13,7 @@
1313 
1414 #include <linux/device.h>
1515 #include <linux/spinlock.h>
16
+#include <linux/mutex.h>
1617 #include <linux/ioport.h>
1718 #include <linux/list.h>
1819 #include <linux/bitops.h>
....@@ -21,18 +22,21 @@
2122 #include <linux/debugfs.h>
2223 #include <linux/wait.h>
2324 #include <linux/workqueue.h>
25
+#include <linux/android_kabi.h>
2426 
2527 #include <linux/usb/ch9.h>
2628 #include <linux/usb/gadget.h>
2729 #include <linux/usb/otg.h>
30
+#include <linux/usb/role.h>
2831 #include <linux/ulpi/interface.h>
2932 
3033 #include <linux/phy/phy.h>
3134 
35
+#include <linux/power_supply.h>
36
+
3237 #define DWC3_MSG_MAX	500
3338 
3439 /* Global constants */
35
-#define DWC3_DISCON_TIMEOUT	1000	/* ms */
3640 #define DWC3_PULL_UP_TIMEOUT	500	/* ms */
3741 #define DWC3_BOUNCE_SIZE	1024	/* size of a superspeed bulk */
3842 #define DWC3_EP0_SETUP_SIZE	512
....@@ -54,7 +58,7 @@
5458 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
5559 #define DWC3_DEVICE_EVENT_WAKEUP		4
5660 #define DWC3_DEVICE_EVENT_HIBER_REQ		5
57
-#define DWC3_DEVICE_EVENT_EOPF			6
61
+#define DWC3_DEVICE_EVENT_SUSPEND		6
5862 #define DWC3_DEVICE_EVENT_SOF			7
5963 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
6064 #define DWC3_DEVICE_EVENT_CMD_CMPL		10
....@@ -69,6 +73,7 @@
6973 #define DWC3_GEVNTCOUNT_EHB	BIT(31)
7074 #define DWC3_GSNPSID_MASK	0xffff0000
7175 #define DWC3_GSNPSREV_MASK	0xffff
76
+#define DWC3_GSNPS_ID(p)	(((p) & DWC3_GSNPSID_MASK) >> 16)
7277 
7378 /* DWC3 registers memory space boundries */
7479 #define DWC3_XHCI_REGS_START		0x0
....@@ -137,7 +142,9 @@
137142 #define DWC3_GEVNTCOUNT(n)	(0xc40c + ((n) * 0x10))
138143 
139144 #define DWC3_GHWPARAMS8		0xc600
145
+#define DWC3_GUCTL3		0xc60c
140146 #define DWC3_GFLADJ		0xc630
147
+#define DWC3_GHWPARAMS9		0xc6e0
141148 
142149 /* Device Registers */
143150 #define DWC3_DCFG		0xc700
....@@ -250,10 +257,11 @@
250257 #define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
251258 
252259 /* Global User Control 1 Register */
260
+#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
253261 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
254262 #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
255
-#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
256
-#define DWC3_GUCTL1_PARKMODE_DISABLE_SS	BIT(17)
263
+#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
264
+#define DWC3_GUCTL1_PARKMODE_DISABLE_SS		BIT(17)
257265 
258266 /* Global Status Register */
259267 #define DWC3_GSTS_OTG_IP	BIT(10)
....@@ -309,13 +317,14 @@
309317 
310318 /* Global TX Fifo Size Register */
311319 #define DWC31_GTXFIFOSIZ_TXFRAMNUM	BIT(15)		/* DWC_usb31 only */
312
-#define DWC31_GTXFIFOSIZ_TXFDEF(n)	((n) & 0x7fff)	/* DWC_usb31 only */
313
-#define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
320
+#define DWC31_GTXFIFOSIZ_TXFDEP(n)	((n) & 0x7fff)	/* DWC_usb31 only */
321
+#define DWC3_GTXFIFOSIZ_TXFDEP(n)	((n) & 0xffff)
314322 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)	((n) & 0xffff0000)
315323 
316324 /* Global RX Fifo Size Register */
317325 #define DWC31_GRXFIFOSIZ_RXFDEP(n)	((n) & 0x7fff)	/* DWC_usb31 only */
318326 #define DWC3_GRXFIFOSIZ_RXFDEP(n)	((n) & 0xffff)
327
+#define DWC3_GRXFIFOSIZ_RXFSTADDR(n)	((n) & 0xffff0000)
319328 
320329 /* Global Event Size Registers */
321330 #define DWC3_GEVNTSIZ_INTMASK		BIT(31)
....@@ -366,10 +375,17 @@
366375 #define DWC3_GHWPARAMS6_HNPSUPPORT		BIT(11)
367376 #define DWC3_GHWPARAMS6_SRPSUPPORT		BIT(10)
368377 #define DWC3_GHWPARAMS6_EN_FPGA			BIT(7)
378
+#define DWC3_GHWPARAMS6_RAM0_DEPTH(n)		(((n) >> 16) & 0xffff)
379
+
380
+/* DWC_usb32 only */
381
+#define DWC3_GHWPARAMS6_MDWIDTH(n)		((n) & (0x3 << 8))
369382 
370383 /* Global HWPARAMS7 Register */
371384 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n)	((n) & 0xffff)
372385 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n)	(((n) >> 16) & 0xffff)
386
+
387
+/* Global HWPARAMS9 Register */
388
+#define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS	BIT(0)
373389 
374390 /* Global Frame Length Adjustment Register */
375391 #define DWC3_GFLADJ_30MHZ_SDBND_SEL		BIT(7)
....@@ -378,7 +394,12 @@
378394 /* Global User Control Register 2 */
379395 #define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)
380396 
397
+/* Global User Control Register 3 */
398
+#define DWC3_GUCTL3_SPLITDISABLE		BIT(14)
399
+
381400 /* Device Configuration Register */
401
+#define DWC3_DCFG_NUMLANES(n)	(((n) & 0x3) << 30) /* DWC_usb32 only */
402
+
382403 #define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)
383404 #define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)
384405 
....@@ -393,6 +414,7 @@
393414 #define DWC3_DCFG_NUMP(n)	(((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
394415 #define DWC3_DCFG_NUMP_MASK	(0x1f << DWC3_DCFG_NUMP_SHIFT)
395416 #define DWC3_DCFG_LPM_CAP	BIT(22)
417
+#define DWC3_DCFG_IGNSTRMPP	BIT(23)
396418 
397419 /* Device Control Register */
398420 #define DWC3_DCTL_RUN_STOP	BIT(31)
....@@ -444,13 +466,15 @@
444466 #define DWC3_DEVTEN_CMDCMPLTEN		BIT(10)
445467 #define DWC3_DEVTEN_ERRTICERREN		BIT(9)
446468 #define DWC3_DEVTEN_SOFEN		BIT(7)
447
-#define DWC3_DEVTEN_EOPFEN		BIT(6)
469
+#define DWC3_DEVTEN_U3L2L1SUSPEN	BIT(6)
448470 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN	BIT(5)
449471 #define DWC3_DEVTEN_WKUPEVTEN		BIT(4)
450472 #define DWC3_DEVTEN_ULSTCNGEN		BIT(3)
451473 #define DWC3_DEVTEN_CONNECTDONEEN	BIT(2)
452474 #define DWC3_DEVTEN_USBRSTEN		BIT(1)
453475 #define DWC3_DEVTEN_DISCONNEVTEN	BIT(0)
476
+
477
+#define DWC3_DSTS_CONNLANES(n)		(((n) >> 30) & 0x3) /* DWC_usb32 only */
454478 
455479 /* Device Status Register */
456480 #define DWC3_DSTS_DCNRD			BIT(29)
....@@ -493,6 +517,7 @@
493517 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH	0x09
494518 #define DWC3_DGCMD_ALL_FIFO_FLUSH	0x0a
495519 #define DWC3_DGCMD_SET_ENDPOINT_NRDY	0x0c
520
+#define DWC3_DGCMD_SET_ENDPOINT_PRIME	0x0d
496521 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK	0x10
497522 
498523 #define DWC3_DGCMD_STATUS(n)		(((n) >> 12) & 0x0F)
....@@ -631,7 +656,7 @@
631656 struct dwc3_event_buffer {
632657 	void			*buf;
633658 	void			*cache;
634
-	unsigned		length;
659
+	unsigned int		length;
635660 	unsigned int		lpos;
636661 	unsigned int		count;
637662 	unsigned int		flags;
....@@ -641,6 +666,8 @@
641666 	dma_addr_t		dma;
642667 
643668 	struct dwc3		*dwc;
669
+
670
+	ANDROID_KABI_RESERVE(1);
644671 };
645672 
646673 #define DWC3_EP_FLAG_STALLED	BIT(0)
....@@ -657,7 +684,6 @@
657684  * @cancelled_list: list of cancelled requests for this endpoint
658685  * @pending_list: list of pending requests for this endpoint
659686  * @started_list: list of started requests on this endpoint
660
- * @lock: spinlock for endpoint request queue traversal
661687  * @regs: pointer to first endpoint register
662688  * @trb_pool: array of transaction buffers
663689  * @trb_pool_dma: dma address of @trb_pool
....@@ -685,7 +711,6 @@
685711 	struct list_head	pending_list;
686712 	struct list_head	started_list;
687713 
688
-	spinlock_t		lock;
689714 	void __iomem		*regs;
690715 
691716 	struct dwc3_trb		*trb_pool;
....@@ -693,7 +718,7 @@
693718 	struct dwc3		*dwc;
694719 
695720 	u32			saved_state;
696
-	unsigned		flags;
721
+	unsigned int		flags;
697722 #define DWC3_EP_ENABLED		BIT(0)
698723 #define DWC3_EP_STALL		BIT(1)
699724 #define DWC3_EP_WEDGE		BIT(2)
....@@ -701,6 +726,13 @@
701726 #define DWC3_EP_END_TRANSFER_PENDING BIT(4)
702727 #define DWC3_EP_PENDING_REQUEST	BIT(5)
703728 #define DWC3_EP_DELAY_START	BIT(6)
729
+#define DWC3_EP_WAIT_TRANSFER_COMPLETE	BIT(7)
730
+#define DWC3_EP_IGNORE_NEXT_NOSTREAM	BIT(8)
731
+#define DWC3_EP_FORCE_RESTART_STREAM	BIT(9)
732
+#define DWC3_EP_FIRST_STREAM_PRIMED	BIT(10)
733
+#define DWC3_EP_PENDING_CLEAR_STALL	BIT(11)
734
+#define DWC3_EP_TXFIFO_RESIZED		BIT(12)
735
+#define DWC3_EP_DELAY_STOP             BIT(13)
704736 
705737 	/* This last one is specific to EP0 */
706738 #define DWC3_EP0_DIR_IN		BIT(31)
....@@ -731,6 +763,9 @@
731763 	/* For isochronous START TRANSFER workaround only */
732764 	u8			combo_num;
733765 	int			start_cmd_status;
766
+
767
+	ANDROID_KABI_RESERVE(1);
768
+	ANDROID_KABI_RESERVE(2);
734769 };
735770 
736771 enum dwc3_phy {
....@@ -829,6 +864,7 @@
829864  * @hwparams6: GHWPARAMS6
830865  * @hwparams7: GHWPARAMS7
831866  * @hwparams8: GHWPARAMS8
867
+ * @hwparams9: GHWPARAMS9
832868  */
833869 struct dwc3_hwparams {
834870 	u32	hwparams0;
....@@ -840,15 +876,18 @@
840876 	u32	hwparams6;
841877 	u32	hwparams7;
842878 	u32	hwparams8;
879
+	u32	hwparams9;
880
+
881
+	ANDROID_KABI_RESERVE(1);
882
+	ANDROID_KABI_RESERVE(2);
843883 };
844884 
845885 /* HWPARAMS0 */
846886 #define DWC3_MODE(n)		((n) & 0x7)
847887 
848
-#define DWC3_MDWIDTH(n)		(((n) & 0xff00) >> 8)
849
-
850888 /* HWPARAMS1 */
851889 #define DWC3_NUM_INT(n)		(((n) & (0x3f << 15)) >> 15)
890
+#define DWC3_NUM_RAMS(n)	(((n) & (0x3 << 21)) >> 21)
852891 
853892 /* HWPARAMS3 */
854893 #define DWC3_NUM_IN_EPS_MASK	(0x1f << 18)
....@@ -888,26 +927,31 @@
888927 	struct scatterlist	*sg;
889928 	struct scatterlist	*start_sg;
890929 
891
-	unsigned		num_pending_sgs;
930
+	unsigned int		num_pending_sgs;
892931 	unsigned int		num_queued_sgs;
893
-	unsigned		remaining;
932
+	unsigned int		remaining;
894933 
895934 	unsigned int		status;
896
-#define DWC3_REQUEST_STATUS_QUEUED	0
897
-#define DWC3_REQUEST_STATUS_STARTED	1
898
-#define DWC3_REQUEST_STATUS_CANCELLED	2
899
-#define DWC3_REQUEST_STATUS_COMPLETED	3
900
-#define DWC3_REQUEST_STATUS_UNKNOWN	-1
935
+#define DWC3_REQUEST_STATUS_QUEUED		0
936
+#define DWC3_REQUEST_STATUS_STARTED		1
937
+#define DWC3_REQUEST_STATUS_DISCONNECTED	2
938
+#define DWC3_REQUEST_STATUS_DEQUEUED		3
939
+#define DWC3_REQUEST_STATUS_STALLED		4
940
+#define DWC3_REQUEST_STATUS_COMPLETED		5
941
+#define DWC3_REQUEST_STATUS_UNKNOWN		-1
901942 
902943 	u8			epnum;
903944 	struct dwc3_trb		*trb;
904945 	dma_addr_t		trb_dma;
905946 
906
-	unsigned		num_trbs;
947
+	unsigned int		num_trbs;
907948 
908
-	unsigned		needs_extra_trb:1;
909
-	unsigned		direction:1;
910
-	unsigned		mapped:1;
949
+	unsigned int		needs_extra_trb:1;
950
+	unsigned int		direction:1;
951
+	unsigned int		mapped:1;
952
+
953
+	ANDROID_KABI_RESERVE(1);
954
+	ANDROID_KABI_RESERVE(2);
911955 };
912956 
913957 /*
....@@ -930,8 +974,8 @@
930974  * @ep0_usb_req: dummy req used while handling STD USB requests
931975  * @scratch_addr: dma address of scratchbuf
932976  * @ep0_in_setup: one control transfer is completed and enter setup phase
933
- * @discon_done: disconnect event is completed
934977  * @lock: for synchronizing
978
+ * @mutex: for mode switching
935979  * @dev: pointer to our struct device
936980  * @sysdev: pointer to the DMA-capable device
937981  * @xhci: pointer to our xHCI child
....@@ -954,7 +998,12 @@
954998  * @nr_scratch: number of scratch buffers
955999  * @u1u2: only used on revisions <1.83a for workaround
9561000  * @maximum_speed: maximum speed requested (mainly for testing purposes)
957
- * @revision: revision register contents
1001
+ * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count
1002
+ * @gadget_max_speed: maximum gadget speed requested
1003
+ * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling
1004
+ *			rate and lane count.
1005
+ * @ip: controller's ID
1006
+ * @revision: controller's version of an IP
9581007  * @version_type: VERSIONTYPE register contents, a sub release of a revision
9591008  * @dr_mode: requested mode of operation
9601009  * @current_dr_role: current role of operation when in dual-role mode
....@@ -964,6 +1013,12 @@
9641013  * @hsphy_mode: UTMI phy mode, one of following:
9651014  *		- USBPHY_INTERFACE_MODE_UTMI
9661015  *		- USBPHY_INTERFACE_MODE_UTMIW
1016
+ * @role_sw: usb_role_switch handle
1017
+ * @role_switch_default_mode: default operation mode of controller while
1018
+ *			usb role is USB_ROLE_NONE.
1019
+ * @current_role_sw_mode: current usb role switch mode.
1020
+ * @desired_role_sw_mode: desired usb role switch mode.
1021
+ * @usb_psy: pointer to power supply interface.
9671022  * @usb2_phy: pointer to USB2 PHY
9681023  * @usb3_phy: pointer to USB3 PHY
9691024  * @usb2_generic_phy: pointer to USB2 PHY
....@@ -992,6 +1047,7 @@
9921047  * @rx_max_burst_prd: max periodic ESS receive burst size
9931048  * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
9941049  * @tx_max_burst_prd: max periodic ESS transmit burst size
1050
+ * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
9951051  * @hsphy_interface: "utmi" or "ulpi"
9961052  * @connected: true when we're connected to a host, false otherwise
9971053  * @delayed_status: true when gadget driver asks for delayed status
....@@ -1002,17 +1058,19 @@
10021058  * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
10031059  *			there's now way for software to detect this in runtime.
10041060  * @is_utmi_l1_suspend: the core asserts output signal
1005
- * 	0	- utmi_sleep_n
1006
- * 	1	- utmi_l1_suspend_n
1061
+ *	0	- utmi_sleep_n
1062
+ *	1	- utmi_l1_suspend_n
10071063  * @is_fpga: true when we are using the FPGA board
10081064  * @pending_events: true when we have pending IRQs to be handled
1065
+ * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
10091066  * @pullups_connected: true when Run/Stop bit is set
10101067  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
10111068  * @three_stage_setup: set if we perform a three phase setup
10121069  * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
10131070  *			not needed for DWC_usb31 version 1.70a-ea06 and below
10141071  * @usb3_lpm_capable: set if hadrware supports Link Power Management
1015
- * @usb2_lpm_disable: set to disable usb2 lpm
1072
+ * @usb2_lpm_disable: set to disable usb2 lpm for host
1073
+ * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget
10161074  * @disable_scramble_quirk: set if we enable the disable scramble quirk
10171075  * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
10181076  * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
....@@ -1023,9 +1081,10 @@
10231081  * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
10241082  * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
10251083  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1026
- * @dis_u1u2_quirk: set if we reject transition to U1 or U2 state
10271084  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
10281085  *                      disabling the suspend signal to the PHY.
1086
+ * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1087
+ * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
10291088  * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
10301089  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
10311090  *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
....@@ -1036,31 +1095,21 @@
10361095  *			check during HS transmit.
10371096  * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
10381097  *			instances in park mode.
1039
- * @xhci_slow_suspend_quirk: set if need an extraordinary delay to wait
1040
- *			for xHC enter the Halted state after the Run/Stop
1041
- *			(R/S) bit is cleared to '0'.
1042
- * @xhci_trb_ent_quirk: set if need to enable the Evaluate Next TRB(ENT)
1043
-			flag in the TRB data structure to force xHC to
1044
-			pre-fetch the next TRB of a TD.
1045
- * @xhci_warm_reset_on_suspend_quirk: set if need to do a warm port reset
1046
- *			for xHC USB3 port upon suspend.
1047
- * @dis_u3_autosuspend_quirk: set if the we want to disable usb3 autosuspend
10481098  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
10491099  * @tx_de_emphasis: Tx de-emphasis value
1050
- * 	0	- -6dB de-emphasis
1051
- * 	1	- -3.5dB de-emphasis
1052
- * 	2	- No de-emphasis
1053
- * 	3	- Reserved
1100
+ *	0	- -6dB de-emphasis
1101
+ *	1	- -3.5dB de-emphasis
1102
+ *	2	- No de-emphasis
1103
+ *	3	- Reserved
10541104  * @dis_metastability_quirk: set to disable metastability quirk.
1055
- * @needs_fifo_resize: set if we want to resize TXFIFO.
1056
- * @fifo_resize_status: true if the TXFIFOs have been resized.
1057
- * @drd_connected: true when usb connected to a host or a device(drd mode),
1058
- *			false otherwise.
1059
- * @en_runtime: true when need runtime PM management. For example, RK3399 need
1060
- *			reset dwc3 and usb3phy to support typec interface.
1061
- * @uwk_en: true when enable usb wakeup from host resume signal.
1105
+ * @dis_split_quirk: set to disable split boundary.
10621106  * @imod_interval: set the interrupt moderation interval in 250ns
1063
- *                 increments or 0 to disable.
1107
+ *			increments or 0 to disable.
1108
+ * @max_cfg_eps: current max number of IN eps used across all USB configs.
1109
+ * @last_fifo_depth: last fifo depth used to determine next fifo ram start
1110
+ *		     address.
1111
+ * @num_ep_resized: carries the current number endpoints which have had its tx
1112
+ *		    fifo resized.
10641113  */
10651114 struct dwc3 {
10661115 	struct work_struct	drd_work;
....@@ -1073,10 +1122,12 @@
10731122 	dma_addr_t		scratch_addr;
10741123 	struct dwc3_request	ep0_usb_req;
10751124 	struct completion	ep0_in_setup;
1076
-	struct completion	discon_done;
10771125 
10781126 	/* device lock */
10791127 	spinlock_t		lock;
1128
+
1129
+	/* mode switching lock */
1130
+	struct mutex		mutex;
10801131 
10811132 	struct device		*dev;
10821133 	struct device		*sysdev;
....@@ -1087,7 +1138,7 @@
10871138 	struct dwc3_event_buffer *ev_buf;
10881139 	struct dwc3_ep		*eps[DWC3_ENDPOINTS_NUM];
10891140 
1090
-	struct usb_gadget	gadget;
1141
+	struct usb_gadget	*gadget;
10911142 	struct usb_gadget_driver *gadget_driver;
10921143 
10931144 	struct clk_bulk_data	*clks;
....@@ -1115,6 +1166,14 @@
11151166 	struct extcon_dev	*edev;
11161167 	struct notifier_block	edev_nb;
11171168 	enum usb_phy_interface	hsphy_mode;
1169
+	struct usb_role_switch	*role_sw;
1170
+	enum usb_dr_mode	role_switch_default_mode;
1171
+#if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
1172
+	u32			current_role_sw_mode;
1173
+	u32			desired_role_sw_mode;
1174
+#endif
1175
+
1176
+	struct power_supply	*usb_psy;
11181177 
11191178 	u32			fladj;
11201179 	u32			irq_gadget;
....@@ -1125,16 +1184,19 @@
11251184 	u32			nr_scratch;
11261185 	u32			u1u2;
11271186 	u32			maximum_speed;
1187
+	u32			gadget_max_speed;
1188
+	enum usb_ssp_rate	max_ssp_rate;
1189
+	enum usb_ssp_rate	gadget_ssp_rate;
11281190 
1129
-	/*
1130
-	 * All 3.1 IP version constants are greater than the 3.0 IP
1131
-	 * version constants. This works for most version checks in
1132
-	 * dwc3. However, in the future, this may not apply as
1133
-	 * features may be developed on newer versions of the 3.0 IP
1134
-	 * that are not in the 3.1 IP.
1135
-	 */
1191
+	u32			ip;
1192
+
1193
+#define DWC3_IP			0x5533
1194
+#define DWC31_IP		0x3331
1195
+#define DWC32_IP		0x3332
1196
+
11361197 	u32			revision;
11371198 
1199
+#define DWC3_REVISION_ANY	0x0
11381200 #define DWC3_REVISION_173A	0x5533173a
11391201 #define DWC3_REVISION_175A	0x5533175a
11401202 #define DWC3_REVISION_180A	0x5533180a
....@@ -1159,18 +1221,20 @@
11591221 #define DWC3_REVISION_310A	0x5533310a
11601222 #define DWC3_REVISION_330A	0x5533330a
11611223 
1162
-/*
1163
- * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
1164
- * just so dwc31 revisions are always larger than dwc3.
1165
- */
1166
-#define DWC3_REVISION_IS_DWC31		0x80000000
1167
-#define DWC3_USB31_REVISION_110A	(0x3131302a | DWC3_REVISION_IS_DWC31)
1168
-#define DWC3_USB31_REVISION_120A	(0x3132302a | DWC3_REVISION_IS_DWC31)
1169
-#define DWC3_USB31_REVISION_160A	(0x3136302a | DWC3_REVISION_IS_DWC31)
1170
-#define DWC3_USB31_REVISION_170A	(0x3137302a | DWC3_REVISION_IS_DWC31)
1224
+#define DWC31_REVISION_ANY	0x0
1225
+#define DWC31_REVISION_110A	0x3131302a
1226
+#define DWC31_REVISION_120A	0x3132302a
1227
+#define DWC31_REVISION_160A	0x3136302a
1228
+#define DWC31_REVISION_170A	0x3137302a
1229
+#define DWC31_REVISION_180A	0x3138302a
1230
+#define DWC31_REVISION_190A	0x3139302a
1231
+
1232
+#define DWC32_REVISION_ANY	0x0
1233
+#define DWC32_REVISION_100A	0x3130302a
11711234 
11721235 	u32			version_type;
11731236 
1237
+#define DWC31_VERSIONTYPE_ANY		0x0
11741238 #define DWC31_VERSIONTYPE_EA01		0x65613031
11751239 #define DWC31_VERSIONTYPE_EA02		0x65613032
11761240 #define DWC31_VERSIONTYPE_EA03		0x65613033
....@@ -1205,6 +1269,7 @@
12051269 	u8			rx_max_burst_prd;
12061270 	u8			tx_thr_num_pkt_prd;
12071271 	u8			tx_max_burst_prd;
1272
+	u8			tx_fifo_resize_max_num;
12081273 
12091274 	const char		*hsphy_interface;
12101275 
....@@ -1218,12 +1283,14 @@
12181283 	unsigned		is_utmi_l1_suspend:1;
12191284 	unsigned		is_fpga:1;
12201285 	unsigned		pending_events:1;
1286
+	unsigned		do_fifo_resize:1;
12211287 	unsigned		pullups_connected:1;
12221288 	unsigned		setup_packet_pending:1;
12231289 	unsigned		three_stage_setup:1;
12241290 	unsigned		dis_start_transfer_quirk:1;
12251291 	unsigned		usb3_lpm_capable:1;
12261292 	unsigned		usb2_lpm_disable:1;
1293
+	unsigned		usb2_gadget_lpm_disable:1;
12271294 
12281295 	unsigned		disable_scramble_quirk:1;
12291296 	unsigned		u2exit_lfps_quirk:1;
....@@ -1235,29 +1302,45 @@
12351302 	unsigned		rx_detect_poll_quirk:1;
12361303 	unsigned		dis_u3_susphy_quirk:1;
12371304 	unsigned		dis_u2_susphy_quirk:1;
1238
-	unsigned		dis_u1u2_quirk:1;
12391305 	unsigned		dis_enblslpm_quirk:1;
1306
+	unsigned		dis_u1_entry_quirk:1;
1307
+	unsigned		dis_u2_entry_quirk:1;
12401308 	unsigned		dis_rxdet_inp3_quirk:1;
12411309 	unsigned		dis_u2_freeclk_exists_quirk:1;
12421310 	unsigned		dis_del_phy_power_chg_quirk:1;
12431311 	unsigned		dis_tx_ipgap_linecheck_quirk:1;
12441312 	unsigned		parkmode_disable_ss_quirk:1;
1245
-	unsigned		xhci_slow_suspend_quirk:1;
1246
-	unsigned		xhci_trb_ent_quirk:1;
1247
-	unsigned		xhci_warm_reset_on_suspend_quirk:1;
1248
-	unsigned		dis_u3_autosuspend_quirk:1;
12491313 
12501314 	unsigned		tx_de_emphasis_quirk:1;
12511315 	unsigned		tx_de_emphasis:2;
12521316 
12531317 	unsigned		dis_metastability_quirk:1;
1254
-	unsigned		needs_fifo_resize:1;
1255
-	unsigned		fifo_resize_status:1;
1256
-	unsigned		drd_connected:1;
1257
-	unsigned		en_runtime:1;
1258
-	unsigned		uwk_en:1;
1318
+
1319
+	unsigned		dis_split_quirk:1;
1320
+	unsigned		async_callbacks:1;
12591321 
12601322 	u16			imod_interval;
1323
+
1324
+	int			max_cfg_eps;
1325
+	int			last_fifo_depth;
1326
+	int			num_ep_resized;
1327
+
1328
+	ANDROID_KABI_RESERVE(1);
1329
+	ANDROID_KABI_RESERVE(2);
1330
+	ANDROID_KABI_RESERVE(3);
1331
+	ANDROID_KABI_RESERVE(4);
1332
+};
1333
+
1334
+/**
1335
+ * struct dwc3_vendor - contains parameters without modifying the format of DWC3 core
1336
+ * @dwc: contains dwc3 core reference
1337
+ * @clear_stall_protocol: endpoint number that requires a delayed status phase
1338
+ * @softconnect: true when gadget connect is called, false when disconnect runs
1339
+ */
1340
+struct dwc3_vendor {
1341
+	struct dwc3	dwc;
1342
+	u8		clear_stall_protocol;
1343
+	unsigned	softconnect:1;
12611344 };
12621345 
12631346 #define INCRX_BURST_MODE 0
....@@ -1281,7 +1364,7 @@
12811364 #define DWC3_DEPEVT_EPCMDCMPLT		0x07
12821365 
12831366 /**
1284
- * struct dwc3_event_depvt - Device Endpoint Events
1367
+ * struct dwc3_event_depevt - Device Endpoint Events
12851368  * @one_bit: indicates this is an endpoint event (not used)
12861369  * @endpoint_number: number of the endpoint
12871370  * @endpoint_event: The event we have:
....@@ -1320,6 +1403,10 @@
13201403 #define DEPEVT_STREAMEVT_FOUND		1
13211404 #define DEPEVT_STREAMEVT_NOTFOUND	2
13221405 
1406
+/* Stream event parameter */
1407
+#define DEPEVT_STREAM_PRIME		0xfffe
1408
+#define DEPEVT_STREAM_NOSTREAM		0x0
1409
+
13231410 /* Control-only Status */
13241411 #define DEPEVT_STATUS_CONTROL_DATA	1
13251412 #define DEPEVT_STATUS_CONTROL_STATUS	2
....@@ -1346,7 +1433,7 @@
13461433  *	3	- ULStChng
13471434  *	4	- WkUpEvt
13481435  *	5	- Reserved
1349
- *	6	- EOPF
1436
+ *	6	- Suspend (EOPF on revisions 2.10a and prior)
13501437  *	7	- SOF
13511438  *	8	- Reserved
13521439  *	9	- ErrticErr
....@@ -1422,22 +1509,50 @@
14221509 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
14231510 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
14241511 
1425
-/* check whether we are on the DWC_usb3 core */
1426
-static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1427
-{
1428
-	return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1429
-}
1512
+#define DWC3_IP_IS(_ip)							\
1513
+	(dwc->ip == _ip##_IP)
14301514 
1431
-/* check whether we are on the DWC_usb31 core */
1432
-static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1515
+#define DWC3_VER_IS(_ip, _ver)						\
1516
+	(DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1517
+
1518
+#define DWC3_VER_IS_PRIOR(_ip, _ver)					\
1519
+	(DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1520
+
1521
+#define DWC3_VER_IS_WITHIN(_ip, _from, _to)				\
1522
+	(DWC3_IP_IS(_ip) &&						\
1523
+	 dwc->revision >= _ip##_REVISION_##_from &&			\
1524
+	 (!(_ip##_REVISION_##_to) ||					\
1525
+	  dwc->revision <= _ip##_REVISION_##_to))
1526
+
1527
+#define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to)			\
1528
+	(DWC3_VER_IS(_ip, _ver) &&					\
1529
+	 dwc->version_type >= _ip##_VERSIONTYPE_##_from &&		\
1530
+	 (!(_ip##_VERSIONTYPE_##_to) ||					\
1531
+	  dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1532
+
1533
+/**
1534
+ * dwc3_mdwidth - get MDWIDTH value in bits
1535
+ * @dwc: pointer to our context structure
1536
+ *
1537
+ * Return MDWIDTH configuration value in bits.
1538
+ */
1539
+static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
14331540 {
1434
-	return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1541
+	u32 mdwidth;
1542
+
1543
+	mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1544
+	if (DWC3_IP_IS(DWC32))
1545
+		mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1546
+
1547
+	return mdwidth;
14351548 }
14361549 
14371550 bool dwc3_has_imod(struct dwc3 *dwc);
14381551 
14391552 int dwc3_event_buffers_setup(struct dwc3 *dwc);
14401553 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1554
+
1555
+int dwc3_core_soft_reset(struct dwc3 *dwc);
14411556 
14421557 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
14431558 int dwc3_host_init(struct dwc3 *dwc);
....@@ -1455,11 +1570,13 @@
14551570 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
14561571 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
14571572 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1458
-int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1573
+int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
14591574 		struct dwc3_gadget_ep_cmd_params *params);
1460
-int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1461
-void dwc3_gadget_disable_irq(struct dwc3 *dwc);
1462
-void dwc3_gadget_enable_irq(struct dwc3 *dwc);
1575
+int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1576
+		u32 param);
1577
+void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt);
1578
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1579
+void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status);
14631580 #else
14641581 static inline int dwc3_gadget_init(struct dwc3 *dwc)
14651582 { return 0; }
....@@ -1473,15 +1590,16 @@
14731590 		enum dwc3_link_state state)
14741591 { return 0; }
14751592 
1476
-static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1593
+static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
14771594 		struct dwc3_gadget_ep_cmd_params *params)
14781595 { return 0; }
14791596 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
14801597 		int cmd, u32 param)
14811598 { return 0; }
1482
-static inline void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1599
+static inline void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
1600
+					     bool interrupt)
14831601 { }
1484
-static inline void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1602
+static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
14851603 { }
14861604 #endif
14871605