add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/usb/dwc2/hw.h
..
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@@ -1,4 +1,4 @@
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-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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 /*
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  * hw.h - DesignWare HS OTG Controller hardware definitions
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  *
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@@ -54,6 +54,12 @@
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 #define GOTGCTL_HSTSETHNPEN		BIT(10)
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 #define GOTGCTL_HNPREQ			BIT(9)
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 #define GOTGCTL_HSTNEGSCS		BIT(8)
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+#define GOTGCTL_BVALOVAL		BIT(7)
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+#define GOTGCTL_BVALOEN			BIT(6)
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+#define GOTGCTL_AVALOVAL		BIT(5)
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+#define GOTGCTL_AVALOEN			BIT(4)
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+#define GOTGCTL_VBVALOVAL		BIT(3)
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+#define GOTGCTL_VBVALOEN		BIT(2)
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 #define GOTGCTL_SESREQ			BIT(1)
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 #define GOTGCTL_SESREQSCS		BIT(0)
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@@ -120,6 +126,7 @@
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 #define GRSTCTL				HSOTG_REG(0x010)
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 #define GRSTCTL_AHBIDLE			BIT(31)
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 #define GRSTCTL_DMAREQ			BIT(30)
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+#define GRSTCTL_CSFTRST_DONE		BIT(29)
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 #define GRSTCTL_TXFNUM_MASK		(0x1f << 6)
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 #define GRSTCTL_TXFNUM_SHIFT		6
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 #define GRSTCTL_TXFNUM_LIMIT		0x1f
..
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@@ -227,6 +234,8 @@
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 #define GPVNDCTL			HSOTG_REG(0x0034)
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 #define GGPIO				HSOTG_REG(0x0038)
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 #define GGPIO_STM32_OTG_GCCFG_PWRDWN	BIT(16)
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+#define GGPIO_STM32_OTG_GCCFG_VBDEN	BIT(21)
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+#define GGPIO_STM32_OTG_GCCFG_IDEN	BIT(22)
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 #define GUID				HSOTG_REG(0x003c)
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 #define GSNPSID				HSOTG_REG(0x0040)
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@@ -310,11 +319,12 @@
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 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT	16
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 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK	(0x3 << 14)
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 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT	14
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-#define GHWCFG4_ACG_SUPPORTED			BIT(12)
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-#define GHWCFG4_IPG_ISOC_SUPPORTED		BIT(11)
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 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8		0
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 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16		1
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 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16	2
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+#define GHWCFG4_ACG_SUPPORTED			BIT(12)
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+#define GHWCFG4_IPG_ISOC_SUPPORTED		BIT(11)
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+#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
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 #define GHWCFG4_XHIBER				BIT(7)
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 #define GHWCFG4_HIBER				BIT(6)
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 #define GHWCFG4_MIN_AHB_FREQ			BIT(5)
..
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@@ -332,6 +342,8 @@
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 #define GLPMCFG_SNDLPM			BIT(24)
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 #define GLPMCFG_RETRY_CNT_MASK		(0x7 << 21)
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 #define GLPMCFG_RETRY_CNT_SHIFT		21
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+#define GLPMCFG_LPM_REJECT_CTRL_CONTROL	BIT(21)
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+#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC	BIT(22)
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 #define GLPMCFG_LPM_CHNL_INDX_MASK	(0xf << 17)
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 #define GLPMCFG_LPM_CHNL_INDX_SHIFT	17
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 #define GLPMCFG_L1RESUMEOK		BIT(16)
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@@ -404,6 +416,19 @@
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 #define ADPCTL_PRB_DSCHRG_MASK		(0x3 << 0)
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 #define ADPCTL_PRB_DSCHRG_SHIFT		0
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+#define GREFCLK				    HSOTG_REG(0x0064)
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+#define GREFCLK_REFCLKPER_MASK		    (0x1ffff << 15)
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+#define GREFCLK_REFCLKPER_SHIFT		    15
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+#define GREFCLK_REF_CLK_MODE		    BIT(14)
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+#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK	    (0x3ff)
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+#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT    0
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+
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+#define GINTMSK2			HSOTG_REG(0x0068)
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+#define GINTMSK2_WKUP_ALERT_INT_MSK	BIT(0)
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+
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+#define GINTSTS2			HSOTG_REG(0x006c)
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+#define GINTSTS2_WKUP_ALERT_INT		BIT(0)
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+
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 #define HPTXFSIZ			HSOTG_REG(0x100)
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 /* Use FIFOSIZE_* constants to access this register */
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@@ -443,6 +468,7 @@
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 #define DCFG_DEVSPD_FS48		3
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 #define DCTL				HSOTG_REG(0x804)
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+#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
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 #define DCTL_PWRONPRGDONE		BIT(11)
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 #define DCTL_CGOUTNAK			BIT(10)
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 #define DCTL_SGOUTNAK			BIT(9)