forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/usb/dwc2/gadget.c
....@@ -28,6 +28,8 @@
2828 #include <linux/usb/ch9.h>
2929 #include <linux/usb/gadget.h>
3030 #include <linux/usb/phy.h>
31
+#include <linux/usb/composite.h>
32
+
3133 
3234 #include "core.h"
3335 #include "hw.h"
....@@ -148,6 +150,30 @@
148150 }
149151 
150152 /**
153
+ * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
154
+ *                                    by one.
155
+ * @hs_ep: The endpoint.
156
+ *
157
+ * This function used in service interval based scheduling flow to calculate
158
+ * descriptor frame number filed value. For service interval mode frame
159
+ * number in descriptor should point to last (u)frame in the interval.
160
+ *
161
+ */
162
+static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
163
+{
164
+	struct dwc2_hsotg *hsotg = hs_ep->parent;
165
+	u16 limit = DSTS_SOFFN_LIMIT;
166
+
167
+	if (hsotg->gadget.speed != USB_SPEED_HIGH)
168
+		limit >>= 3;
169
+
170
+	if (hs_ep->target_frame)
171
+		hs_ep->target_frame -= 1;
172
+	else
173
+		hs_ep->target_frame = limit;
174
+}
175
+
176
+/**
151177  * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
152178  * @hsotg: The device state
153179  * @ints: A bitmask of the interrupts to enable
....@@ -250,6 +276,28 @@
250276 		return 0;
251277 
252278 	return tx_addr_max - addr;
279
+}
280
+
281
+/**
282
+ * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
283
+ *
284
+ * @hsotg: Programming view of the DWC_otg controller
285
+ *
286
+ */
287
+static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
288
+{
289
+	u32 gintsts2;
290
+	u32 gintmsk2;
291
+
292
+	gintsts2 = dwc2_readl(hsotg, GINTSTS2);
293
+	gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
294
+	gintsts2 &= gintmsk2;
295
+
296
+	if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
297
+		dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
298
+		dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
299
+		dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
300
+	}
253301 }
254302 
255303 /**
....@@ -753,22 +801,13 @@
753801 	return desc_size;
754802 }
755803 
756
-/*
757
- * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
758
- * @hs_ep: The endpoint
759
- * @dma_buff: DMA address to use
760
- * @len: Length of the transfer
761
- *
762
- * This function will iterate over descriptor chain and fill its entries
763
- * with corresponding information based on transfer data.
764
- */
765
-static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
804
+static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
805
+						 struct dwc2_dma_desc **desc,
766806 						 dma_addr_t dma_buff,
767
-						 unsigned int len)
807
+						 unsigned int len,
808
+						 bool true_last)
768809 {
769
-	struct dwc2_hsotg *hsotg = hs_ep->parent;
770810 	int dir_in = hs_ep->dir_in;
771
-	struct dwc2_dma_desc *desc = hs_ep->desc_list;
772811 	u32 mps = hs_ep->ep.maxpacket;
773812 	u32 maxsize = 0;
774813 	u32 offset = 0;
....@@ -783,39 +822,80 @@
783822 		hs_ep->desc_count = 1;
784823 
785824 	for (i = 0; i < hs_ep->desc_count; ++i) {
786
-		desc->status = 0;
787
-		desc->status |= (DEV_DMA_BUFF_STS_HBUSY
825
+		(*desc)->status = 0;
826
+		(*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
788827 				 << DEV_DMA_BUFF_STS_SHIFT);
789828 
790829 		if (len > maxsize) {
791830 			if (!hs_ep->index && !dir_in)
792
-				desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
831
+				(*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
793832 
794
-			desc->status |= (maxsize <<
795
-						DEV_DMA_NBYTES_SHIFT & mask);
796
-			desc->buf = dma_buff + offset;
833
+			(*desc)->status |=
834
+				maxsize << DEV_DMA_NBYTES_SHIFT & mask;
835
+			(*desc)->buf = dma_buff + offset;
797836 
798837 			len -= maxsize;
799838 			offset += maxsize;
800839 		} else {
801
-			desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
840
+			if (true_last)
841
+				(*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
802842 
803843 			if (dir_in)
804
-				desc->status |= (len % mps) ? DEV_DMA_SHORT :
805
-					((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
806
-			if (len > maxsize)
807
-				dev_err(hsotg->dev, "wrong len %d\n", len);
844
+				(*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
845
+					((hs_ep->send_zlp && true_last) ?
846
+					DEV_DMA_SHORT : 0);
808847 
809
-			desc->status |=
848
+			(*desc)->status |=
810849 				len << DEV_DMA_NBYTES_SHIFT & mask;
811
-			desc->buf = dma_buff + offset;
850
+			(*desc)->buf = dma_buff + offset;
812851 		}
813852 
814
-		desc->status &= ~DEV_DMA_BUFF_STS_MASK;
815
-		desc->status |= (DEV_DMA_BUFF_STS_HREADY
853
+		(*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
854
+		(*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
816855 				 << DEV_DMA_BUFF_STS_SHIFT);
817
-		desc++;
856
+		(*desc)++;
818857 	}
858
+}
859
+
860
+/*
861
+ * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
862
+ * @hs_ep: The endpoint
863
+ * @ureq: Request to transfer
864
+ * @offset: offset in bytes
865
+ * @len: Length of the transfer
866
+ *
867
+ * This function will iterate over descriptor chain and fill its entries
868
+ * with corresponding information based on transfer data.
869
+ */
870
+static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
871
+						 dma_addr_t dma_buff,
872
+						 unsigned int len)
873
+{
874
+	struct usb_request *ureq = NULL;
875
+	struct dwc2_dma_desc *desc = hs_ep->desc_list;
876
+	struct scatterlist *sg;
877
+	int i;
878
+	u8 desc_count = 0;
879
+
880
+	if (hs_ep->req)
881
+		ureq = &hs_ep->req->req;
882
+
883
+	/* non-DMA sg buffer */
884
+	if (!ureq || !ureq->num_sgs) {
885
+		dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
886
+			dma_buff, len, true);
887
+		return;
888
+	}
889
+
890
+	/* DMA sg buffer */
891
+	for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
892
+		dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
893
+			sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
894
+			sg_is_last(sg));
895
+		desc_count += hs_ep->desc_count;
896
+	}
897
+
898
+	hs_ep->desc_count = desc_count;
819899 }
820900 
821901 /*
....@@ -835,11 +915,10 @@
835915 	struct dwc2_dma_desc *desc;
836916 	struct dwc2_hsotg *hsotg = hs_ep->parent;
837917 	u32 index;
838
-	u32 maxsize = 0;
839918 	u32 mask = 0;
840919 	u8 pid = 0;
841920 
842
-	maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
921
+	dwc2_gadget_get_desc_params(hs_ep, &mask);
843922 
844923 	index = hs_ep->next_desc;
845924 	desc = &hs_ep->desc_list[index];
....@@ -929,7 +1008,13 @@
9291008 
9301009 	hs_ep->next_desc = 0;
9311010 	list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
932
-		ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1011
+		dma_addr_t dma_addr = hs_req->req.dma;
1012
+
1013
+		if (hs_req->req.num_sgs) {
1014
+			WARN_ON(hs_req->req.num_sgs > 1);
1015
+			dma_addr = sg_dma_address(hs_req->req.sg);
1016
+		}
1017
+		ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
9331018 						 hs_req->req.length);
9341019 		if (ret)
9351020 			break;
....@@ -1400,11 +1485,22 @@
14001485 	 */
14011486 	if (using_desc_dma(hs) && hs_ep->isochronous) {
14021487 		if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1403
-			dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1488
+			dma_addr_t dma_addr = hs_req->req.dma;
1489
+
1490
+			if (hs_req->req.num_sgs) {
1491
+				WARN_ON(hs_req->req.num_sgs > 1);
1492
+				dma_addr = sg_dma_address(hs_req->req.sg);
1493
+			}
1494
+			dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
14041495 						   hs_req->req.length);
14051496 		}
14061497 		return 0;
14071498 	}
1499
+
1500
+	/* Change EP direction if status phase request is after data out */
1501
+	if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1502
+	    hs->ep0_state == DWC2_EP0_DATA_OUT)
1503
+		hs_ep->dir_in = 1;
14081504 
14091505 	if (first) {
14101506 		if (!hs_ep->isochronous) {
....@@ -1519,11 +1615,11 @@
15191615 
15201616 	dctl &= ~DCTL_TSTCTL_MASK;
15211617 	switch (testmode) {
1522
-	case TEST_J:
1523
-	case TEST_K:
1524
-	case TEST_SE0_NAK:
1525
-	case TEST_PACKET:
1526
-	case TEST_FORCE_EN:
1618
+	case USB_TEST_J:
1619
+	case USB_TEST_K:
1620
+	case USB_TEST_SE0_NAK:
1621
+	case USB_TEST_PACKET:
1622
+	case USB_TEST_FORCE_ENABLE:
15271623 		dctl |= testmode << DCTL_TSTCTL_SHIFT;
15281624 		break;
15291625 	default:
....@@ -1604,7 +1700,8 @@
16041700 
16051701 	switch (ctrl->bRequestType & USB_RECIP_MASK) {
16061702 	case USB_RECIP_DEVICE:
1607
-		status = 1 << USB_DEVICE_SELF_POWERED;
1703
+		status = hsotg->gadget.is_selfpowered <<
1704
+			 USB_DEVICE_SELF_POWERED;
16081705 		status |= hsotg->remote_wakeup_allowed <<
16091706 			  USB_DEVICE_REMOTE_WAKEUP;
16101707 		reply = cpu_to_le16(status);
....@@ -1905,6 +2002,10 @@
19052002 			dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
19062003 	}
19072004 
2005
+	hsotg->delayed_status = false;
2006
+	if (ret == USB_GADGET_DELAYED_STATUS)
2007
+		hsotg->delayed_status = true;
2008
+
19082009 	/*
19092010 	 * the request is either unhandlable, or is not formatted correctly
19102011 	 * so respond with a STALL for the status stage to indicate failure.
....@@ -2125,6 +2226,11 @@
21252226 			 */
21262227 			if (!hs_ep->dir_in && ureq->length & 0x3)
21272228 				ureq->actual += 4 - (ureq->length & 0x3);
2229
+
2230
+			/* Set actual frame number for completed transfers */
2231
+			ureq->frame_number =
2232
+				(desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2233
+				DEV_DMA_ISOC_FRNUM_SHIFT;
21282234 		}
21292235 
21302236 		dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
....@@ -2357,8 +2463,8 @@
23572463 	if (!using_desc_dma(hsotg) && epnum == 0 &&
23582464 	    hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
23592465 		/* Move to STATUS IN */
2360
-		dwc2_hsotg_ep0_zlp(hsotg, true);
2361
-		return;
2466
+		if (!hsotg->delayed_status)
2467
+			dwc2_hsotg_ep0_zlp(hsotg, true);
23622468 	}
23632469 
23642470 	/* Set actual frame number for completed transfers */
....@@ -2876,6 +2982,23 @@
28762982 		if (using_desc_dma(hsotg)) {
28772983 			hs_ep->target_frame = hsotg->frame_number;
28782984 			dwc2_gadget_incr_frame_num(hs_ep);
2985
+
2986
+			/* In service interval mode target_frame must
2987
+			 * be set to last (u)frame of the service interval.
2988
+			 */
2989
+			if (hsotg->params.service_interval) {
2990
+				/* Set target_frame to the first (u)frame of
2991
+				 * the service interval
2992
+				 */
2993
+				hs_ep->target_frame &= ~hs_ep->interval + 1;
2994
+
2995
+				/* Set target_frame to the last (u)frame of
2996
+				 * the service interval
2997
+				 */
2998
+				dwc2_gadget_incr_frame_num(hs_ep);
2999
+				dwc2_gadget_dec_frame_num_by_one(hs_ep);
3000
+			}
3001
+
28793002 			dwc2_gadget_start_isoc_ddma(hs_ep);
28803003 			return;
28813004 		}
....@@ -2952,10 +3075,8 @@
29523075 	u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
29533076 	u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
29543077 	u32 ints;
2955
-	u32 ctrl;
29563078 
29573079 	ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2958
-	ctrl = dwc2_readl(hsotg, epctl_reg);
29593080 
29603081 	/* Clear endpoint interrupts */
29613082 	dwc2_writel(hsotg, ints, epint_reg);
....@@ -3049,8 +3170,20 @@
30493170 		/* Safety check EP0 state when STSPHSERCVD asserted */
30503171 		if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
30513172 			/* Move to STATUS IN for DDMA */
3052
-			if (using_desc_dma(hsotg))
3053
-				dwc2_hsotg_ep0_zlp(hsotg, true);
3173
+			if (using_desc_dma(hsotg)) {
3174
+				if (!hsotg->delayed_status)
3175
+					dwc2_hsotg_ep0_zlp(hsotg, true);
3176
+				else
3177
+				/* In case of 3 stage Control Write with delayed
3178
+				 * status, when Status IN transfer started
3179
+				 * before STSPHSERCVD asserted, NAKSTS bit not
3180
+				 * cleared by CNAK in dwc2_hsotg_start_req()
3181
+				 * function. Clear now NAKSTS to allow complete
3182
+				 * transfer.
3183
+				 */
3184
+					dwc2_set_bit(hsotg, DIEPCTL(0),
3185
+						     DXEPCTL_CNAK);
3186
+			}
30543187 		}
30553188 
30563189 	}
....@@ -3185,14 +3318,15 @@
31853318 			      struct dwc2_hsotg_ep *ep,
31863319 			      int result)
31873320 {
3188
-	struct dwc2_hsotg_req *req, *treq;
31893321 	unsigned int size;
31903322 
31913323 	ep->req = NULL;
31923324 
3193
-	list_for_each_entry_safe(req, treq, &ep->queue, queue)
3194
-		dwc2_hsotg_complete_request(hsotg, ep, req,
3195
-					    result);
3325
+	while (!list_empty(&ep->queue)) {
3326
+		struct dwc2_hsotg_req *req = get_ep_head(ep);
3327
+
3328
+		dwc2_hsotg_complete_request(hsotg, ep, req, result);
3329
+	}
31963330 
31973331 	if (!hsotg->dedicated_fifos)
31983332 		return;
....@@ -3310,21 +3444,14 @@
33103444 
33113445 	/* keep other bits untouched (so e.g. forced modes are not lost) */
33123446 	usbcfg = dwc2_readl(hsotg, GUSBCFG);
3313
-	usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3314
-		GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3447
+	usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3448
+	usbcfg |= GUSBCFG_TOUTCAL(7);
33153449 
3316
-	if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3317
-	    (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3318
-	     hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3319
-		/* FS/LS Dedicated Transceiver Interface */
3320
-		usbcfg |= GUSBCFG_PHYSEL;
3321
-	} else {
3322
-		/* set the PLL on, remove the HNP/SRP and set the PHY */
3323
-		val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3324
-		usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3325
-			(val << GUSBCFG_USBTRDTIM_SHIFT);
3326
-	}
3327
-	dwc2_writel(hsotg, usbcfg, GUSBCFG);
3450
+	/* remove the HNP/SRP and set the PHY */
3451
+	usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3452
+        dwc2_writel(hsotg, usbcfg, GUSBCFG);
3453
+
3454
+	dwc2_phy_init(hsotg, true);
33283455 
33293456 	dwc2_hsotg_init_fifo(hsotg);
33303457 
....@@ -3416,6 +3543,10 @@
34163543 		dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
34173544 	}
34183545 
3546
+	/* Enable Service Interval mode if supported */
3547
+	if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3548
+		dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3549
+
34193550 	dwc2_writel(hsotg, 0, DAINTMSK);
34203551 
34213552 	dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
....@@ -3472,6 +3603,10 @@
34723603 	/* configure the core to support LPM */
34733604 	dwc2_gadget_init_lpm(hsotg);
34743605 
3606
+	/* program GREFCLK register if needed */
3607
+	if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3608
+		dwc2_gadget_program_ref_clk(hsotg);
3609
+
34753610 	/* must be at-least 3ms to allow bus to see disconnect */
34763611 	mdelay(3);
34773612 
....@@ -3484,7 +3619,7 @@
34843619 		dwc2_readl(hsotg, DOEPCTL0));
34853620 }
34863621 
3487
-static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3622
+void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
34883623 {
34893624 	/* set the soft-disconnect bit */
34903625 	dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
....@@ -3493,7 +3628,8 @@
34933628 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
34943629 {
34953630 	/* remove the soft-disconnect and let's go */
3496
-	dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3631
+	if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3632
+		dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
34973633 }
34983634 
34993635 /**
....@@ -3743,14 +3879,25 @@
37433879 		for (idx = 1; idx < hsotg->num_of_eps; idx++) {
37443880 			hs_ep = hsotg->eps_out[idx];
37453881 			/* Proceed only unmasked ISOC EPs */
3746
-			if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3882
+			if (BIT(idx) & ~daintmsk)
37473883 				continue;
37483884 
37493885 			epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
37503886 
3751
-			if (epctrl & DXEPCTL_EPENA) {
3887
+			//ISOC Ep's only
3888
+			if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
37523889 				epctrl |= DXEPCTL_SNAK;
37533890 				epctrl |= DXEPCTL_EPDIS;
3891
+				dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3892
+				continue;
3893
+			}
3894
+
3895
+			//Non-ISOC EP's
3896
+			if (hs_ep->halted) {
3897
+				if (!(epctrl & DXEPCTL_EPENA))
3898
+					epctrl |= DXEPCTL_EPENA;
3899
+				epctrl |= DXEPCTL_EPDIS;
3900
+				epctrl |= DXEPCTL_STALL;
37543901 				dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
37553902 			}
37563903 		}
....@@ -3779,6 +3926,10 @@
37793926 
37803927 	if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
37813928 		goto irq_retry;
3929
+
3930
+	/* Check WKUP_ALERT interrupt*/
3931
+	if (hsotg->params.service_interval)
3932
+		dwc2_gadget_wkup_alert_handler(hsotg);
37823933 
37833934 	spin_unlock(&hsotg->lock);
37843935 
....@@ -3818,8 +3969,26 @@
38183969 					 __func__);
38193970 		}
38203971 	} else {
3972
+		/* Mask GINTSTS_GOUTNAKEFF interrupt */
3973
+		dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3974
+
38213975 		if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
38223976 			dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3977
+
3978
+		if (!using_dma(hsotg)) {
3979
+			/* Wait for GINTSTS_RXFLVL interrupt */
3980
+			if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3981
+						    GINTSTS_RXFLVL, 100)) {
3982
+				dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3983
+					 __func__);
3984
+			} else {
3985
+				/*
3986
+				 * Pop GLOBAL OUT NAK status packet from RxFIFO
3987
+				 * to assert GOUTNAKEFF interrupt
3988
+				 */
3989
+				dwc2_readl(hsotg, GRXSTSP);
3990
+			}
3991
+		}
38233992 
38243993 		/* Wait for global nak to take effect */
38253994 		if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
....@@ -4036,6 +4205,7 @@
40364205 			ret = -ENOMEM;
40374206 			goto error1;
40384207 		}
4208
+		epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
40394209 		hsotg->fifo_map |= 1 << fifo_index;
40404210 		epctrl |= DXEPCTL_TXFNUM(fifo_index);
40414211 		hs_ep->fifo_index = fifo_index;
....@@ -4266,19 +4436,23 @@
42664436 		epctl = dwc2_readl(hs, epreg);
42674437 
42684438 		if (value) {
4269
-			epctl |= DXEPCTL_STALL;
4439
+			/* Unmask GOUTNAKEFF interrupt */
4440
+			dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4441
+
4442
+			if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4443
+				dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4444
+			// STALL bit will be set in GOUTNAKEFF interrupt handler
42704445 		} else {
42714446 			epctl &= ~DXEPCTL_STALL;
42724447 			xfertype = epctl & DXEPCTL_EPTYPE_MASK;
42734448 			if (xfertype == DXEPCTL_EPTYPE_BULK ||
42744449 			    xfertype == DXEPCTL_EPTYPE_INTERRUPT)
42754450 				epctl |= DXEPCTL_SETD0PID;
4451
+			dwc2_writel(hs, epctl, epreg);
42764452 		}
4277
-		dwc2_writel(hs, epctl, epreg);
42784453 	}
42794454 
42804455 	hs_ep->halted = value;
4281
-
42824456 	return 0;
42834457 }
42844458 
....@@ -4318,8 +4492,6 @@
43184492  */
43194493 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
43204494 {
4321
-	u32 trdtim;
4322
-	u32 usbcfg;
43234495 	/* unmask subset of endpoint interrupts */
43244496 
43254497 	dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
....@@ -4342,17 +4514,6 @@
43424514 		dwc2_readl(hsotg, GNPTXFSIZ));
43434515 
43444516 	dwc2_hsotg_init_fifo(hsotg);
4345
-
4346
-	/* keep other bits untouched (so e.g. forced modes are not lost) */
4347
-	usbcfg = dwc2_readl(hsotg, GUSBCFG);
4348
-	usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4349
-		GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4350
-
4351
-	/* set the PLL on, remove the HNP/SRP and set the PHY */
4352
-	trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4353
-	usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4354
-		(trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4355
-	dwc2_writel(hsotg, usbcfg, GUSBCFG);
43564517 
43574518 	if (using_dma(hsotg))
43584519 		dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
....@@ -4393,7 +4554,6 @@
43934554 
43944555 	WARN_ON(hsotg->driver);
43954556 
4396
-	driver->driver.bus = NULL;
43974557 	hsotg->driver = driver;
43984558 	hsotg->gadget.dev.of_node = hsotg->dev->of_node;
43994559 	hsotg->gadget.speed = USB_SPEED_UNKNOWN;
....@@ -4424,6 +4584,7 @@
44244584 	hsotg->enabled = 0;
44254585 	spin_unlock_irqrestore(&hsotg->lock, flags);
44264586 
4587
+	gadget->sg_supported = using_desc_dma(hsotg);
44274588 	dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
44284589 
44294590 	return 0;
....@@ -4487,6 +4648,26 @@
44874648 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
44884649 {
44894650 	return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4651
+}
4652
+
4653
+/**
4654
+ * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4655
+ * @gadget: The usb gadget state
4656
+ * @is_selfpowered: Whether the device is self-powered
4657
+ *
4658
+ * Set if the device is self or bus powered.
4659
+ */
4660
+static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4661
+				      int is_selfpowered)
4662
+{
4663
+	struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4664
+	unsigned long flags;
4665
+
4666
+	spin_lock_irqsave(&hsotg->lock, flags);
4667
+	gadget->is_selfpowered = !!is_selfpowered;
4668
+	spin_unlock_irqrestore(&hsotg->lock, flags);
4669
+
4670
+	return 0;
44904671 }
44914672 
44924673 /**
....@@ -4580,6 +4761,7 @@
45804761 
45814762 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
45824763 	.get_frame	= dwc2_hsotg_gadget_getframe,
4764
+	.set_selfpowered	= dwc2_hsotg_set_selfpowered,
45834765 	.udc_start		= dwc2_hsotg_udc_start,
45844766 	.udc_stop		= dwc2_hsotg_udc_stop,
45854767 	.pullup                 = dwc2_hsotg_pullup,
....@@ -5069,8 +5251,33 @@
50695251 	val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
50705252 	val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
50715253 	val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5254
+	val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5255
+	val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
50725256 	dwc2_writel(hsotg, val, GLPMCFG);
50735257 	dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5258
+
5259
+	/* Unmask WKUP_ALERT Interrupt */
5260
+	if (hsotg->params.service_interval)
5261
+		dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5262
+}
5263
+
5264
+/**
5265
+ * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5266
+ *
5267
+ * @hsotg: Programming view of DWC_otg controller
5268
+ *
5269
+ */
5270
+void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5271
+{
5272
+	u32 val = 0;
5273
+
5274
+	val |= GREFCLK_REF_CLK_MODE;
5275
+	val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5276
+	val |= hsotg->params.sof_cnt_wkup_alert <<
5277
+	       GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5278
+
5279
+	dwc2_writel(hsotg, val, GREFCLK);
5280
+	dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
50745281 }
50755282 
50765283 /**