add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/thermal/tegra/tegra210-soctherm.c
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@@ -1,5 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
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+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
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  *
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  * This software is licensed under the terms of the GNU General Public
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  * License version 2, as published by the Free Software Foundation, and
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@@ -56,6 +57,7 @@
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 	.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
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 	.thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK,
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 	.thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK,
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+	.thermctl_isr_mask = THERM_IRQ_CPU_MASK,
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 	.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
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 	.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
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 	.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
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@@ -74,6 +76,7 @@
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 	.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
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 	.thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK,
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 	.thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
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+	.thermctl_isr_mask = THERM_IRQ_GPU_MASK,
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 	.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
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 	.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
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 	.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
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@@ -90,6 +93,7 @@
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 	.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
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 	.thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK,
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 	.thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK,
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+	.thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
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 	.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
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 	.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
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 	.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
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@@ -108,6 +112,7 @@
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 	.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
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 	.thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK,
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 	.thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
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+	.thermctl_isr_mask = THERM_IRQ_MEM_MASK,
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 	.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
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 	.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
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 	.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
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@@ -203,6 +208,13 @@
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 	.fuse_spare_realignment = 0,
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 };
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+static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = {
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+	{.id = TEGRA124_SOCTHERM_SENSOR_NUM},
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+	{.id = TEGRA124_SOCTHERM_SENSOR_NUM},
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+	{.id = TEGRA124_SOCTHERM_SENSOR_NUM},
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+	{.id = TEGRA124_SOCTHERM_SENSOR_NUM},
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+};
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+
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 const struct tegra_soctherm_soc tegra210_soctherm = {
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 	.tsensors = tegra210_tsensors,
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 	.num_tsensors = ARRAY_SIZE(tegra210_tsensors),
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@@ -212,4 +224,5 @@
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 	.thresh_grain = TEGRA210_THRESH_GRAIN,
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 	.bptt = TEGRA210_BPTT,
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 	.use_ccroc = false,
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+	.thermtrips = tegra210_tsensor_thermtrips,
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 };