add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/thermal/tegra/soctherm.h
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
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  *
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@@ -28,6 +29,14 @@
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 #define THERMCTL_THERMTRIP_CTL			0x80
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 /* BITs are defined in device file */
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+
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+#define THERMCTL_INTR_ENABLE			0x88
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+#define THERMCTL_INTR_DISABLE			0x8c
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+#define TH_INTR_UP_DN_EN			0x3
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+#define THERM_IRQ_MEM_MASK			(TH_INTR_UP_DN_EN << 24)
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+#define THERM_IRQ_GPU_MASK			(TH_INTR_UP_DN_EN << 16)
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+#define THERM_IRQ_CPU_MASK			(TH_INTR_UP_DN_EN << 8)
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+#define THERM_IRQ_TSENSE_MASK			(TH_INTR_UP_DN_EN << 0)
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 #define SENSOR_PDIV				0x1c0
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 #define SENSOR_PDIV_CPU_MASK			(0xf << 12)
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@@ -70,6 +79,7 @@
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 	u32 thermtrip_enable_mask;
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 	u32 thermtrip_any_en_mask;
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 	u32 thermtrip_threshold_mask;
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+	u32 thermctl_isr_mask;
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 	u16 thermctl_lvl0_offset;
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 	u32 thermctl_lvl0_up_thresh_mask;
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 	u32 thermctl_lvl0_dn_thresh_mask;
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@@ -90,6 +100,11 @@
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 	 */
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 	const s32 fuse_corr_alpha, fuse_corr_beta;
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 	const struct tegra_tsensor_group *group;
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+};
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+
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+struct tsensor_group_thermtrips {
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+	u8 id;
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+	u32 temp;
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 };
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 struct tegra_soctherm_fuse {
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@@ -113,6 +128,7 @@
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 	const int thresh_grain;
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 	const unsigned int bptt;
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 	const bool use_ccroc;
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+	struct tsensor_group_thermtrips *thermtrips;
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 };
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 int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,