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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/thermal/rockchip_thermal.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
34  * Caesar Wang <wxt@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
135  */
146 
157 #include <linux/clk.h>
....@@ -29,7 +21,7 @@
2921 #include <linux/pinctrl/consumer.h>
3022 #include <linux/nvmem-consumer.h>
3123 
32
-/**
24
+/*
3325  * If the temperature over a period of time High,
3426  * the resulting TSHUT gave CRU module,let it reset the entire chip,
3527  * or via GPIO give PMIC.
....@@ -39,7 +31,7 @@
3931 	TSHUT_MODE_OTP,
4032 };
4133 
42
-/**
34
+/*
4335  * The system Temperature Sensors tshut(tshut) polarity
4436  * the bit 8 is tshut polarity.
4537  * 0: low active, 1: high active
....@@ -49,7 +41,7 @@
4941 	TSHUT_HIGH_ACTIVE,
5042 };
5143 
52
-/**
44
+/*
5345  * The system has two Temperature Sensors.
5446  * sensor0 is for CPU, and sensor1 is for GPU.
5547  */
....@@ -58,7 +50,7 @@
5850 	SENSOR_GPU,
5951 };
6052 
61
-/**
53
+/*
6254  * The conversion table has the adc value and temperature.
6355  * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
6456  * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
....@@ -67,6 +59,8 @@
6759 	ADC_DECREMENT = 0,
6860 	ADC_INCREMENT,
6961 };
62
+
63
+#include "thermal_hwmon.h"
7064 
7165 /**
7266  * The max sensors is seven in rockchip SoCs.
....@@ -78,6 +72,8 @@
7872  * @id: conversion table
7973  * @length: size of conversion table
8074  * @data_mask: mask to apply on data inputs
75
+ * @kNum: linear parameter k
76
+ * @bNum: linear parameter b
8177  * @mode: sort mode of this adc variant (incrementing or decrementing)
8278  */
8379 struct chip_tsadc_table {
....@@ -92,7 +88,7 @@
9288 
9389 /**
9490  * struct rockchip_tsadc_chip - hold the private data of tsadc chip
95
- * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel
91
+ * @chn_id: array of sensor ids of chip corresponding to the channel
9692  * @chn_num: the channel number of tsadc chip
9793  * @conversion_time: the conversion time of tsadc
9894  * @trim_slope: use to conversion trim code to trim temp
....@@ -101,6 +97,7 @@
10197  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
10298  * @initialize: SoC special initialize tsadc controller method
10399  * @irq_ack: clear the interrupt
100
+ * @control: enable/disable method for the tsadc controller
104101  * @get_temp: get the temperature
105102  * @set_alarm_temp: set the high temperature interrupt
106103  * @set_tshut_temp: set the hardware-controlled shutdown temperature
....@@ -169,13 +166,17 @@
169166  * @chip: pointer to the platform/configuration data
170167  * @pdev: platform device of thermal
171168  * @reset: the reset controller of tsadc
172
- * @sensors[SOC_MAX_SENSORS]: the thermal sensor
173
- * @clk: the controller clock is divided by the exteral 24MHz
174
- * @pclk: the advanced peripherals bus clock
169
+ * @sensors: array of thermal sensors
170
+ * @clk: the bulk clk of tsadc, include controller clock and peripherals bus clock
171
+ * @num_clks: the number of tsadc clks
175172  * @grf: the general register file will be used to do static set by software
176173  * @regs: the base address of tsadc controller
177174  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
178175  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
176
+ * @pinctrl: the pinctrl of tsadc
177
+ * @gpio_state: pinctrl select gpio function
178
+ * @otp_state: pinctrl select otp out function
179
+ * @panic_nb: panic notifier block
179180  */
180181 struct rockchip_thermal_data {
181182 	const struct rockchip_tsadc_chip *chip;
....@@ -230,6 +231,8 @@
230231 #define TSADCV2_AUTO_PERIOD_HT			0x6c
231232 #define TSADCV3_AUTO_PERIOD			0x154
232233 #define TSADCV3_AUTO_PERIOD_HT			0x158
234
+#define TSADCV9_Q_MAX				0x210
235
+#define TSADCV9_FLOW_CON			0x218
233236 
234237 #define TSADCV2_AUTO_EN				BIT(0)
235238 #define TSADCV2_AUTO_EN_MASK			BIT(16)
....@@ -240,6 +243,7 @@
240243 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK	BIT(24)
241244 
242245 #define TSADCV3_AUTO_Q_SEL_EN			BIT(1)
246
+#define TSADCV3_AUTO_Q_SEL_EN_MASK		BIT(17)
243247 
244248 #define TSADCV2_INT_SRC_EN(chn)			BIT(chn)
245249 #define TSADCV2_INT_SRC_EN_MASK(chn)		BIT(16 + (chn))
....@@ -253,6 +257,7 @@
253257 #define TSADCV2_DATA_MASK			0xfff
254258 #define TSADCV3_DATA_MASK			0x3ff
255259 #define TSADCV4_DATA_MASK			0x1ff
260
+#define TSADCV5_DATA_MASK			0x7ff
256261 
257262 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT	4
258263 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT	4
....@@ -264,9 +269,19 @@
264269 #define TSADCV5_AUTO_PERIOD_HT_TIME		1622 /* 2.5ms */
265270 #define TSADCV6_AUTO_PERIOD_TIME		5000 /* 2.5ms */
266271 #define TSADCV6_AUTO_PERIOD_HT_TIME		5000 /* 2.5ms */
272
+#define TSADCV7_AUTO_PERIOD_TIME		3000 /* 2.5ms */
273
+#define TSADCV7_AUTO_PERIOD_HT_TIME		3000 /* 2.5ms */
274
+#define TSADCV12_AUTO_PERIOD_TIME		3000 /* 2.5ms */
275
+#define TSADCV12_AUTO_PERIOD_HT_TIME		3000 /* 2.5ms */
276
+#define TSADCV3_Q_MAX_VAL			0x7ff /* 11bit 2047 */
277
+#define TSADCV12_Q_MAX_VAL			0xfff /* 12bit 4095 */
267278 
268279 #define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
269280 #define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
281
+
282
+#define TSADCV9_AUTO_SRC			(0x10001 << 0)
283
+#define TSADCV9_PD_MODE				(0x10001 << 4)
284
+#define TSADCV9_Q_MAX_VAL			(0xffff0400 << 0)
270285 
271286 #define GRF_SARADC_TESTBIT			0x0e644
272287 #define GRF_TSADC_TESTBIT_L			0x0e648
....@@ -277,11 +292,19 @@
277292 
278293 #define RK1808_BUS_GRF_SOC_CON0			0x0400
279294 
295
+#define RK3528_GRF_TSADC_CON			0x40030
296
+
297
+#define RK3562_GRF_TSADC_CON			0x0580
298
+
280299 #define RK3568_GRF_TSADC_CON			0x0600
281300 #define RK3568_GRF_TSADC_ANA_REG0		(0x10001 << 0)
282301 #define RK3568_GRF_TSADC_ANA_REG1		(0x10001 << 1)
283302 #define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
284303 #define RK3568_GRF_TSADC_TSEN			(0x10001 << 8)
304
+
305
+#define RV1106_VOGRF_TSADC_CON			0x6000C
306
+#define RV1106_VOGRF_TSADC_TSEN			(0x10001 << 8)
307
+#define RV1106_VOGRF_TSADC_ANA			(0xff0007 << 0)
285308 
286309 #define RV1126_GRF0_TSADC_CON			0x0100
287310 
....@@ -299,16 +322,10 @@
299322 #define PX30S_TSADC_TDC_MODE			(0x10001 << 4)
300323 #define PX30S_TSADC_TRIM			(0xf0007 << 0)
301324 
302
-#define MIN_TEMP				(-40000)
303
-#define LOWEST_TEMP				(-273000)
304
-#define MAX_TEMP				(125000)
305
-#define MAX_ENV_TEMP				(85000)
306325 
307
-#define BASE					(1024)
308
-#define BASE_SHIFT				(10)
309
-#define START_DEBOUNCE_COUNT			(100)
310
-#define HIGHER_DEBOUNCE_TEMP			(30000)
311
-#define LOWER_DEBOUNCE_TEMP			(15000)
326
+/* -40 to 125 is reliable, outside the range existed unreliability */
327
+#define MIN_TEMP				(-60000)
328
+#define MAX_TEMP				(180000)
312329 
313330 /**
314331  * struct tsadc_table - code to temperature conversion table
....@@ -325,9 +342,20 @@
325342 	int temp;
326343 };
327344 
345
+static const struct tsadc_table rv1106_code_table[] = {
346
+	{0, MIN_TEMP},
347
+	{363, MIN_TEMP},
348
+	{396, -40000},
349
+	{504, 25000},
350
+	{605, 85000},
351
+	{673, 125000},
352
+	{758, MAX_TEMP},
353
+	{TSADCV2_DATA_MASK, MAX_TEMP},
354
+};
328355 
329356 static const struct tsadc_table rv1108_table[] = {
330
-	{0, -40000},
357
+	{0, MIN_TEMP},
358
+	{342, MIN_TEMP},
331359 	{374, -40000},
332360 	{382, -35000},
333361 	{389, -30000},
....@@ -362,11 +390,13 @@
362390 	{618, 115000},
363391 	{626, 120000},
364392 	{634, 125000},
365
-	{TSADCV2_DATA_MASK, 125000},
393
+	{722, MAX_TEMP},
394
+	{TSADCV2_DATA_MASK, MAX_TEMP},
366395 };
367396 
368397 static const struct tsadc_table rk1808_code_table[] = {
369
-	{0, -40000},
398
+	{0, MIN_TEMP},
399
+	{3423, MIN_TEMP},
370400 	{3455, -40000},
371401 	{3463, -35000},
372402 	{3471, -30000},
....@@ -401,11 +431,13 @@
401431 	{3709, 115000},
402432 	{3718, 120000},
403433 	{3726, 125000},
404
-	{TSADCV2_DATA_MASK, 125000},
434
+	{3820, MAX_TEMP},
435
+	{TSADCV2_DATA_MASK, MAX_TEMP},
405436 };
406437 
407438 static const struct tsadc_table rk3228_code_table[] = {
408
-	{0, -40000},
439
+	{0, MIN_TEMP},
440
+	{568, MIN_TEMP},
409441 	{588, -40000},
410442 	{593, -35000},
411443 	{598, -30000},
....@@ -440,11 +472,13 @@
440472 	{749, 115000},
441473 	{754, 120000},
442474 	{760, 125000},
443
-	{TSADCV2_DATA_MASK, 125000},
475
+	{821, MAX_TEMP},
476
+	{TSADCV2_DATA_MASK, MAX_TEMP},
444477 };
445478 
446479 static const struct tsadc_table rk3288_code_table[] = {
447
-	{TSADCV2_DATA_MASK, -40000},
480
+	{TSADCV2_DATA_MASK, MIN_TEMP},
481
+	{3833, MIN_TEMP},
448482 	{3800, -40000},
449483 	{3792, -35000},
450484 	{3783, -30000},
....@@ -479,11 +513,15 @@
479513 	{3452, 115000},
480514 	{3437, 120000},
481515 	{3421, 125000},
482
-	{0, 125000},
516
+	{3350, 145000},
517
+	{3270, 165000},
518
+	{3195, MAX_TEMP},
519
+	{0, MAX_TEMP},
483520 };
484521 
485522 static const struct tsadc_table rk3328_code_table[] = {
486
-	{0, -40000},
523
+	{0, MIN_TEMP},
524
+	{261, MIN_TEMP},
487525 	{296, -40000},
488526 	{304, -35000},
489527 	{313, -30000},
....@@ -517,11 +555,15 @@
517555 	{644, 115000},
518556 	{659, 120000},
519557 	{675, 125000},
520
-	{TSADCV2_DATA_MASK, 125000},
558
+	{745, 145000},
559
+	{825, 165000},
560
+	{900, MAX_TEMP},
561
+	{TSADCV2_DATA_MASK, MAX_TEMP},
521562 };
522563 
523564 static const struct tsadc_table rk3368_code_table[] = {
524
-	{0, -40000},
565
+	{0, MIN_TEMP},
566
+	{98, MIN_TEMP},
525567 	{106, -40000},
526568 	{108, -35000},
527569 	{110, -30000},
....@@ -556,11 +598,13 @@
556598 	{167, 115000},
557599 	{169, 120000},
558600 	{171, 125000},
559
-	{TSADCV3_DATA_MASK, 125000},
601
+	{193, MAX_TEMP},
602
+	{TSADCV3_DATA_MASK, MAX_TEMP},
560603 };
561604 
562605 static const struct tsadc_table rk3399_code_table[] = {
563
-	{0, -40000},
606
+	{0, MIN_TEMP},
607
+	{368, MIN_TEMP},
564608 	{402, -40000},
565609 	{410, -35000},
566610 	{419, -30000},
....@@ -595,11 +639,95 @@
595639 	{668, 115000},
596640 	{677, 120000},
597641 	{685, 125000},
598
-	{TSADCV3_DATA_MASK, 125000},
642
+	{782, MAX_TEMP},
643
+	{TSADCV3_DATA_MASK, MAX_TEMP},
644
+};
645
+
646
+static const struct tsadc_table rk3528_code_table[] = {
647
+	{0, MIN_TEMP},
648
+	{1386, MIN_TEMP},
649
+	{1419, -40000},
650
+	{1427, -35000},
651
+	{1435, -30000},
652
+	{1443, -25000},
653
+	{1452, -20000},
654
+	{1460, -15000},
655
+	{1468, -10000},
656
+	{1477, -5000},
657
+	{1486, 0},
658
+	{1494, 5000},
659
+	{1502, 10000},
660
+	{1510, 15000},
661
+	{1519, 20000},
662
+	{1527, 25000},
663
+	{1535, 30000},
664
+	{1544, 35000},
665
+	{1552, 40000},
666
+	{1561, 45000},
667
+	{1569, 50000},
668
+	{1578, 55000},
669
+	{1586, 60000},
670
+	{1594, 65000},
671
+	{1603, 70000},
672
+	{1612, 75000},
673
+	{1620, 80000},
674
+	{1628, 85000},
675
+	{1637, 90000},
676
+	{1646, 95000},
677
+	{1654, 100000},
678
+	{1662, 105000},
679
+	{1671, 110000},
680
+	{1679, 115000},
681
+	{1688, 120000},
682
+	{1696, 125000},
683
+	{1790, MAX_TEMP},
684
+	{TSADCV5_DATA_MASK, MAX_TEMP},
685
+};
686
+
687
+static const struct tsadc_table rk3562_code_table[] = {
688
+	{0, MIN_TEMP},
689
+	{1385, MIN_TEMP},
690
+	{1419, -40000},
691
+	{1428, -35000},
692
+	{1436, -30000},
693
+	{1445, -25000},
694
+	{1453, -20000},
695
+	{1462, -15000},
696
+	{1470, -10000},
697
+	{1479, -5000},
698
+	{1487, 0},
699
+	{1496, 5000},
700
+	{1504, 10000},
701
+	{1512, 15000},
702
+	{1521, 20000},
703
+	{1529, 25000},
704
+	{1538, 30000},
705
+	{1546, 35000},
706
+	{1555, 40000},
707
+	{1563, 45000},
708
+	{1572, 50000},
709
+	{1580, 55000},
710
+	{1589, 60000},
711
+	{1598, 65000},
712
+	{1606, 70000},
713
+	{1615, 75000},
714
+	{1623, 80000},
715
+	{1632, 85000},
716
+	{1640, 90000},
717
+	{1648, 95000},
718
+	{1657, 100000},
719
+	{1666, 105000},
720
+	{1674, 110000},
721
+	{1682, 115000},
722
+	{1691, 120000},
723
+	{1699, 125000},
724
+	{1793, MAX_TEMP},
725
+	{TSADCV2_DATA_MASK, MAX_TEMP},
599726 };
600727 
601728 static const struct tsadc_table rk3568_code_table[] = {
602
-	{0, -40000},
729
+	{0, MIN_TEMP},
730
+	{1448, MIN_TEMP},
603731 	{1584, -40000},
604732 	{1620, -35000},
605733 	{1652, -30000},
....@@ -634,16 +762,19 @@
634762 	{2636, 115000},
635763 	{2672, 120000},
636764 	{2704, 125000},
637
-	{TSADCV2_DATA_MASK, 125000},
765
+	{3076, MAX_TEMP},
766
+	{TSADCV2_DATA_MASK, MAX_TEMP},
638767 };
639768 
640769 static const struct tsadc_table rk3588_code_table[] = {
641
-	{0, -40000},
770
+	{0, MIN_TEMP},
771
+	{194, MIN_TEMP},
642772 	{215, -40000},
643773 	{285, 25000},
644774 	{350, 85000},
645775 	{395, 125000},
646
-	{TSADCV4_DATA_MASK, 125000},
776
+	{455, MAX_TEMP},
777
+	{TSADCV4_DATA_MASK, MAX_TEMP},
647778 };
648779 
649780 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
....@@ -775,6 +906,9 @@
775906 
776907 /**
777908  * rk_tsadcv2_initialize - initialize TASDC Controller.
909
+ * @grf: the general register file will be used to do static set by software
910
+ * @regs: the base address of tsadc controller
911
+ * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
778912  *
779913  * (1) Set TSADC_V2_AUTO_PERIOD:
780914  *     Configure the interleave between every two accessing of
....@@ -809,6 +943,9 @@
809943 
810944 /**
811945  * rk_tsadcv3_initialize - initialize TASDC Controller.
946
+ * @grf: the general register file will be used to do static set by software
947
+ * @regs: the base address of tsadc controller
948
+ * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
812949  *
813950  * (1) The tsadc control power sequence.
814951  *
....@@ -874,8 +1011,7 @@
8741011 				  enum tshut_polarity tshut_polarity)
8751012 {
8761013 	rk_tsadcv2_initialize(grf, regs, tshut_polarity);
877
-	if (!IS_ERR(grf))
878
-		regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
1014
+	regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
8791015 }
8801016 
8811017 static void rk_tsadcv5_initialize(struct regmap *grf, void __iomem *regs,
....@@ -932,12 +1068,26 @@
9321068 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
9331069 			       regs + TSADCV2_AUTO_CON);
9341070 
1071
+	/*
1072
+	 * The general register file will is optional
1073
+	 * and might not be available.
1074
+	 */
9351075 	if (!IS_ERR(grf)) {
9361076 		regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1077
+		/*
1078
+		 * RK3568 TRM, section 18.5. requires a delay no less
1079
+		 * than 10us between the rising edge of tsadc_tsen_en
1080
+		 * and the rising edge of tsadc_ana_reg_0/1/2.
1081
+		 */
9371082 		udelay(15);
9381083 		regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
9391084 		regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
9401085 		regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1086
+
1087
+		/*
1088
+		 * RK3568 TRM, section 18.5. requires a delay no less
1089
+		 * than 90us after the rising edge of tsadc_ana_reg_0/1/2.
1090
+		 */
9411091 		usleep_range(100, 200);
9421092 	}
9431093 }
....@@ -964,10 +1114,101 @@
9641114 static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs,
9651115 				  enum tshut_polarity tshut_polarity)
9661116 {
1117
+	regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN);
1118
+	udelay(10);
1119
+	regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA);
1120
+	udelay(100);
1121
+
1122
+	writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1123
+	writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
1124
+		       regs + TSADCV3_AUTO_PERIOD_HT);
1125
+	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1126
+		       regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1127
+	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1128
+		       regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1129
+	writel_relaxed(TSADCV9_AUTO_SRC, regs + TSADCV2_INT_PD);
1130
+	writel_relaxed(TSADCV9_PD_MODE, regs + TSADCV9_FLOW_CON);
1131
+	writel_relaxed(TSADCV9_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
1132
+	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1133
+		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1134
+			       TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1135
+			       regs + TSADCV2_AUTO_CON);
1136
+	else
1137
+		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1138
+			       regs + TSADCV2_AUTO_CON);
1139
+	writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | (TSADCV3_AUTO_Q_SEL_EN << 16),
1140
+		       regs + TSADCV2_AUTO_CON);
1141
+}
1142
+
1143
+static void rk_tsadcv10_initialize(struct regmap *grf, void __iomem *regs,
1144
+				   enum tshut_polarity tshut_polarity)
1145
+{
9671146 	rk_tsadcv2_initialize(grf, regs, tshut_polarity);
9681147 	if (!IS_ERR(grf)) {
9691148 		regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TDC_MODE);
9701149 		regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TRIM);
1150
+	}
1151
+}
1152
+
1153
+static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
1154
+				  enum tshut_polarity tshut_polarity)
1155
+{
1156
+	writel_relaxed(TSADCV7_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1157
+	writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME,
1158
+		       regs + TSADCV3_AUTO_PERIOD_HT);
1159
+	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1160
+		       regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1161
+	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1162
+		       regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1163
+	writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
1164
+	writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
1165
+		       regs + TSADCV2_AUTO_CON);
1166
+	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1167
+		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1168
+			       TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1169
+			       regs + TSADCV2_AUTO_CON);
1170
+	else
1171
+		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1172
+			       regs + TSADCV2_AUTO_CON);
1173
+
1174
+	if (!IS_ERR(grf)) {
1175
+		regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1176
+		udelay(15);
1177
+		regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
1178
+		regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
1179
+		regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1180
+		usleep_range(100, 200);
1181
+	}
1182
+}
1183
+
1184
+static void rk_tsadcv12_initialize(struct regmap *grf, void __iomem *regs,
1185
+				   enum tshut_polarity tshut_polarity)
1186
+{
1187
+	writel_relaxed(TSADCV12_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1188
+	writel_relaxed(TSADCV12_AUTO_PERIOD_HT_TIME,
1189
+		       regs + TSADCV3_AUTO_PERIOD_HT);
1190
+	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1191
+		       regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1192
+	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1193
+		       regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1194
+	writel_relaxed(TSADCV12_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
1195
+	writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
1196
+		       regs + TSADCV2_AUTO_CON);
1197
+	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1198
+		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1199
+			       TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1200
+			       regs + TSADCV2_AUTO_CON);
1201
+	else
1202
+		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1203
+			       regs + TSADCV2_AUTO_CON);
1204
+
1205
+	if (!IS_ERR(grf)) {
1206
+		regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1207
+		udelay(15);
1208
+		regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
1209
+		regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
1210
+		regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1211
+		usleep_range(100, 200);
9711212 	}
9721213 }
9731214 
....@@ -1013,6 +1254,8 @@
10131254 
10141255 /**
10151256  * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
1257
+ * @regs: the base address of tsadc controller
1258
+ * @enable: boolean flag to enable the controller
10161259  *
10171260  * NOTE: TSADC controller works at auto mode, and some SoCs need set the
10181261  * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
....@@ -1051,91 +1294,6 @@
10511294 	val = readl_relaxed(regs + TSADCV2_DATA(chn));
10521295 
10531296 	return rk_tsadcv2_code_to_temp(table, val, temp);
1054
-}
1055
-
1056
-static int predict_temp(int temp)
1057
-{
1058
-	/*
1059
-	 * The deviation of prediction. the temperature will not change rapidly,
1060
-	 * so this cov_q is small
1061
-	 */
1062
-	int cov_q = 18;
1063
-	/*
1064
-	 * The deviation of tsadc's reading, deviation of tsadc is very big when
1065
-	 * abnormal temperature is get
1066
-	 */
1067
-	int cov_r = 542;
1068
-
1069
-	int gain;
1070
-	int temp_mid;
1071
-	int temp_now;
1072
-	int prob_mid;
1073
-	int prob_now;
1074
-	static int temp_last = LOWEST_TEMP;
1075
-	static int prob_last = 160;
1076
-	static int bounding_cnt;
1077
-
1078
-	/*
1079
-	 * init temp_last with a more suitable value, which mostly equals to
1080
-	 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the
1081
-	 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal
1082
-	 * value and temp_last is adjusted to MAX_ENV_TEMP.
1083
-	 */
1084
-	if (temp_last == LOWEST_TEMP)
1085
-		temp_last = min(temp, MAX_ENV_TEMP);
1086
-
1087
-	/*
1088
-	 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider
1089
-	 * tsadc is stable, i.e. after that, the temperature may be not stable
1090
-	 * and may have abnormal reading, so we set a bounding temperature. If
1091
-	 * the reading from tsadc is too big, we set the delta temperature of
1092
-	 * DEBOUNCE_TEMP/3 comparing to the last temperature.
1093
-	 */
1094
-
1095
-	if (bounding_cnt++ > START_DEBOUNCE_COUNT) {
1096
-		bounding_cnt = START_DEBOUNCE_COUNT;
1097
-		if (temp - temp_last > HIGHER_DEBOUNCE_TEMP)
1098
-			temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3;
1099
-		if (temp_last - temp > LOWER_DEBOUNCE_TEMP)
1100
-			temp = temp_last - LOWER_DEBOUNCE_TEMP / 3;
1101
-	}
1102
-
1103
-	temp_mid = temp_last;
1104
-
1105
-	/* calculate the probability of this time's prediction */
1106
-	prob_mid = prob_last + cov_q;
1107
-
1108
-	/* calculate the Kalman Gain */
1109
-	gain = (prob_mid * BASE) / (prob_mid + cov_r);
1110
-
1111
-	/* calculate the prediction of temperature */
1112
-	temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT;
1113
-
1114
-	/*
1115
-	 * Base on this time's Kalman Gain, ajust our probability of prediction
1116
-	 * for next time calculation
1117
-	 */
1118
-	prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT;
1119
-
1120
-	prob_last = prob_now;
1121
-	temp_last = temp_now;
1122
-
1123
-	return temp_last;
1124
-}
1125
-
1126
-static int rk_tsadcv3_get_temp(const struct chip_tsadc_table *table,
1127
-			       int chn, void __iomem *regs, int *temp)
1128
-{
1129
-	u32 val;
1130
-	int ret;
1131
-
1132
-	val = readl_relaxed(regs + TSADCV2_DATA(chn));
1133
-
1134
-	ret = rk_tsadcv2_code_to_temp(table, val, temp);
1135
-	if (!ret)
1136
-		*temp = predict_temp(*temp);
1137
-
1138
-	return ret;
11391297 }
11401298 
11411299 static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
....@@ -1347,6 +1505,75 @@
13471505 	return 0;
13481506 }
13491507 
1508
+static const struct rockchip_tsadc_chip px30_tsadc_data = {
1509
+	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1510
+	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1511
+	.chn_num = 2, /* 2 channels for tsadc */
1512
+
1513
+	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1514
+	.tshut_temp = 95000,
1515
+
1516
+	.initialize = rk_tsadcv4_initialize,
1517
+	.irq_ack = rk_tsadcv3_irq_ack,
1518
+	.control = rk_tsadcv3_control,
1519
+	.get_temp = rk_tsadcv2_get_temp,
1520
+	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1521
+	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1522
+	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1523
+
1524
+	.table = {
1525
+		.id = rk3328_code_table,
1526
+		.length = ARRAY_SIZE(rk3328_code_table),
1527
+		.data_mask = TSADCV2_DATA_MASK,
1528
+		.mode = ADC_INCREMENT,
1529
+	},
1530
+};
1531
+
1532
+static const struct rockchip_tsadc_chip px30s_tsadc_data = {
1533
+	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1534
+	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1535
+	.chn_num = 2, /* 1 channels for tsadc */
1536
+	.conversion_time = 2100, /* us */
1537
+	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1538
+	.tshut_temp = 95000,
1539
+	.initialize = rk_tsadcv10_initialize,
1540
+	.irq_ack = rk_tsadcv3_irq_ack,
1541
+	.control = rk_tsadcv2_control,
1542
+	.get_temp = rk_tsadcv2_get_temp,
1543
+	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1544
+	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1545
+	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1546
+	.set_clk_rate = rk_tsadcv1_set_clk_rate,
1547
+	.table = {
1548
+		.kNum = 2699,
1549
+		.bNum = 2796,
1550
+		.data_mask = TSADCV2_DATA_MASK,
1551
+		.mode = ADC_INCREMENT,
1552
+	},
1553
+};
1554
+
1555
+static const struct rockchip_tsadc_chip rv1106_tsadc_data = {
1556
+	/* top, big_core0, big_core1, little_core, center, gpu, npu */
1557
+	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1558
+	.chn_num = 1, /* seven channels for tsadc */
1559
+	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1560
+	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1561
+	.tshut_temp = 95000,
1562
+	.initialize = rk_tsadcv9_initialize,
1563
+	.irq_ack = rk_tsadcv4_irq_ack,
1564
+	.control = rk_tsadcv4_control,
1565
+	.get_temp = rk_tsadcv4_get_temp,
1566
+	.set_alarm_temp = rk_tsadcv3_alarm_temp,
1567
+	.set_tshut_temp = rk_tsadcv3_tshut_temp,
1568
+	.set_tshut_mode = rk_tsadcv4_tshut_mode,
1569
+	.table = {
1570
+		.id = rv1106_code_table,
1571
+		.length = ARRAY_SIZE(rv1106_code_table),
1572
+		.data_mask = TSADCV2_DATA_MASK,
1573
+		.mode = ADC_INCREMENT,
1574
+	},
1575
+};
1576
+
13501577 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
13511578 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
13521579 	.chn_num = 1, /* one channel for tsadc */
....@@ -1457,7 +1684,7 @@
14571684 	.initialize = rk_tsadcv2_initialize,
14581685 	.irq_ack = rk_tsadcv2_irq_ack,
14591686 	.control = rk_tsadcv2_control,
1460
-	.get_temp = rk_tsadcv3_get_temp,
1687
+	.get_temp = rk_tsadcv2_get_temp,
14611688 	.set_alarm_temp = rk_tsadcv2_alarm_temp,
14621689 	.set_tshut_temp = rk_tsadcv2_tshut_temp,
14631690 	.set_tshut_mode = rk_tsadcv2_tshut_mode,
....@@ -1478,7 +1705,7 @@
14781705 	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
14791706 	.tshut_temp = 95000,
14801707 
1481
-	.initialize = rk_tsadcv4_initialize,
1708
+	.initialize = rk_tsadcv2_initialize,
14821709 	.irq_ack = rk_tsadcv3_irq_ack,
14831710 	.control = rk_tsadcv3_control,
14841711 	.get_temp = rk_tsadcv2_get_temp,
....@@ -1494,38 +1721,16 @@
14941721 	},
14951722 };
14961723 
1497
-static const struct rockchip_tsadc_chip px30_tsadc_data = {
1724
+static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = {
14981725 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1499
-	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1500
-	.chn_num = 2, /* 2 channels for tsadc */
1726
+	.chn_num = 1, /* 1 channels for tsadc */
15011727 
1502
-	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1503
-	.tshut_temp = 95000,
1504
-
1505
-	.initialize = rk_tsadcv4_initialize,
1506
-	.irq_ack = rk_tsadcv3_irq_ack,
1507
-	.control = rk_tsadcv3_control,
1508
-	.get_temp = rk_tsadcv2_get_temp,
1509
-	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1510
-	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1511
-	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1512
-
1513
-	.table = {
1514
-		.id = rk3328_code_table,
1515
-		.length = ARRAY_SIZE(rk3328_code_table),
1516
-		.data_mask = TSADCV2_DATA_MASK,
1517
-		.mode = ADC_INCREMENT,
1518
-	},
1519
-};
1520
-
1521
-static const struct rockchip_tsadc_chip px30s_tsadc_data = {
1522
-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1523
-	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1524
-	.chn_num = 2, /* 1 channels for tsadc */
15251728 	.conversion_time = 2100, /* us */
1729
+
15261730 	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
15271731 	.tshut_temp = 95000,
1528
-	.initialize = rk_tsadcv9_initialize,
1732
+
1733
+	.initialize = rk_tsadcv2_initialize,
15291734 	.irq_ack = rk_tsadcv3_irq_ack,
15301735 	.control = rk_tsadcv2_control,
15311736 	.get_temp = rk_tsadcv2_get_temp,
....@@ -1533,6 +1738,7 @@
15331738 	.set_tshut_temp = rk_tsadcv2_tshut_temp,
15341739 	.set_tshut_mode = rk_tsadcv2_tshut_mode,
15351740 	.set_clk_rate = rk_tsadcv1_set_clk_rate,
1741
+
15361742 	.table = {
15371743 		.kNum = 2699,
15381744 		.bNum = 2796,
....@@ -1639,6 +1845,54 @@
16391845 	},
16401846 };
16411847 
1848
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
1849
+	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1850
+	.chn_num = 1, /* one channels for tsadc */
1851
+
1852
+	.tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1853
+	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1854
+	.tshut_temp = 95000,
1855
+
1856
+	.initialize = rk_tsadcv11_initialize,
1857
+	.irq_ack = rk_tsadcv4_irq_ack,
1858
+	.control = rk_tsadcv4_control,
1859
+	.get_temp = rk_tsadcv4_get_temp,
1860
+	.set_alarm_temp = rk_tsadcv3_alarm_temp,
1861
+	.set_tshut_temp = rk_tsadcv3_tshut_temp,
1862
+	.set_tshut_mode = rk_tsadcv4_tshut_mode,
1863
+
1864
+	.table = {
1865
+		.id = rk3528_code_table,
1866
+		.length = ARRAY_SIZE(rk3528_code_table),
1867
+		.data_mask = TSADCV2_DATA_MASK,
1868
+		.mode = ADC_INCREMENT,
1869
+	},
1870
+};
1871
+
1872
+static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
1873
+	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1874
+	.chn_num = 1, /* one channels for tsadc */
1875
+
1876
+	.tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1877
+	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1878
+	.tshut_temp = 95000,
1879
+
1880
+	.initialize = rk_tsadcv12_initialize,
1881
+	.irq_ack = rk_tsadcv4_irq_ack,
1882
+	.control = rk_tsadcv4_control,
1883
+	.get_temp = rk_tsadcv4_get_temp,
1884
+	.set_alarm_temp = rk_tsadcv3_alarm_temp,
1885
+	.set_tshut_temp = rk_tsadcv3_tshut_temp,
1886
+	.set_tshut_mode = rk_tsadcv4_tshut_mode,
1887
+
1888
+	.table = {
1889
+		.id = rk3562_code_table,
1890
+		.length = ARRAY_SIZE(rk3562_code_table),
1891
+		.data_mask = TSADCV2_DATA_MASK,
1892
+		.mode = ADC_INCREMENT,
1893
+	},
1894
+};
1895
+
16421896 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
16431897 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
16441898 	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
....@@ -1689,7 +1943,21 @@
16891943 };
16901944 
16911945 static const struct of_device_id of_rockchip_thermal_match[] = {
1692
-#ifdef CONFIG_CPU_RV110X
1946
+#ifdef CONFIG_CPU_PX30
1947
+	{	.compatible = "rockchip,px30-tsadc",
1948
+		.data = (void *)&px30_tsadc_data,
1949
+	},
1950
+	{	.compatible = "rockchip,px30s-tsadc",
1951
+		.data = (void *)&px30s_tsadc_data,
1952
+	},
1953
+#endif
1954
+#ifdef CONFIG_CPU_RV1106
1955
+	{
1956
+		.compatible = "rockchip,rv1106-tsadc",
1957
+		.data = (void *)&rv1106_tsadc_data,
1958
+	},
1959
+#endif
1960
+#ifdef CONFIG_CPU_RV1108
16931961 	{
16941962 		.compatible = "rockchip,rv1108-tsadc",
16951963 		.data = (void *)&rv1108_tsadc_data,
....@@ -1699,14 +1967,6 @@
16991967 	{
17001968 		.compatible = "rockchip,rv1126-tsadc",
17011969 		.data = (void *)&rv1126_tsadc_data,
1702
-	},
1703
-#endif
1704
-#ifdef CONFIG_CPU_PX30
1705
-	{	.compatible = "rockchip,px30-tsadc",
1706
-		.data = (void *)&px30_tsadc_data,
1707
-	},
1708
-	{	.compatible = "rockchip,px30s-tsadc",
1709
-		.data = (void *)&px30s_tsadc_data,
17101970 	},
17111971 #endif
17121972 #ifdef CONFIG_CPU_RK1808
....@@ -1731,6 +1991,10 @@
17311991 	{
17321992 		.compatible = "rockchip,rk3308-tsadc",
17331993 		.data = (void *)&rk3308_tsadc_data,
1994
+	},
1995
+	{
1996
+		.compatible = "rockchip,rk3308bs-tsadc",
1997
+		.data = (void *)&rk3308bs_tsadc_data,
17341998 	},
17351999 #endif
17362000 #ifdef CONFIG_CPU_RK3328
....@@ -1757,6 +2021,18 @@
17572021 		.data = (void *)&rk3399_tsadc_data,
17582022 	},
17592023 #endif
2024
+#ifdef CONFIG_CPU_RK3528
2025
+	{
2026
+		.compatible = "rockchip,rk3528-tsadc",
2027
+		.data = (void *)&rk3528_tsadc_data,
2028
+	},
2029
+#endif
2030
+#ifdef CONFIG_CPU_RK3562
2031
+	{
2032
+		.compatible = "rockchip,rk3562-tsadc",
2033
+		.data = (void *)&rk3562_tsadc_data,
2034
+	},
2035
+#endif
17602036 #ifdef CONFIG_CPU_RK3568
17612037 	{
17622038 		.compatible = "rockchip,rk3568-tsadc",
....@@ -1778,8 +2054,10 @@
17782054 {
17792055 	struct thermal_zone_device *tzd = sensor->tzd;
17802056 
1781
-	tzd->ops->set_mode(tzd,
1782
-		on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
2057
+	if (on)
2058
+		thermal_zone_device_enable(tzd);
2059
+	else
2060
+		thermal_zone_device_disable(tzd);
17832061 }
17842062 
17852063 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
....@@ -2050,6 +2328,7 @@
20502328 
20512329 /**
20522330  * Reset TSADC Controller, reset all tsadc registers.
2331
+ * @reset: the reset controller of tsadc
20532332  */
20542333 static void rockchip_thermal_reset_controller(struct reset_control *reset)
20552334 {
....@@ -2110,10 +2389,8 @@
21102389 		return -ENXIO;
21112390 
21122391 	irq = platform_get_irq(pdev, 0);
2113
-	if (irq < 0) {
2114
-		dev_err(&pdev->dev, "no irq resource?\n");
2392
+	if (irq < 0)
21152393 		return -EINVAL;
2116
-	}
21172394 
21182395 	thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
21192396 			       GFP_KERNEL);
....@@ -2127,6 +2404,8 @@
21272404 		return -EINVAL;
21282405 	if (soc_is_px30s())
21292406 		thermal->chip = &px30s_tsadc_data;
2407
+	if (soc_is_rk3308bs())
2408
+		thermal->chip = &rk3308bs_tsadc_data;
21302409 
21312410 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
21322411 	thermal->regs = devm_ioremap_resource(&pdev->dev, res);
....@@ -2214,8 +2493,15 @@
22142493 		usleep_range(thermal->chip->conversion_time,
22152494 			     thermal->chip->conversion_time + 50);
22162495 
2217
-	for (i = 0; i < thermal->chip->chn_num; i++)
2496
+	for (i = 0; i < thermal->chip->chn_num; i++) {
22182497 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
2498
+		thermal->sensors[i].tzd->tzp->no_hwmon = false;
2499
+		error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
2500
+		if (error)
2501
+			dev_warn(&pdev->dev,
2502
+				 "failed to register sensor %d with hwmon: %d\n",
2503
+				 i, error);
2504
+	}
22192505 
22202506 	thermal->panic_nb.notifier_call = rockchip_thermal_panic;
22212507 	atomic_notifier_chain_register(&panic_notifier_list,
....@@ -2239,6 +2525,7 @@
22392525 	for (i = 0; i < thermal->chip->chn_num; i++) {
22402526 		struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
22412527 
2528
+		thermal_remove_hwmon_sysfs(sensor->tzd);
22422529 		rockchip_thermal_toggle_sensor(sensor, false);
22432530 	}
22442531 
....@@ -2268,8 +2555,7 @@
22682555 
22692556 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
22702557 {
2271
-	struct platform_device *pdev = to_platform_device(dev);
2272
-	struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
2558
+	struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
22732559 	int i;
22742560 
22752561 	for (i = 0; i < thermal->chip->chn_num; i++)
....@@ -2287,14 +2573,13 @@
22872573 
22882574 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
22892575 {
2290
-	struct platform_device *pdev = to_platform_device(dev);
2291
-	struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
2576
+	struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
22922577 	int i;
22932578 	int error;
22942579 
22952580 	error = clk_bulk_enable(thermal->num_clks, thermal->clks);
22962581 	if (error) {
2297
-		dev_err(&pdev->dev, "failed to enable tsadc bulk clks: %d\n",
2582
+		dev_err(dev, "failed to enable tsadc bulk clks: %d\n",
22982583 			error);
22992584 		return error;
23002585 	}
....@@ -2315,7 +2600,7 @@
23152600 						      id, thermal->regs,
23162601 						      tshut_temp);
23172602 		if (error)
2318
-			dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
2603
+			dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
23192604 				__func__, tshut_temp, error);
23202605 	}
23212606 
....@@ -2347,7 +2632,17 @@
23472632 	.shutdown = rockchip_thermal_shutdown,
23482633 };
23492634 
2350
-module_platform_driver(rockchip_thermal_driver);
2635
+static int __init rockchip_thermal_driver_init(void)
2636
+{
2637
+	return platform_driver_register(&rockchip_thermal_driver);
2638
+}
2639
+rootfs_initcall(rockchip_thermal_driver_init);
2640
+
2641
+static void __exit rockchip_thermal_driver_exit(void)
2642
+{
2643
+	platform_driver_unregister(&rockchip_thermal_driver);
2644
+}
2645
+module_exit(rockchip_thermal_driver_exit);
23512646 
23522647 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
23532648 MODULE_AUTHOR("Rockchip, Inc.");