hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/staging/vt6656/mac.h
....@@ -1,4 +1,4 @@
1
-// SPDX-License-Identifier: GPL-2.0+
1
+/* SPDX-License-Identifier: GPL-2.0+ */
22 /*
33 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
44 * All rights reserved.
....@@ -20,6 +20,7 @@
2020 #ifndef __MAC_H__
2121 #define __MAC_H__
2222
23
+#include <linux/bits.h>
2324 #include "device.h"
2425
2526 #define REV_ID_VT3253_A0 0x00
....@@ -142,109 +143,109 @@
142143 #define MAC_REG_RSPINF_A_72 0xfc
143144
144145 /* Bits in the I2MCFG EEPROM register */
145
-#define I2MCFG_BOUNDCTL 0x80
146
-#define I2MCFG_WAITCTL 0x20
147
-#define I2MCFG_SCLOECTL 0x10
148
-#define I2MCFG_WBUSYCTL 0x08
149
-#define I2MCFG_NORETRY 0x04
150
-#define I2MCFG_I2MLDSEQ 0x02
151
-#define I2MCFG_I2CMFAST 0x01
146
+#define I2MCFG_BOUNDCTL BIT(7)
147
+#define I2MCFG_WAITCTL BIT(5)
148
+#define I2MCFG_SCLOECTL BIT(4)
149
+#define I2MCFG_WBUSYCTL BIT(3)
150
+#define I2MCFG_NORETRY BIT(2)
151
+#define I2MCFG_I2MLDSEQ BIT(1)
152
+#define I2MCFG_I2CMFAST BIT(0)
152153
153154 /* Bits in the I2MCSR EEPROM register */
154
-#define I2MCSR_EEMW 0x80
155
-#define I2MCSR_EEMR 0x40
156
-#define I2MCSR_AUTOLD 0x08
157
-#define I2MCSR_NACK 0x02
158
-#define I2MCSR_DONE 0x01
155
+#define I2MCSR_EEMW BIT(7)
156
+#define I2MCSR_EEMR BIT(6)
157
+#define I2MCSR_AUTOLD BIT(3)
158
+#define I2MCSR_NACK BIT(1)
159
+#define I2MCSR_DONE BIT(0)
159160
160161 /* Bits in the TMCTL register */
161
-#define TMCTL_TSUSP 0x04
162
-#define TMCTL_TMD 0x02
163
-#define TMCTL_TE 0x01
162
+#define TMCTL_TSUSP BIT(2)
163
+#define TMCTL_TMD BIT(1)
164
+#define TMCTL_TE BIT(0)
164165
165166 /* Bits in the TFTCTL register */
166
-#define TFTCTL_HWUTSF 0x80
167
-#define TFTCTL_TBTTSYNC 0x40
168
-#define TFTCTL_HWUTSFEN 0x20
169
-#define TFTCTL_TSFCNTRRD 0x10
170
-#define TFTCTL_TBTTSYNCEN 0x08
171
-#define TFTCTL_TSFSYNCEN 0x04
172
-#define TFTCTL_TSFCNTRST 0x02
173
-#define TFTCTL_TSFCNTREN 0x01
167
+#define TFTCTL_HWUTSF BIT(7)
168
+#define TFTCTL_TBTTSYNC BIT(6)
169
+#define TFTCTL_HWUTSFEN BIT(5)
170
+#define TFTCTL_TSFCNTRRD BIT(4)
171
+#define TFTCTL_TBTTSYNCEN BIT(3)
172
+#define TFTCTL_TSFSYNCEN BIT(2)
173
+#define TFTCTL_TSFCNTRST BIT(1)
174
+#define TFTCTL_TSFCNTREN BIT(0)
174175
175176 /* Bits in the EnhanceCFG_0 register */
176177 #define EnCFG_BBType_a 0x00
177
-#define EnCFG_BBType_b 0x01
178
-#define EnCFG_BBType_g 0x02
179
-#define EnCFG_BBType_MASK 0x03
180
-#define EnCFG_ProtectMd 0x20
178
+#define EnCFG_BBType_b BIT(0)
179
+#define EnCFG_BBType_g BIT(1)
180
+#define EnCFG_BBType_MASK (EnCFG_BBType_b | EnCFG_BBType_g)
181
+#define EnCFG_ProtectMd BIT(5)
181182
182183 /* Bits in the EnhanceCFG_1 register */
183
-#define EnCFG_BcnSusInd 0x01
184
-#define EnCFG_BcnSusClr 0x02
184
+#define EnCFG_BcnSusInd BIT(0)
185
+#define EnCFG_BcnSusClr BIT(1)
185186
186187 /* Bits in the EnhanceCFG_2 register */
187
-#define EnCFG_NXTBTTCFPSTR 0x01
188
-#define EnCFG_BarkerPream 0x02
189
-#define EnCFG_PktBurstMode 0x04
188
+#define EnCFG_NXTBTTCFPSTR BIT(0)
189
+#define EnCFG_BarkerPream BIT(1)
190
+#define EnCFG_PktBurstMode BIT(2)
190191
191192 /* Bits in the CFG register */
192
-#define CFG_TKIPOPT 0x80
193
-#define CFG_RXDMAOPT 0x40
194
-#define CFG_TMOT_SW 0x20
195
-#define CFG_TMOT_HWLONG 0x10
193
+#define CFG_TKIPOPT BIT(7)
194
+#define CFG_RXDMAOPT BIT(6)
195
+#define CFG_TMOT_SW BIT(5)
196
+#define CFG_TMOT_HWLONG BIT(4)
196197 #define CFG_TMOT_HW 0x00
197
-#define CFG_CFPENDOPT 0x08
198
-#define CFG_BCNSUSEN 0x04
199
-#define CFG_NOTXTIMEOUT 0x02
200
-#define CFG_NOBUFOPT 0x01
198
+#define CFG_CFPENDOPT BIT(3)
199
+#define CFG_BCNSUSEN BIT(2)
200
+#define CFG_NOTXTIMEOUT BIT(1)
201
+#define CFG_NOBUFOPT BIT(0)
201202
202203 /* Bits in the TEST register */
203
-#define TEST_LBEXT 0x80
204
-#define TEST_LBINT 0x40
204
+#define TEST_LBEXT BIT(7)
205
+#define TEST_LBINT BIT(6)
205206 #define TEST_LBNONE 0x00
206
-#define TEST_SOFTINT 0x20
207
-#define TEST_CONTTX 0x10
208
-#define TEST_TXPE 0x08
209
-#define TEST_NAVDIS 0x04
210
-#define TEST_NOCTS 0x02
211
-#define TEST_NOACK 0x01
207
+#define TEST_SOFTINT BIT(5)
208
+#define TEST_CONTTX BIT(4)
209
+#define TEST_TXPE BIT(3)
210
+#define TEST_NAVDIS BIT(2)
211
+#define TEST_NOCTS BIT(1)
212
+#define TEST_NOACK BIT(0)
212213
213214 /* Bits in the HOSTCR register */
214
-#define HOSTCR_TXONST 0x80
215
-#define HOSTCR_RXONST 0x40
216
-#define HOSTCR_ADHOC 0x20
217
-#define HOSTCR_AP 0x10
218
-#define HOSTCR_TXON 0x08
219
-#define HOSTCR_RXON 0x04
220
-#define HOSTCR_MACEN 0x02
221
-#define HOSTCR_SOFTRST 0x01
215
+#define HOSTCR_TXONST BIT(7)
216
+#define HOSTCR_RXONST BIT(6)
217
+#define HOSTCR_ADHOC BIT(5)
218
+#define HOSTCR_AP BIT(4)
219
+#define HOSTCR_TXON BIT(3)
220
+#define HOSTCR_RXON BIT(2)
221
+#define HOSTCR_MACEN BIT(1)
222
+#define HOSTCR_SOFTRST BIT(0)
222223
223224 /* Bits in the MACCR register */
224
-#define MACCR_SYNCFLUSHOK 0x04
225
-#define MACCR_SYNCFLUSH 0x02
226
-#define MACCR_CLRNAV 0x01
225
+#define MACCR_SYNCFLUSHOK BIT(2)
226
+#define MACCR_SYNCFLUSH BIT(1)
227
+#define MACCR_CLRNAV BIT(0)
227228
228229 /* Bits in the RCR register */
229
-#define RCR_SSID 0x80
230
-#define RCR_RXALLTYPE 0x40
231
-#define RCR_UNICAST 0x20
232
-#define RCR_BROADCAST 0x10
233
-#define RCR_MULTICAST 0x08
234
-#define RCR_WPAERR 0x04
235
-#define RCR_ERRCRC 0x02
236
-#define RCR_BSSID 0x01
230
+#define RCR_SSID BIT(7)
231
+#define RCR_RXALLTYPE BIT(6)
232
+#define RCR_UNICAST BIT(5)
233
+#define RCR_BROADCAST BIT(4)
234
+#define RCR_MULTICAST BIT(3)
235
+#define RCR_WPAERR BIT(2)
236
+#define RCR_ERRCRC BIT(1)
237
+#define RCR_BSSID BIT(0)
237238
238239 /* Bits in the TCR register */
239
-#define TCR_SYNCDCFOPT 0x02
240
-#define TCR_AUTOBCNTX 0x01
240
+#define TCR_SYNCDCFOPT BIT(1)
241
+#define TCR_AUTOBCNTX BIT(0)
241242
242243 /* ISR1 */
243
-#define ISR_GPIO3 0x40
244
-#define ISR_RXNOBUF 0x08
245
-#define ISR_MIBNEARFULL 0x04
246
-#define ISR_SOFTINT 0x02
247
-#define ISR_FETALERR 0x01
244
+#define ISR_GPIO3 BIT(6)
245
+#define ISR_RXNOBUF BIT(3)
246
+#define ISR_MIBNEARFULL BIT(2)
247
+#define ISR_SOFTINT BIT(1)
248
+#define ISR_FETALERR BIT(0)
248249
249250 #define LEDSTS_STS 0x06
250251 #define LEDSTS_TMLEN 0x78
....@@ -254,85 +255,85 @@
254255 #define LEDSTS_INTER 0x06
255256
256257 /* ISR0 */
257
-#define ISR_WATCHDOG 0x80
258
-#define ISR_SOFTTIMER 0x40
259
-#define ISR_GPIO0 0x20
260
-#define ISR_TBTT 0x10
261
-#define ISR_RXDMA0 0x08
262
-#define ISR_BNTX 0x04
263
-#define ISR_ACTX 0x01
258
+#define ISR_WATCHDOG BIT(7)
259
+#define ISR_SOFTTIMER BIT(6)
260
+#define ISR_GPIO0 BIT(5)
261
+#define ISR_TBTT BIT(4)
262
+#define ISR_RXDMA0 BIT(3)
263
+#define ISR_BNTX BIT(2)
264
+#define ISR_ACTX BIT(0)
264265
265266 /* Bits in the PSCFG register */
266
-#define PSCFG_PHILIPMD 0x40
267
-#define PSCFG_WAKECALEN 0x20
268
-#define PSCFG_WAKETMREN 0x10
269
-#define PSCFG_BBPSPROG 0x08
270
-#define PSCFG_WAKESYN 0x04
271
-#define PSCFG_SLEEPSYN 0x02
272
-#define PSCFG_AUTOSLEEP 0x01
267
+#define PSCFG_PHILIPMD BIT(6)
268
+#define PSCFG_WAKECALEN BIT(5)
269
+#define PSCFG_WAKETMREN BIT(4)
270
+#define PSCFG_BBPSPROG BIT(3)
271
+#define PSCFG_WAKESYN BIT(2)
272
+#define PSCFG_SLEEPSYN BIT(1)
273
+#define PSCFG_AUTOSLEEP BIT(0)
273274
274275 /* Bits in the PSCTL register */
275
-#define PSCTL_WAKEDONE 0x20
276
-#define PSCTL_PS 0x10
277
-#define PSCTL_GO2DOZE 0x08
278
-#define PSCTL_LNBCN 0x04
279
-#define PSCTL_ALBCN 0x02
280
-#define PSCTL_PSEN 0x01
276
+#define PSCTL_WAKEDONE BIT(5)
277
+#define PSCTL_PS BIT(4)
278
+#define PSCTL_GO2DOZE BIT(3)
279
+#define PSCTL_LNBCN BIT(2)
280
+#define PSCTL_ALBCN BIT(1)
281
+#define PSCTL_PSEN BIT(0)
281282
282283 /* Bits in the PSPWSIG register */
283
-#define PSSIG_WPE3 0x80
284
-#define PSSIG_WPE2 0x40
285
-#define PSSIG_WPE1 0x20
286
-#define PSSIG_WRADIOPE 0x10
287
-#define PSSIG_SPE3 0x08
288
-#define PSSIG_SPE2 0x04
289
-#define PSSIG_SPE1 0x02
290
-#define PSSIG_SRADIOPE 0x01
284
+#define PSSIG_WPE3 BIT(7)
285
+#define PSSIG_WPE2 BIT(6)
286
+#define PSSIG_WPE1 BIT(5)
287
+#define PSSIG_WRADIOPE BIT(4)
288
+#define PSSIG_SPE3 BIT(3)
289
+#define PSSIG_SPE2 BIT(2)
290
+#define PSSIG_SPE1 BIT(1)
291
+#define PSSIG_SRADIOPE BIT(0)
291292
292293 /* Bits in the BBREGCTL register */
293
-#define BBREGCTL_DONE 0x04
294
-#define BBREGCTL_REGR 0x02
295
-#define BBREGCTL_REGW 0x01
294
+#define BBREGCTL_DONE BIT(2)
295
+#define BBREGCTL_REGR BIT(1)
296
+#define BBREGCTL_REGW BIT(0)
296297
297298 /* Bits in the IFREGCTL register */
298
-#define IFREGCTL_DONE 0x04
299
-#define IFREGCTL_IFRF 0x02
300
-#define IFREGCTL_REGW 0x01
299
+#define IFREGCTL_DONE BIT(2)
300
+#define IFREGCTL_IFRF BIT(1)
301
+#define IFREGCTL_REGW BIT(0)
301302
302303 /* Bits in the SOFTPWRCTL register */
303
-#define SOFTPWRCTL_RFLEOPT 0x08
304
-#define SOFTPWRCTL_TXPEINV 0x02
305
-#define SOFTPWRCTL_SWPECTI 0x01
306
-#define SOFTPWRCTL_SWPAPE 0x20
307
-#define SOFTPWRCTL_SWCALEN 0x10
308
-#define SOFTPWRCTL_SWRADIO_PE 0x08
309
-#define SOFTPWRCTL_SWPE2 0x04
310
-#define SOFTPWRCTL_SWPE1 0x02
311
-#define SOFTPWRCTL_SWPE3 0x01
304
+#define SOFTPWRCTL_RFLEOPT BIT(3)
305
+#define SOFTPWRCTL_TXPEINV BIT(1)
306
+#define SOFTPWRCTL_SWPECTI BIT(0)
307
+#define SOFTPWRCTL_SWPAPE BIT(5)
308
+#define SOFTPWRCTL_SWCALEN BIT(4)
309
+#define SOFTPWRCTL_SWRADIO_PE BIT(3)
310
+#define SOFTPWRCTL_SWPE2 BIT(2)
311
+#define SOFTPWRCTL_SWPE1 BIT(1)
312
+#define SOFTPWRCTL_SWPE3 BIT(0)
312313
313314 /* Bits in the GPIOCTL1 register */
314
-#define GPIO3_MD 0x20
315
-#define GPIO3_DATA 0x40
316
-#define GPIO3_INTMD 0x80
315
+#define GPIO3_MD BIT(5)
316
+#define GPIO3_DATA BIT(6)
317
+#define GPIO3_INTMD BIT(7)
317318
318319 /* Bits in the MISCFFCTL register */
319
-#define MISCFFCTL_WRITE 0x0001
320
+#define MISCFFCTL_WRITE BIT(0)
320321
321322 /* Loopback mode */
322
-#define MAC_LB_EXT 0x02
323
-#define MAC_LB_INTERNAL 0x01
323
+#define MAC_LB_EXT BIT(1)
324
+#define MAC_LB_INTERNAL BIT(0)
324325 #define MAC_LB_NONE 0x00
325326
326327 /* Ethernet address filter type */
327328 #define PKT_TYPE_NONE 0x00 /* turn off receiver */
328
-#define PKT_TYPE_ALL_MULTICAST 0x80
329
-#define PKT_TYPE_PROMISCUOUS 0x40
330
-#define PKT_TYPE_DIRECTED 0x20 /* obselete */
331
-#define PKT_TYPE_BROADCAST 0x10
332
-#define PKT_TYPE_MULTICAST 0x08
333
-#define PKT_TYPE_ERROR_WPA 0x04
334
-#define PKT_TYPE_ERROR_CRC 0x02
335
-#define PKT_TYPE_BSSID 0x01
329
+#define PKT_TYPE_ALL_MULTICAST BIT(7)
330
+#define PKT_TYPE_PROMISCUOUS BIT(6)
331
+#define PKT_TYPE_DIRECTED BIT(5) /* obselete */
332
+#define PKT_TYPE_BROADCAST BIT(4)
333
+#define PKT_TYPE_MULTICAST BIT(3)
334
+#define PKT_TYPE_ERROR_WPA BIT(2)
335
+#define PKT_TYPE_ERROR_CRC BIT(1)
336
+#define PKT_TYPE_BSSID BIT(0)
336337
337338 #define Default_BI 0x200
338339
....@@ -354,21 +355,21 @@
354355 u8 key[WLAN_KEY_LEN_CCMP];
355356 } __packed;
356357
357
-void vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter);
358
-void vnt_mac_shutdown(struct vnt_private *priv);
359
-void vnt_mac_set_bb_type(struct vnt_private *priv, u8 type);
360
-void vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx);
361
-void vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx,
362
- u32 key_idx, u8 *addr, u8 *key);
363
-void vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
364
-void vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
365
-void vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);
366
-void vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr);
367
-void vnt_mac_enable_protect_mode(struct vnt_private *priv);
368
-void vnt_mac_disable_protect_mode(struct vnt_private *priv);
369
-void vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv);
370
-void vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv);
371
-void vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval);
372
-void vnt_mac_set_led(struct vnt_private *privpriv, u8 state, u8 led);
358
+int vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter);
359
+int vnt_mac_shutdown(struct vnt_private *priv);
360
+int vnt_mac_set_bb_type(struct vnt_private *priv, u8 type);
361
+int vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx);
362
+int vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx,
363
+ u32 key_idx, u8 *addr, u8 *key);
364
+int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
365
+int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
366
+int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);
367
+int vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr);
368
+int vnt_mac_enable_protect_mode(struct vnt_private *priv);
369
+int vnt_mac_disable_protect_mode(struct vnt_private *priv);
370
+int vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv);
371
+int vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv);
372
+int vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval);
373
+int vnt_mac_set_led(struct vnt_private *privpriv, u8 state, u8 led);
373374
374375 #endif /* __MAC_H__ */