.. | .. |
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1 | | -// SPDX-License-Identifier: GPL-2.0+ |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | 2 | /* |
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3 | 3 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. |
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4 | 4 | * All rights reserved. |
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.. | .. |
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20 | 20 | #ifndef __MAC_H__ |
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21 | 21 | #define __MAC_H__ |
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22 | 22 | |
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| 23 | +#include <linux/bits.h> |
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23 | 24 | #include "device.h" |
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24 | 25 | |
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25 | 26 | #define REV_ID_VT3253_A0 0x00 |
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.. | .. |
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142 | 143 | #define MAC_REG_RSPINF_A_72 0xfc |
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143 | 144 | |
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144 | 145 | /* Bits in the I2MCFG EEPROM register */ |
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145 | | -#define I2MCFG_BOUNDCTL 0x80 |
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146 | | -#define I2MCFG_WAITCTL 0x20 |
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147 | | -#define I2MCFG_SCLOECTL 0x10 |
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148 | | -#define I2MCFG_WBUSYCTL 0x08 |
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149 | | -#define I2MCFG_NORETRY 0x04 |
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150 | | -#define I2MCFG_I2MLDSEQ 0x02 |
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151 | | -#define I2MCFG_I2CMFAST 0x01 |
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| 146 | +#define I2MCFG_BOUNDCTL BIT(7) |
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| 147 | +#define I2MCFG_WAITCTL BIT(5) |
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| 148 | +#define I2MCFG_SCLOECTL BIT(4) |
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| 149 | +#define I2MCFG_WBUSYCTL BIT(3) |
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| 150 | +#define I2MCFG_NORETRY BIT(2) |
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| 151 | +#define I2MCFG_I2MLDSEQ BIT(1) |
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| 152 | +#define I2MCFG_I2CMFAST BIT(0) |
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152 | 153 | |
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153 | 154 | /* Bits in the I2MCSR EEPROM register */ |
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154 | | -#define I2MCSR_EEMW 0x80 |
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155 | | -#define I2MCSR_EEMR 0x40 |
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156 | | -#define I2MCSR_AUTOLD 0x08 |
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157 | | -#define I2MCSR_NACK 0x02 |
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158 | | -#define I2MCSR_DONE 0x01 |
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| 155 | +#define I2MCSR_EEMW BIT(7) |
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| 156 | +#define I2MCSR_EEMR BIT(6) |
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| 157 | +#define I2MCSR_AUTOLD BIT(3) |
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| 158 | +#define I2MCSR_NACK BIT(1) |
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| 159 | +#define I2MCSR_DONE BIT(0) |
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159 | 160 | |
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160 | 161 | /* Bits in the TMCTL register */ |
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161 | | -#define TMCTL_TSUSP 0x04 |
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162 | | -#define TMCTL_TMD 0x02 |
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163 | | -#define TMCTL_TE 0x01 |
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| 162 | +#define TMCTL_TSUSP BIT(2) |
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| 163 | +#define TMCTL_TMD BIT(1) |
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| 164 | +#define TMCTL_TE BIT(0) |
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164 | 165 | |
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165 | 166 | /* Bits in the TFTCTL register */ |
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166 | | -#define TFTCTL_HWUTSF 0x80 |
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167 | | -#define TFTCTL_TBTTSYNC 0x40 |
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168 | | -#define TFTCTL_HWUTSFEN 0x20 |
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169 | | -#define TFTCTL_TSFCNTRRD 0x10 |
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170 | | -#define TFTCTL_TBTTSYNCEN 0x08 |
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171 | | -#define TFTCTL_TSFSYNCEN 0x04 |
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172 | | -#define TFTCTL_TSFCNTRST 0x02 |
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173 | | -#define TFTCTL_TSFCNTREN 0x01 |
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| 167 | +#define TFTCTL_HWUTSF BIT(7) |
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| 168 | +#define TFTCTL_TBTTSYNC BIT(6) |
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| 169 | +#define TFTCTL_HWUTSFEN BIT(5) |
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| 170 | +#define TFTCTL_TSFCNTRRD BIT(4) |
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| 171 | +#define TFTCTL_TBTTSYNCEN BIT(3) |
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| 172 | +#define TFTCTL_TSFSYNCEN BIT(2) |
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| 173 | +#define TFTCTL_TSFCNTRST BIT(1) |
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| 174 | +#define TFTCTL_TSFCNTREN BIT(0) |
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174 | 175 | |
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175 | 176 | /* Bits in the EnhanceCFG_0 register */ |
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176 | 177 | #define EnCFG_BBType_a 0x00 |
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177 | | -#define EnCFG_BBType_b 0x01 |
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178 | | -#define EnCFG_BBType_g 0x02 |
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179 | | -#define EnCFG_BBType_MASK 0x03 |
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180 | | -#define EnCFG_ProtectMd 0x20 |
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| 178 | +#define EnCFG_BBType_b BIT(0) |
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| 179 | +#define EnCFG_BBType_g BIT(1) |
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| 180 | +#define EnCFG_BBType_MASK (EnCFG_BBType_b | EnCFG_BBType_g) |
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| 181 | +#define EnCFG_ProtectMd BIT(5) |
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181 | 182 | |
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182 | 183 | /* Bits in the EnhanceCFG_1 register */ |
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183 | | -#define EnCFG_BcnSusInd 0x01 |
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184 | | -#define EnCFG_BcnSusClr 0x02 |
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| 184 | +#define EnCFG_BcnSusInd BIT(0) |
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| 185 | +#define EnCFG_BcnSusClr BIT(1) |
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185 | 186 | |
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186 | 187 | /* Bits in the EnhanceCFG_2 register */ |
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187 | | -#define EnCFG_NXTBTTCFPSTR 0x01 |
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188 | | -#define EnCFG_BarkerPream 0x02 |
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189 | | -#define EnCFG_PktBurstMode 0x04 |
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| 188 | +#define EnCFG_NXTBTTCFPSTR BIT(0) |
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| 189 | +#define EnCFG_BarkerPream BIT(1) |
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| 190 | +#define EnCFG_PktBurstMode BIT(2) |
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190 | 191 | |
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191 | 192 | /* Bits in the CFG register */ |
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192 | | -#define CFG_TKIPOPT 0x80 |
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193 | | -#define CFG_RXDMAOPT 0x40 |
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194 | | -#define CFG_TMOT_SW 0x20 |
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195 | | -#define CFG_TMOT_HWLONG 0x10 |
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| 193 | +#define CFG_TKIPOPT BIT(7) |
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| 194 | +#define CFG_RXDMAOPT BIT(6) |
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| 195 | +#define CFG_TMOT_SW BIT(5) |
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| 196 | +#define CFG_TMOT_HWLONG BIT(4) |
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196 | 197 | #define CFG_TMOT_HW 0x00 |
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197 | | -#define CFG_CFPENDOPT 0x08 |
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198 | | -#define CFG_BCNSUSEN 0x04 |
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199 | | -#define CFG_NOTXTIMEOUT 0x02 |
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200 | | -#define CFG_NOBUFOPT 0x01 |
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| 198 | +#define CFG_CFPENDOPT BIT(3) |
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| 199 | +#define CFG_BCNSUSEN BIT(2) |
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| 200 | +#define CFG_NOTXTIMEOUT BIT(1) |
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| 201 | +#define CFG_NOBUFOPT BIT(0) |
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201 | 202 | |
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202 | 203 | /* Bits in the TEST register */ |
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203 | | -#define TEST_LBEXT 0x80 |
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204 | | -#define TEST_LBINT 0x40 |
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| 204 | +#define TEST_LBEXT BIT(7) |
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| 205 | +#define TEST_LBINT BIT(6) |
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205 | 206 | #define TEST_LBNONE 0x00 |
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206 | | -#define TEST_SOFTINT 0x20 |
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207 | | -#define TEST_CONTTX 0x10 |
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208 | | -#define TEST_TXPE 0x08 |
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209 | | -#define TEST_NAVDIS 0x04 |
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210 | | -#define TEST_NOCTS 0x02 |
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211 | | -#define TEST_NOACK 0x01 |
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| 207 | +#define TEST_SOFTINT BIT(5) |
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| 208 | +#define TEST_CONTTX BIT(4) |
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| 209 | +#define TEST_TXPE BIT(3) |
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| 210 | +#define TEST_NAVDIS BIT(2) |
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| 211 | +#define TEST_NOCTS BIT(1) |
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| 212 | +#define TEST_NOACK BIT(0) |
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212 | 213 | |
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213 | 214 | /* Bits in the HOSTCR register */ |
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214 | | -#define HOSTCR_TXONST 0x80 |
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215 | | -#define HOSTCR_RXONST 0x40 |
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216 | | -#define HOSTCR_ADHOC 0x20 |
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217 | | -#define HOSTCR_AP 0x10 |
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218 | | -#define HOSTCR_TXON 0x08 |
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219 | | -#define HOSTCR_RXON 0x04 |
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220 | | -#define HOSTCR_MACEN 0x02 |
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221 | | -#define HOSTCR_SOFTRST 0x01 |
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| 215 | +#define HOSTCR_TXONST BIT(7) |
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| 216 | +#define HOSTCR_RXONST BIT(6) |
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| 217 | +#define HOSTCR_ADHOC BIT(5) |
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| 218 | +#define HOSTCR_AP BIT(4) |
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| 219 | +#define HOSTCR_TXON BIT(3) |
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| 220 | +#define HOSTCR_RXON BIT(2) |
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| 221 | +#define HOSTCR_MACEN BIT(1) |
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| 222 | +#define HOSTCR_SOFTRST BIT(0) |
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222 | 223 | |
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223 | 224 | /* Bits in the MACCR register */ |
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224 | | -#define MACCR_SYNCFLUSHOK 0x04 |
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225 | | -#define MACCR_SYNCFLUSH 0x02 |
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226 | | -#define MACCR_CLRNAV 0x01 |
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| 225 | +#define MACCR_SYNCFLUSHOK BIT(2) |
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| 226 | +#define MACCR_SYNCFLUSH BIT(1) |
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| 227 | +#define MACCR_CLRNAV BIT(0) |
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227 | 228 | |
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228 | 229 | /* Bits in the RCR register */ |
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229 | | -#define RCR_SSID 0x80 |
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230 | | -#define RCR_RXALLTYPE 0x40 |
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231 | | -#define RCR_UNICAST 0x20 |
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232 | | -#define RCR_BROADCAST 0x10 |
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233 | | -#define RCR_MULTICAST 0x08 |
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234 | | -#define RCR_WPAERR 0x04 |
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235 | | -#define RCR_ERRCRC 0x02 |
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236 | | -#define RCR_BSSID 0x01 |
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| 230 | +#define RCR_SSID BIT(7) |
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| 231 | +#define RCR_RXALLTYPE BIT(6) |
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| 232 | +#define RCR_UNICAST BIT(5) |
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| 233 | +#define RCR_BROADCAST BIT(4) |
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| 234 | +#define RCR_MULTICAST BIT(3) |
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| 235 | +#define RCR_WPAERR BIT(2) |
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| 236 | +#define RCR_ERRCRC BIT(1) |
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| 237 | +#define RCR_BSSID BIT(0) |
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237 | 238 | |
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238 | 239 | /* Bits in the TCR register */ |
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239 | | -#define TCR_SYNCDCFOPT 0x02 |
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240 | | -#define TCR_AUTOBCNTX 0x01 |
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| 240 | +#define TCR_SYNCDCFOPT BIT(1) |
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| 241 | +#define TCR_AUTOBCNTX BIT(0) |
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241 | 242 | |
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242 | 243 | /* ISR1 */ |
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243 | | -#define ISR_GPIO3 0x40 |
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244 | | -#define ISR_RXNOBUF 0x08 |
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245 | | -#define ISR_MIBNEARFULL 0x04 |
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246 | | -#define ISR_SOFTINT 0x02 |
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247 | | -#define ISR_FETALERR 0x01 |
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| 244 | +#define ISR_GPIO3 BIT(6) |
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| 245 | +#define ISR_RXNOBUF BIT(3) |
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| 246 | +#define ISR_MIBNEARFULL BIT(2) |
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| 247 | +#define ISR_SOFTINT BIT(1) |
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| 248 | +#define ISR_FETALERR BIT(0) |
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248 | 249 | |
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249 | 250 | #define LEDSTS_STS 0x06 |
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250 | 251 | #define LEDSTS_TMLEN 0x78 |
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.. | .. |
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254 | 255 | #define LEDSTS_INTER 0x06 |
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255 | 256 | |
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256 | 257 | /* ISR0 */ |
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257 | | -#define ISR_WATCHDOG 0x80 |
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258 | | -#define ISR_SOFTTIMER 0x40 |
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259 | | -#define ISR_GPIO0 0x20 |
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260 | | -#define ISR_TBTT 0x10 |
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261 | | -#define ISR_RXDMA0 0x08 |
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262 | | -#define ISR_BNTX 0x04 |
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263 | | -#define ISR_ACTX 0x01 |
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| 258 | +#define ISR_WATCHDOG BIT(7) |
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| 259 | +#define ISR_SOFTTIMER BIT(6) |
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| 260 | +#define ISR_GPIO0 BIT(5) |
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| 261 | +#define ISR_TBTT BIT(4) |
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| 262 | +#define ISR_RXDMA0 BIT(3) |
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| 263 | +#define ISR_BNTX BIT(2) |
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| 264 | +#define ISR_ACTX BIT(0) |
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264 | 265 | |
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265 | 266 | /* Bits in the PSCFG register */ |
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266 | | -#define PSCFG_PHILIPMD 0x40 |
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267 | | -#define PSCFG_WAKECALEN 0x20 |
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268 | | -#define PSCFG_WAKETMREN 0x10 |
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269 | | -#define PSCFG_BBPSPROG 0x08 |
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270 | | -#define PSCFG_WAKESYN 0x04 |
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271 | | -#define PSCFG_SLEEPSYN 0x02 |
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272 | | -#define PSCFG_AUTOSLEEP 0x01 |
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| 267 | +#define PSCFG_PHILIPMD BIT(6) |
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| 268 | +#define PSCFG_WAKECALEN BIT(5) |
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| 269 | +#define PSCFG_WAKETMREN BIT(4) |
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| 270 | +#define PSCFG_BBPSPROG BIT(3) |
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| 271 | +#define PSCFG_WAKESYN BIT(2) |
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| 272 | +#define PSCFG_SLEEPSYN BIT(1) |
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| 273 | +#define PSCFG_AUTOSLEEP BIT(0) |
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273 | 274 | |
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274 | 275 | /* Bits in the PSCTL register */ |
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275 | | -#define PSCTL_WAKEDONE 0x20 |
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276 | | -#define PSCTL_PS 0x10 |
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277 | | -#define PSCTL_GO2DOZE 0x08 |
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278 | | -#define PSCTL_LNBCN 0x04 |
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279 | | -#define PSCTL_ALBCN 0x02 |
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280 | | -#define PSCTL_PSEN 0x01 |
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| 276 | +#define PSCTL_WAKEDONE BIT(5) |
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| 277 | +#define PSCTL_PS BIT(4) |
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| 278 | +#define PSCTL_GO2DOZE BIT(3) |
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| 279 | +#define PSCTL_LNBCN BIT(2) |
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| 280 | +#define PSCTL_ALBCN BIT(1) |
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| 281 | +#define PSCTL_PSEN BIT(0) |
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281 | 282 | |
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282 | 283 | /* Bits in the PSPWSIG register */ |
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283 | | -#define PSSIG_WPE3 0x80 |
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284 | | -#define PSSIG_WPE2 0x40 |
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285 | | -#define PSSIG_WPE1 0x20 |
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286 | | -#define PSSIG_WRADIOPE 0x10 |
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287 | | -#define PSSIG_SPE3 0x08 |
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288 | | -#define PSSIG_SPE2 0x04 |
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289 | | -#define PSSIG_SPE1 0x02 |
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290 | | -#define PSSIG_SRADIOPE 0x01 |
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| 284 | +#define PSSIG_WPE3 BIT(7) |
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| 285 | +#define PSSIG_WPE2 BIT(6) |
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| 286 | +#define PSSIG_WPE1 BIT(5) |
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| 287 | +#define PSSIG_WRADIOPE BIT(4) |
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| 288 | +#define PSSIG_SPE3 BIT(3) |
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| 289 | +#define PSSIG_SPE2 BIT(2) |
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| 290 | +#define PSSIG_SPE1 BIT(1) |
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| 291 | +#define PSSIG_SRADIOPE BIT(0) |
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291 | 292 | |
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292 | 293 | /* Bits in the BBREGCTL register */ |
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293 | | -#define BBREGCTL_DONE 0x04 |
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294 | | -#define BBREGCTL_REGR 0x02 |
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295 | | -#define BBREGCTL_REGW 0x01 |
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| 294 | +#define BBREGCTL_DONE BIT(2) |
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| 295 | +#define BBREGCTL_REGR BIT(1) |
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| 296 | +#define BBREGCTL_REGW BIT(0) |
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296 | 297 | |
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297 | 298 | /* Bits in the IFREGCTL register */ |
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298 | | -#define IFREGCTL_DONE 0x04 |
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299 | | -#define IFREGCTL_IFRF 0x02 |
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300 | | -#define IFREGCTL_REGW 0x01 |
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| 299 | +#define IFREGCTL_DONE BIT(2) |
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| 300 | +#define IFREGCTL_IFRF BIT(1) |
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| 301 | +#define IFREGCTL_REGW BIT(0) |
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301 | 302 | |
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302 | 303 | /* Bits in the SOFTPWRCTL register */ |
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303 | | -#define SOFTPWRCTL_RFLEOPT 0x08 |
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304 | | -#define SOFTPWRCTL_TXPEINV 0x02 |
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305 | | -#define SOFTPWRCTL_SWPECTI 0x01 |
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306 | | -#define SOFTPWRCTL_SWPAPE 0x20 |
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307 | | -#define SOFTPWRCTL_SWCALEN 0x10 |
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308 | | -#define SOFTPWRCTL_SWRADIO_PE 0x08 |
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309 | | -#define SOFTPWRCTL_SWPE2 0x04 |
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310 | | -#define SOFTPWRCTL_SWPE1 0x02 |
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311 | | -#define SOFTPWRCTL_SWPE3 0x01 |
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| 304 | +#define SOFTPWRCTL_RFLEOPT BIT(3) |
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| 305 | +#define SOFTPWRCTL_TXPEINV BIT(1) |
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| 306 | +#define SOFTPWRCTL_SWPECTI BIT(0) |
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| 307 | +#define SOFTPWRCTL_SWPAPE BIT(5) |
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| 308 | +#define SOFTPWRCTL_SWCALEN BIT(4) |
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| 309 | +#define SOFTPWRCTL_SWRADIO_PE BIT(3) |
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| 310 | +#define SOFTPWRCTL_SWPE2 BIT(2) |
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| 311 | +#define SOFTPWRCTL_SWPE1 BIT(1) |
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| 312 | +#define SOFTPWRCTL_SWPE3 BIT(0) |
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312 | 313 | |
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313 | 314 | /* Bits in the GPIOCTL1 register */ |
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314 | | -#define GPIO3_MD 0x20 |
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315 | | -#define GPIO3_DATA 0x40 |
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316 | | -#define GPIO3_INTMD 0x80 |
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| 315 | +#define GPIO3_MD BIT(5) |
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| 316 | +#define GPIO3_DATA BIT(6) |
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| 317 | +#define GPIO3_INTMD BIT(7) |
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317 | 318 | |
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318 | 319 | /* Bits in the MISCFFCTL register */ |
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319 | | -#define MISCFFCTL_WRITE 0x0001 |
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| 320 | +#define MISCFFCTL_WRITE BIT(0) |
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320 | 321 | |
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321 | 322 | /* Loopback mode */ |
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322 | | -#define MAC_LB_EXT 0x02 |
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323 | | -#define MAC_LB_INTERNAL 0x01 |
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| 323 | +#define MAC_LB_EXT BIT(1) |
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| 324 | +#define MAC_LB_INTERNAL BIT(0) |
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324 | 325 | #define MAC_LB_NONE 0x00 |
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325 | 326 | |
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326 | 327 | /* Ethernet address filter type */ |
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327 | 328 | #define PKT_TYPE_NONE 0x00 /* turn off receiver */ |
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328 | | -#define PKT_TYPE_ALL_MULTICAST 0x80 |
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329 | | -#define PKT_TYPE_PROMISCUOUS 0x40 |
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330 | | -#define PKT_TYPE_DIRECTED 0x20 /* obselete */ |
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331 | | -#define PKT_TYPE_BROADCAST 0x10 |
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332 | | -#define PKT_TYPE_MULTICAST 0x08 |
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333 | | -#define PKT_TYPE_ERROR_WPA 0x04 |
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334 | | -#define PKT_TYPE_ERROR_CRC 0x02 |
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335 | | -#define PKT_TYPE_BSSID 0x01 |
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| 329 | +#define PKT_TYPE_ALL_MULTICAST BIT(7) |
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| 330 | +#define PKT_TYPE_PROMISCUOUS BIT(6) |
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| 331 | +#define PKT_TYPE_DIRECTED BIT(5) /* obselete */ |
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| 332 | +#define PKT_TYPE_BROADCAST BIT(4) |
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| 333 | +#define PKT_TYPE_MULTICAST BIT(3) |
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| 334 | +#define PKT_TYPE_ERROR_WPA BIT(2) |
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| 335 | +#define PKT_TYPE_ERROR_CRC BIT(1) |
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| 336 | +#define PKT_TYPE_BSSID BIT(0) |
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336 | 337 | |
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337 | 338 | #define Default_BI 0x200 |
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338 | 339 | |
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.. | .. |
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354 | 355 | u8 key[WLAN_KEY_LEN_CCMP]; |
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355 | 356 | } __packed; |
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356 | 357 | |
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357 | | -void vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter); |
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358 | | -void vnt_mac_shutdown(struct vnt_private *priv); |
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359 | | -void vnt_mac_set_bb_type(struct vnt_private *priv, u8 type); |
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360 | | -void vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx); |
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361 | | -void vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx, |
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362 | | - u32 key_idx, u8 *addr, u8 *key); |
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363 | | -void vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits); |
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364 | | -void vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits); |
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365 | | -void vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word); |
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366 | | -void vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr); |
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367 | | -void vnt_mac_enable_protect_mode(struct vnt_private *priv); |
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368 | | -void vnt_mac_disable_protect_mode(struct vnt_private *priv); |
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369 | | -void vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv); |
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370 | | -void vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv); |
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371 | | -void vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval); |
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372 | | -void vnt_mac_set_led(struct vnt_private *privpriv, u8 state, u8 led); |
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| 358 | +int vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter); |
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| 359 | +int vnt_mac_shutdown(struct vnt_private *priv); |
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| 360 | +int vnt_mac_set_bb_type(struct vnt_private *priv, u8 type); |
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| 361 | +int vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx); |
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| 362 | +int vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx, |
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| 363 | + u32 key_idx, u8 *addr, u8 *key); |
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| 364 | +int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits); |
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| 365 | +int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits); |
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| 366 | +int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word); |
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| 367 | +int vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr); |
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| 368 | +int vnt_mac_enable_protect_mode(struct vnt_private *priv); |
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| 369 | +int vnt_mac_disable_protect_mode(struct vnt_private *priv); |
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| 370 | +int vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv); |
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| 371 | +int vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv); |
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| 372 | +int vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval); |
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| 373 | +int vnt_mac_set_led(struct vnt_private *privpriv, u8 state, u8 led); |
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373 | 374 | |
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374 | 375 | #endif /* __MAC_H__ */ |
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