.. | .. |
---|
1711 | 1711 | * Indicates an internal error was detected during |
---|
1712 | 1712 | * the BIST sequence. |
---|
1713 | 1713 | * @tdata_out: PHY Test Data Out. |
---|
1714 | | - * Presents either internaly generated signals or |
---|
| 1714 | + * Presents either internally generated signals or |
---|
1715 | 1715 | * test register contents, based upon the value of |
---|
1716 | 1716 | * test_data_out_sel. |
---|
1717 | 1717 | * @siddq: Drives the USBP (USB-PHY) SIDDQ input. |
---|
.. | .. |
---|
1737 | 1737 | * to D+. When an A/B device is acting as a host |
---|
1738 | 1738 | * (downstream-facing port), dp_pulldown and |
---|
1739 | 1739 | * dm_pulldown are enabled. This must not toggle |
---|
1740 | | - * during normal opeartion. |
---|
| 1740 | + * during normal operation. |
---|
1741 | 1741 | * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY. |
---|
1742 | 1742 | * This signal enables the pull-down resistance on |
---|
1743 | 1743 | * the D- line. '1' pull down-resistance is connected |
---|
.. | .. |
---|
1745 | 1745 | * to D-. When an A/B device is acting as a host |
---|
1746 | 1746 | * (downstream-facing port), dp_pulldown and |
---|
1747 | 1747 | * dm_pulldown are enabled. This must not toggle |
---|
1748 | | - * during normal opeartion. |
---|
| 1748 | + * during normal operation. |
---|
1749 | 1749 | * @hst_mode: When '0' the USB is acting as HOST, when '1' |
---|
1750 | 1750 | * USB is acting as device. This field needs to be |
---|
1751 | 1751 | * set while the USB is in reset. |
---|
.. | .. |
---|
1784 | 1784 | * Used to activate BIST in the PHY. |
---|
1785 | 1785 | * @tdata_sel: Test Data Out Select. |
---|
1786 | 1786 | * '1' test_data_out[3:0] (PHY) register contents |
---|
1787 | | - * are output. '0' internaly generated signals are |
---|
| 1787 | + * are output. '0' internally generated signals are |
---|
1788 | 1788 | * output. |
---|
1789 | 1789 | * @taddr_in: Mode Address for Test Interface. |
---|
1790 | 1790 | * Specifies the register address for writing to or |
---|
.. | .. |
---|
1797 | 1797 | * This is a test signal. When the USB Core is |
---|
1798 | 1798 | * powered up (not in Susned Mode), an automatic |
---|
1799 | 1799 | * tester can use this to disable phy_clock and |
---|
1800 | | - * free_clk, then re-eanable them with an aligned |
---|
| 1800 | + * free_clk, then re-enable them with an aligned |
---|
1801 | 1801 | * phase. |
---|
1802 | 1802 | * '1': The phy_clk and free_clk outputs are |
---|
1803 | 1803 | * disabled. "0": The phy_clock and free_clk outputs |
---|