hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/staging/octeon-usb/octeon-hcd.h
....@@ -1711,7 +1711,7 @@
17111711 * Indicates an internal error was detected during
17121712 * the BIST sequence.
17131713 * @tdata_out: PHY Test Data Out.
1714
- * Presents either internaly generated signals or
1714
+ * Presents either internally generated signals or
17151715 * test register contents, based upon the value of
17161716 * test_data_out_sel.
17171717 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
....@@ -1737,7 +1737,7 @@
17371737 * to D+. When an A/B device is acting as a host
17381738 * (downstream-facing port), dp_pulldown and
17391739 * dm_pulldown are enabled. This must not toggle
1740
- * during normal opeartion.
1740
+ * during normal operation.
17411741 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
17421742 * This signal enables the pull-down resistance on
17431743 * the D- line. '1' pull down-resistance is connected
....@@ -1745,7 +1745,7 @@
17451745 * to D-. When an A/B device is acting as a host
17461746 * (downstream-facing port), dp_pulldown and
17471747 * dm_pulldown are enabled. This must not toggle
1748
- * during normal opeartion.
1748
+ * during normal operation.
17491749 * @hst_mode: When '0' the USB is acting as HOST, when '1'
17501750 * USB is acting as device. This field needs to be
17511751 * set while the USB is in reset.
....@@ -1784,7 +1784,7 @@
17841784 * Used to activate BIST in the PHY.
17851785 * @tdata_sel: Test Data Out Select.
17861786 * '1' test_data_out[3:0] (PHY) register contents
1787
- * are output. '0' internaly generated signals are
1787
+ * are output. '0' internally generated signals are
17881788 * output.
17891789 * @taddr_in: Mode Address for Test Interface.
17901790 * Specifies the register address for writing to or
....@@ -1797,7 +1797,7 @@
17971797 * This is a test signal. When the USB Core is
17981798 * powered up (not in Susned Mode), an automatic
17991799 * tester can use this to disable phy_clock and
1800
- * free_clk, then re-eanable them with an aligned
1800
+ * free_clk, then re-enable them with an aligned
18011801 * phase.
18021802 * '1': The phy_clk and free_clk outputs are
18031803 * disabled. "0": The phy_clock and free_clk outputs