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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/staging/mt7621-pci/pci-mt7621.c
....@@ -1,33 +1,10 @@
11 // SPDX-License-Identifier: GPL-2.0+
2
-/**************************************************************************
3
- *
4
- *  BRIEF MODULE DESCRIPTION
2
+/*
3
+ * BRIEF MODULE DESCRIPTION
54  *     PCI init for Ralink RT2880 solution
65  *
7
- *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
6
+ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
87  *
9
- *  This program is free software; you can redistribute  it and/or modify it
10
- *  under  the terms of  the GNU General  Public License as published by the
11
- *  Free Software Foundation;  either version 2 of the  License, or (at your
12
- *  option) any later version.
13
- *
14
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
15
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
16
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
17
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
18
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
20
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
22
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24
- *
25
- *  You should have received a copy of the  GNU General Public License along
26
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
27
- *  675 Mass Ave, Cambridge, MA 02139, USA.
28
- *
29
- *
30
- **************************************************************************
318  * May 2007 Bruce Chang
329  * Initial Release
3310  *
....@@ -36,13 +13,12 @@
3613  *
3714  * May 2011 Bruce Chang
3815  * support RT6855/MT7620 PCIe
39
- *
40
- **************************************************************************
4116  */
4217 
4318 #include <linux/bitops.h>
44
-#include <linux/clk.h>
4519 #include <linux/delay.h>
20
+#include <linux/gpio/consumer.h>
21
+#include <linux/iopoll.h>
4622 #include <linux/module.h>
4723 #include <linux/of.h>
4824 #include <linux/of_address.h>
....@@ -50,36 +26,46 @@
5026 #include <linux/of_pci.h>
5127 #include <linux/of_platform.h>
5228 #include <linux/pci.h>
29
+#include <linux/phy/phy.h>
5330 #include <linux/platform_device.h>
5431 #include <linux/reset.h>
32
+#include <linux/sys_soc.h>
5533 #include <mt7621.h>
5634 #include <ralink_regs.h>
5735 
5836 #include "../../pci/pci.h"
5937 
60
-/*
61
- * These functions and structures provide the BIOS scan and mapping of the PCI
62
- * devices.
63
- */
38
+/* sysctl */
39
+#define MT7621_GPIO_MODE		0x60
6440 
65
-#define RALINK_PCIE0_CLK_EN		BIT(24)
66
-#define RALINK_PCIE1_CLK_EN		BIT(25)
67
-#define RALINK_PCIE2_CLK_EN		BIT(26)
41
+/* MediaTek specific configuration registers */
42
+#define PCIE_FTS_NUM			0x70c
43
+#define PCIE_FTS_NUM_MASK		GENMASK(15, 8)
44
+#define PCIE_FTS_NUM_L0(x)		(((x) & 0xff) << 8)
6845 
69
-#define RALINK_PCI_CONFIG_ADDR		0x20
70
-#define RALINK_PCI_CONFIG_DATA		0x24
71
-#define RALINK_PCI_MEMBASE		0x28
72
-#define RALINK_PCI_IOBASE		0x2C
73
-#define RALINK_PCIE0_RST		BIT(24)
74
-#define RALINK_PCIE1_RST		BIT(25)
75
-#define RALINK_PCIE2_RST		BIT(26)
46
+/* rt_sysc_membase relative registers */
47
+#define RALINK_CLKCFG1			0x30
7648 
49
+/* Host-PCI bridge registers */
7750 #define RALINK_PCI_PCICFG_ADDR		0x0000
7851 #define RALINK_PCI_PCIMSK_ADDR		0x000C
52
+#define RALINK_PCI_CONFIG_ADDR		0x0020
53
+#define RALINK_PCI_CONFIG_DATA		0x0024
54
+#define RALINK_PCI_MEMBASE		0x0028
55
+#define RALINK_PCI_IOBASE		0x002C
7956 
80
-#define RT6855_PCIE0_OFFSET		0x2000
81
-#define RT6855_PCIE1_OFFSET		0x3000
82
-#define RT6855_PCIE2_OFFSET		0x4000
57
+/* PCICFG virtual bridges */
58
+#define PCIE_P2P_CNT			3
59
+#define PCIE_P2P_BR_DEVNUM_SHIFT(p)	(16 + (p) * 4)
60
+#define PCIE_P2P_BR_DEVNUM0_SHIFT	PCIE_P2P_BR_DEVNUM_SHIFT(0)
61
+#define PCIE_P2P_BR_DEVNUM1_SHIFT	PCIE_P2P_BR_DEVNUM_SHIFT(1)
62
+#define PCIE_P2P_BR_DEVNUM2_SHIFT	PCIE_P2P_BR_DEVNUM_SHIFT(2)
63
+#define PCIE_P2P_BR_DEVNUM_MASK		0xf
64
+#define PCIE_P2P_BR_DEVNUM_MASK_FULL	(0xfff << PCIE_P2P_BR_DEVNUM0_SHIFT)
65
+
66
+/* PCIe RC control registers */
67
+#define MT7621_PCIE_OFFSET		0x2000
68
+#define MT7621_NEXT_PORT		0x1000
8369 
8470 #define RALINK_PCI_BAR0SETUP_ADDR	0x0010
8571 #define RALINK_PCI_IMBASEBAR0_ADDR	0x0018
....@@ -88,54 +74,42 @@
8874 #define RALINK_PCI_SUBID		0x0038
8975 #define RALINK_PCI_STATUS		0x0050
9076 
91
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
92
-#define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
77
+/* Some definition values */
78
+#define PCIE_REVISION_ID		BIT(0)
79
+#define PCIE_CLASS_CODE			(0x60400 << 8)
80
+#define PCIE_BAR_MAP_MAX		GENMASK(30, 16)
81
+#define PCIE_BAR_ENABLE			BIT(0)
82
+#define PCIE_PORT_INT_EN(x)		BIT(20 + (x))
83
+#define PCIE_PORT_CLK_EN(x)		BIT(24 + (x))
84
+#define PCIE_PORT_LINKUP		BIT(0)
9385 
94
-#define RALINK_PCI_MM_MAP_BASE		0x60000000
95
-#define RALINK_PCI_IO_MAP_BASE		0x1e160000
96
-
97
-#define ASSERT_SYSRST_PCIE(val)		\
98
-	do {								\
99
-		if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)	\
100
-			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
101
-		else							\
102
-			rt_sysc_m32(val, 0, RALINK_RSTCTRL);		\
103
-	} while (0)
104
-#define DEASSERT_SYSRST_PCIE(val)	\
105
-	do {								\
106
-		if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)	\
107
-			rt_sysc_m32(val, 0, RALINK_RSTCTRL);		\
108
-		else							\
109
-			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
110
-	} while (0)
111
-
112
-#define RALINK_CLKCFG1			0x30
113
-#define RALINK_RSTCTRL			0x34
114
-#define RALINK_GPIOMODE			0x60
115
-#define RALINK_PCIE_CLK_GEN		0x7c
116
-#define RALINK_PCIE_CLK_GEN1		0x80
117
-//RALINK_RSTCTRL bit
118
-#define RALINK_PCIE_RST			BIT(23)
119
-#define RALINK_PCI_RST			BIT(24)
120
-//RALINK_CLKCFG1 bit
121
-#define RALINK_PCI_CLK_EN		BIT(19)
122
-#define RALINK_PCIE_CLK_EN		BIT(21)
123
-
124
-#define MEMORY_BASE 0x0
125
-static int pcie_link_status = 0;
86
+#define MEMORY_BASE			0x0
87
+#define PERST_MODE_MASK			GENMASK(11, 10)
88
+#define PERST_MODE_GPIO			BIT(10)
89
+#define PERST_DELAY_MS			100
12690 
12791 /**
12892  * struct mt7621_pcie_port - PCIe port information
129
- * @base: IO mapped register base
93
+ * @base: I/O mapped register base
13094  * @list: port list
13195  * @pcie: pointer to PCIe host info
132
- * @reset: pointer to port reset control
96
+ * @phy: pointer to PHY control block
97
+ * @pcie_rst: pointer to port reset control
98
+ * @gpio_rst: gpio reset
99
+ * @slot: port slot
100
+ * @irq: GIC irq
101
+ * @enabled: indicates if port is enabled
133102  */
134103 struct mt7621_pcie_port {
135104 	void __iomem *base;
136105 	struct list_head list;
137106 	struct mt7621_pcie *pcie;
138
-	struct reset_control *reset;
107
+	struct phy *phy;
108
+	struct reset_control *pcie_rst;
109
+	struct gpio_desc *gpio_rst;
110
+	u32 slot;
111
+	int irq;
112
+	bool enabled;
139113 };
140114 
141115 /**
....@@ -146,7 +120,11 @@
146120  * @busn: bus range
147121  * @offset: IO / Memory offset
148122  * @dev: Pointer to PCIe device
123
+ * @io_map_base: virtual memory base address for io
149124  * @ports: pointer to PCIe port information
125
+ * @irq_map: irq mapping info according pcie link status
126
+ * @resets_inverted: depends on chip revision
127
+ * reset lines are inverted.
150128  */
151129 struct mt7621_pcie {
152130 	void __iomem *base;
....@@ -158,7 +136,10 @@
158136 		resource_size_t mem;
159137 		resource_size_t io;
160138 	} offset;
139
+	unsigned long io_map_base;
161140 	struct list_head ports;
141
+	int irq_map[PCIE_P2P_CNT];
142
+	bool resets_inverted;
162143 };
163144 
164145 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
....@@ -169,6 +150,26 @@
169150 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
170151 {
171152 	writel(val, pcie->base + reg);
153
+}
154
+
155
+static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
156
+{
157
+	u32 val = readl(pcie->base + reg);
158
+
159
+	val &= ~clr;
160
+	val |= set;
161
+	writel(val, pcie->base + reg);
162
+}
163
+
164
+static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
165
+{
166
+	return readl(port->base + reg);
167
+}
168
+
169
+static inline void pcie_port_write(struct mt7621_pcie_port *port,
170
+				   u32 val, u32 reg)
171
+{
172
+	writel(val, port->base + reg);
172173 }
173174 
174175 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
....@@ -196,8 +197,7 @@
196197 	.write		= pci_generic_config_write,
197198 };
198199 
199
-static u32
200
-read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
200
+static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
201201 {
202202 	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
203203 
....@@ -205,8 +205,8 @@
205205 	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
206206 }
207207 
208
-static void
209
-write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
208
+static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
209
+			 u32 reg, u32 val)
210210 {
211211 	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
212212 
....@@ -214,128 +214,83 @@
214214 	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
215215 }
216216 
217
-void
218
-set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
219
-	     int start_b, int bits, int val)
217
+static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
220218 {
221
-	u32 reg = pcie_read(pcie, offset);
222
-
223
-	reg &= ~(((1 << bits) - 1) << start_b);
224
-	reg |= val << start_b;
225
-	pcie_write(pcie, reg, offset);
219
+	if (port->gpio_rst)
220
+		gpiod_set_value(port->gpio_rst, 1);
226221 }
227222 
228
-void
229
-bypass_pipe_rst(struct mt7621_pcie *pcie)
223
+static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
230224 {
231
-	/* PCIe Port 0 */
232
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
233
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
234
-	/* PCIe Port 1 */
235
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
236
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
237
-	/* PCIe Port 2 */
238
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
239
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
225
+	if (port->gpio_rst)
226
+		gpiod_set_value(port->gpio_rst, 0);
240227 }
241228 
242
-void
243
-set_phy_for_ssc(struct mt7621_pcie *pcie)
229
+static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
244230 {
245
-	unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
246
-
247
-	reg = (reg >> 6) & 0x7;
248
-	/* Set PCIe Port0 & Port1 PHY to disable SSC */
249
-	/* Debug Xtal Type */
250
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
251
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
252
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
253
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 1 enable control
254
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
255
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 1 disable
256
-	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
257
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
258
-		printk("***** Xtal 40MHz *****\n");
259
-	} else {			// 25MHz | 20MHz Xtal
260
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
261
-		if (reg >= 6) {
262
-			printk("***** Xtal 25MHz *****\n");
263
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
264
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
265
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
266
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
267
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
268
-		} else {
269
-			printk("***** Xtal 20MHz *****\n");
270
-		}
271
-	}
272
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
273
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
274
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
275
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
276
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
277
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
278
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
279
-	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
280
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
281
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
282
-	}
283
-	/* Enable PHY and disable force mode */
284
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
285
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable
286
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
287
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control
288
-
289
-	/* Set PCIe Port2 PHY to disable SSC */
290
-	/* Debug Xtal Type */
291
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
292
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
293
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
294
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
295
-	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
296
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
297
-	} else {			// 25MHz | 20MHz Xtal
298
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
299
-		if (reg >= 6) {		// 25MHz Xtal
300
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
301
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
302
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
303
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
304
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
305
-		}
306
-	}
307
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
308
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
309
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
310
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
311
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
312
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
313
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
314
-	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
315
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
316
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
317
-	}
318
-	/* Enable PHY and disable force mode */
319
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
320
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
231
+	return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
321232 }
322233 
323
-static void setup_cm_memory_region(struct resource *mem_resource)
234
+static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port)
324235 {
236
+	rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1);
237
+}
238
+
239
+static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
240
+{
241
+	rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
242
+}
243
+
244
+static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
245
+{
246
+	struct mt7621_pcie *pcie = port->pcie;
247
+
248
+	if (pcie->resets_inverted)
249
+		reset_control_assert(port->pcie_rst);
250
+	else
251
+		reset_control_deassert(port->pcie_rst);
252
+}
253
+
254
+static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
255
+{
256
+	struct mt7621_pcie *pcie = port->pcie;
257
+
258
+	if (pcie->resets_inverted)
259
+		reset_control_deassert(port->pcie_rst);
260
+	else
261
+		reset_control_assert(port->pcie_rst);
262
+}
263
+
264
+static void setup_cm_memory_region(struct mt7621_pcie *pcie)
265
+{
266
+	struct resource *mem_resource = &pcie->mem;
267
+	struct device *dev = pcie->dev;
325268 	resource_size_t mask;
326269 
327270 	if (mips_cps_numiocu(0)) {
328
-		/* FIXME: hardware doesn't accept mask values with 1s after
271
+		/*
272
+		 * FIXME: hardware doesn't accept mask values with 1s after
329273 		 * 0s (e.g. 0xffef), so it would be great to warn if that's
330
-		 * about to happen */
274
+		 * about to happen
275
+		 */
331276 		mask = ~(mem_resource->end - mem_resource->start);
332277 
333278 		write_gcr_reg1_base(mem_resource->start);
334279 		write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
335
-		printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
280
+		dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
336281 			(unsigned long long)read_gcr_reg1_base(),
337282 			(unsigned long long)read_gcr_reg1_mask());
338283 	}
284
+}
285
+
286
+static int mt7621_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
287
+{
288
+	struct mt7621_pcie *pcie = pdev->bus->sysdata;
289
+	struct device *dev = pcie->dev;
290
+	int irq = pcie->irq_map[slot];
291
+
292
+	dev_info(dev, "bus=%d slot=%d irq=%d\n", pdev->bus->number, slot, irq);
293
+	return irq;
339294 }
340295 
341296 static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
....@@ -352,22 +307,21 @@
352307 	}
353308 
354309 	for_each_of_pci_range(&parser, &range) {
355
-		struct resource *res = NULL;
356
-
357310 		switch (range.flags & IORESOURCE_TYPE_BITS) {
358311 		case IORESOURCE_IO:
359
-			ioremap(range.cpu_addr, range.size);
360
-			res = &pcie->io;
312
+			pcie->io_map_base =
313
+				(unsigned long)ioremap(range.cpu_addr,
314
+						       range.size);
315
+			of_pci_range_to_resource(&range, node, &pcie->io);
316
+			pcie->io.start = range.cpu_addr;
317
+			pcie->io.end = range.cpu_addr + range.size - 1;
361318 			pcie->offset.io = 0x00000000UL;
362319 			break;
363320 		case IORESOURCE_MEM:
364
-			res = &pcie->mem;
321
+			of_pci_range_to_resource(&range, node, &pcie->mem);
365322 			pcie->offset.mem = 0x00000000UL;
366323 			break;
367324 		}
368
-
369
-		if (res != NULL)
370
-			of_pci_range_to_resource(&range, node, res);
371325 	}
372326 
373327 	err = of_pci_parse_bus_range(node, &pcie->busn);
....@@ -379,22 +333,77 @@
379333 		pcie->busn.flags = IORESOURCE_BUS;
380334 	}
381335 
336
+	set_io_port_base(pcie->io_map_base);
337
+
338
+	return 0;
339
+}
340
+
341
+static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
342
+				  struct device_node *node,
343
+				  int slot)
344
+{
345
+	struct mt7621_pcie_port *port;
346
+	struct device *dev = pcie->dev;
347
+	struct platform_device *pdev = to_platform_device(dev);
348
+	struct device_node *pnode = dev->of_node;
349
+	struct resource regs;
350
+	char name[10];
351
+	int err;
352
+
353
+	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
354
+	if (!port)
355
+		return -ENOMEM;
356
+
357
+	err = of_address_to_resource(pnode, slot + 1, &regs);
358
+	if (err) {
359
+		dev_err(dev, "missing \"reg\" property\n");
360
+		return err;
361
+	}
362
+
363
+	port->base = devm_ioremap_resource(dev, &regs);
364
+	if (IS_ERR(port->base))
365
+		return PTR_ERR(port->base);
366
+
367
+	snprintf(name, sizeof(name), "pcie%d", slot);
368
+	port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
369
+	if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
370
+		dev_err(dev, "failed to get pcie%d reset control\n", slot);
371
+		return PTR_ERR(port->pcie_rst);
372
+	}
373
+
374
+	snprintf(name, sizeof(name), "pcie-phy%d", slot);
375
+	port->phy = devm_phy_get(dev, name);
376
+	if (IS_ERR(port->phy) && slot != 1)
377
+		return PTR_ERR(port->phy);
378
+
379
+	port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
380
+						       GPIOD_OUT_LOW);
381
+	if (IS_ERR(port->gpio_rst)) {
382
+		dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
383
+		return PTR_ERR(port->gpio_rst);
384
+	}
385
+
386
+	port->slot = slot;
387
+	port->pcie = pcie;
388
+
389
+	port->irq = platform_get_irq(pdev, slot);
390
+	if (port->irq < 0) {
391
+		dev_err(dev, "Failed to get IRQ for PCIe%d\n", slot);
392
+		return -ENXIO;
393
+	}
394
+
395
+	INIT_LIST_HEAD(&port->list);
396
+	list_add_tail(&port->list, &pcie->ports);
397
+
382398 	return 0;
383399 }
384400 
385401 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
386402 {
387403 	struct device *dev = pcie->dev;
388
-	struct device_node *node = dev->of_node;
404
+	struct device_node *node = dev->of_node, *child;
389405 	struct resource regs;
390
-	const char *type;
391406 	int err;
392
-
393
-	type = of_get_property(node, "device_type", NULL);
394
-	if (!type || strcmp(type, "pci") != 0) {
395
-		dev_err(dev, "invalid \"device_type\" %s\n", type);
396
-		return -EINVAL;
397
-	}
398407 
399408 	err = of_address_to_resource(node, 0, &regs);
400409 	if (err) {
....@@ -406,24 +415,249 @@
406415 	if (IS_ERR(pcie->base))
407416 		return PTR_ERR(pcie->base);
408417 
418
+	for_each_available_child_of_node(node, child) {
419
+		int slot;
420
+
421
+		err = of_pci_get_devfn(child);
422
+		if (err < 0) {
423
+			of_node_put(child);
424
+			dev_err(dev, "failed to parse devfn: %d\n", err);
425
+			return err;
426
+		}
427
+
428
+		slot = PCI_SLOT(err);
429
+
430
+		err = mt7621_pcie_parse_port(pcie, child, slot);
431
+		if (err) {
432
+			of_node_put(child);
433
+			return err;
434
+		}
435
+	}
436
+
409437 	return 0;
410438 }
411439 
412
-static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
413
-					 struct list_head *res)
440
+static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
414441 {
442
+	struct mt7621_pcie *pcie = port->pcie;
415443 	struct device *dev = pcie->dev;
444
+	u32 slot = port->slot;
416445 	int err;
417446 
418
-	pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
419
-	pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
420
-	pci_add_resource(res, &pcie->busn);
421
-
422
-	err = devm_request_pci_bus_resources(dev, res);
423
-	if (err < 0)
447
+	err = phy_init(port->phy);
448
+	if (err) {
449
+		dev_err(dev, "failed to initialize port%d phy\n", slot);
424450 		return err;
451
+	}
452
+
453
+	err = phy_power_on(port->phy);
454
+	if (err) {
455
+		dev_err(dev, "failed to power on port%d phy\n", slot);
456
+		phy_exit(port->phy);
457
+		return err;
458
+	}
459
+
460
+	port->enabled = true;
425461 
426462 	return 0;
463
+}
464
+
465
+static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
466
+{
467
+	struct mt7621_pcie_port *port;
468
+
469
+	list_for_each_entry(port, &pcie->ports, list) {
470
+		/* PCIe RC reset assert */
471
+		mt7621_control_assert(port);
472
+
473
+		/* PCIe EP reset assert */
474
+		mt7621_rst_gpio_pcie_assert(port);
475
+	}
476
+
477
+	mdelay(PERST_DELAY_MS);
478
+}
479
+
480
+static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
481
+{
482
+	struct mt7621_pcie_port *port;
483
+
484
+	list_for_each_entry(port, &pcie->ports, list)
485
+		mt7621_control_deassert(port);
486
+}
487
+
488
+static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
489
+{
490
+	struct mt7621_pcie_port *port;
491
+
492
+	list_for_each_entry(port, &pcie->ports, list)
493
+		mt7621_rst_gpio_pcie_deassert(port);
494
+
495
+	mdelay(PERST_DELAY_MS);
496
+}
497
+
498
+static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
499
+{
500
+	struct device *dev = pcie->dev;
501
+	struct mt7621_pcie_port *port, *tmp;
502
+	int err;
503
+
504
+	rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
505
+
506
+	mt7621_pcie_reset_assert(pcie);
507
+	mt7621_pcie_reset_rc_deassert(pcie);
508
+
509
+	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
510
+		u32 slot = port->slot;
511
+
512
+		if (slot == 1) {
513
+			port->enabled = true;
514
+			continue;
515
+		}
516
+
517
+		err = mt7621_pcie_init_port(port);
518
+		if (err) {
519
+			dev_err(dev, "Initiating port %d failed\n", slot);
520
+			list_del(&port->list);
521
+		}
522
+	}
523
+
524
+	mt7621_pcie_reset_ep_deassert(pcie);
525
+
526
+	tmp = NULL;
527
+	list_for_each_entry(port, &pcie->ports, list) {
528
+		u32 slot = port->slot;
529
+
530
+		if (!mt7621_pcie_port_is_linkup(port)) {
531
+			dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
532
+				slot);
533
+			mt7621_control_assert(port);
534
+			mt7621_pcie_port_clk_disable(port);
535
+			port->enabled = false;
536
+
537
+			if (slot == 0) {
538
+				tmp = port;
539
+				continue;
540
+			}
541
+
542
+			if (slot == 1 && tmp && !tmp->enabled)
543
+				phy_power_off(tmp->phy);
544
+
545
+		}
546
+	}
547
+}
548
+
549
+static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
550
+{
551
+	struct mt7621_pcie *pcie = port->pcie;
552
+	u32 slot = port->slot;
553
+	u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
554
+	u32 val;
555
+
556
+	/* enable pcie interrupt */
557
+	val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
558
+	val |= PCIE_PORT_INT_EN(slot);
559
+	pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
560
+
561
+	/* map 2G DDR region */
562
+	pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
563
+		   offset + RALINK_PCI_BAR0SETUP_ADDR);
564
+	pcie_write(pcie, MEMORY_BASE,
565
+		   offset + RALINK_PCI_IMBASEBAR0_ADDR);
566
+
567
+	/* configure class code and revision ID */
568
+	pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
569
+		   offset + RALINK_PCI_CLASS);
570
+}
571
+
572
+static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
573
+{
574
+	struct device *dev = pcie->dev;
575
+	struct mt7621_pcie_port *port;
576
+	u8 num_slots_enabled = 0;
577
+	u32 slot;
578
+	u32 val;
579
+
580
+	/* Setup MEMWIN and IOWIN */
581
+	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
582
+	pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE);
583
+
584
+	list_for_each_entry(port, &pcie->ports, list) {
585
+		if (port->enabled) {
586
+			mt7621_pcie_port_clk_enable(port);
587
+			mt7621_pcie_enable_port(port);
588
+			dev_info(dev, "PCIE%d enabled\n", port->slot);
589
+			num_slots_enabled++;
590
+		}
591
+	}
592
+
593
+	for (slot = 0; slot < num_slots_enabled; slot++) {
594
+		val = read_config(pcie, slot, PCI_COMMAND);
595
+		val |= PCI_COMMAND_MASTER;
596
+		write_config(pcie, slot, PCI_COMMAND, val);
597
+		/* configure RC FTS number to 250 when it leaves L0s */
598
+		val = read_config(pcie, slot, PCIE_FTS_NUM);
599
+		val &= ~PCIE_FTS_NUM_MASK;
600
+		val |= PCIE_FTS_NUM_L0(0x50);
601
+		write_config(pcie, slot, PCIE_FTS_NUM, val);
602
+	}
603
+}
604
+
605
+static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
606
+{
607
+	u32 pcie_link_status = 0;
608
+	u32 n = 0;
609
+	int i = 0;
610
+	u32 p2p_br_devnum[PCIE_P2P_CNT];
611
+	int irqs[PCIE_P2P_CNT];
612
+	struct mt7621_pcie_port *port;
613
+
614
+	list_for_each_entry(port, &pcie->ports, list) {
615
+		u32 slot = port->slot;
616
+
617
+		irqs[i++] = port->irq;
618
+		if (port->enabled)
619
+			pcie_link_status |= BIT(slot);
620
+	}
621
+
622
+	if (pcie_link_status == 0)
623
+		return -1;
624
+
625
+	/*
626
+	 * Assign device numbers from zero to the enabled ports,
627
+	 * then assigning remaining device numbers to any disabled
628
+	 * ports.
629
+	 */
630
+	for (i = 0; i < PCIE_P2P_CNT; i++)
631
+		if (pcie_link_status & BIT(i))
632
+			p2p_br_devnum[i] = n++;
633
+
634
+	for (i = 0; i < PCIE_P2P_CNT; i++)
635
+		if ((pcie_link_status & BIT(i)) == 0)
636
+			p2p_br_devnum[i] = n++;
637
+
638
+	pcie_rmw(pcie, RALINK_PCI_PCICFG_ADDR,
639
+		 PCIE_P2P_BR_DEVNUM_MASK_FULL,
640
+		 (p2p_br_devnum[0] << PCIE_P2P_BR_DEVNUM0_SHIFT) |
641
+		 (p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) |
642
+		 (p2p_br_devnum[2] << PCIE_P2P_BR_DEVNUM2_SHIFT));
643
+
644
+	/* Assign IRQs */
645
+	n = 0;
646
+	for (i = 0; i < PCIE_P2P_CNT; i++)
647
+		if (pcie_link_status & BIT(i))
648
+			pcie->irq_map[n++] = irqs[i];
649
+
650
+	for (i = n; i < PCIE_P2P_CNT; i++)
651
+		pcie->irq_map[i] = -1;
652
+
653
+	return 0;
654
+}
655
+
656
+static void mt7621_pcie_add_resources(struct mt7621_pcie *pcie,
657
+				      struct list_head *res)
658
+{
659
+	pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
660
+	pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
427661 }
428662 
429663 static int mt7621_pcie_register_host(struct pci_host_bridge *host,
....@@ -435,20 +669,24 @@
435669 	host->busnr = pcie->busn.start;
436670 	host->dev.parent = pcie->dev;
437671 	host->ops = &mt7621_pci_ops;
438
-	host->map_irq = of_irq_parse_and_map_pci;
672
+	host->map_irq = mt7621_map_irq;
439673 	host->swizzle_irq = pci_common_swizzle;
440674 	host->sysdata = pcie;
441675 
442676 	return pci_host_probe(host);
443677 }
444678 
679
+static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
680
+	{ .soc_id = "mt7621", .revision = "E2" }
681
+};
682
+
445683 static int mt7621_pci_probe(struct platform_device *pdev)
446684 {
447685 	struct device *dev = &pdev->dev;
686
+	const struct soc_device_attribute *attr;
448687 	struct mt7621_pcie *pcie;
449688 	struct pci_host_bridge *bridge;
450689 	int err;
451
-	u32 val = 0;
452690 	LIST_HEAD(res);
453691 
454692 	if (!dev->of_node)
....@@ -456,225 +694,21 @@
456694 
457695 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
458696 	if (!bridge)
459
-		return -ENODEV;
697
+		return -ENOMEM;
460698 
461699 	pcie = pci_host_bridge_priv(bridge);
462700 	pcie->dev = dev;
463701 	platform_set_drvdata(pdev, pcie);
464702 	INIT_LIST_HEAD(&pcie->ports);
465703 
704
+	attr = soc_device_match(mt7621_pci_quirks_match);
705
+	if (attr)
706
+		pcie->resets_inverted = true;
707
+
466708 	err = mt7621_pcie_parse_dt(pcie);
467709 	if (err) {
468710 		dev_err(dev, "Parsing DT failed\n");
469711 		return err;
470
-	}
471
-
472
-	/* set resources limits */
473
-	iomem_resource.start = 0;
474
-	iomem_resource.end = ~0UL; /* no limit */
475
-	ioport_resource.start = 0;
476
-	ioport_resource.end = ~0UL; /* no limit */
477
-
478
-	val = RALINK_PCIE0_RST;
479
-	val |= RALINK_PCIE1_RST;
480
-	val |= RALINK_PCIE2_RST;
481
-
482
-	ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
483
-
484
-	*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
485
-	*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
486
-	mdelay(100);
487
-	*(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
488
-	mdelay(100);
489
-	*(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);		// clear DATA
490
-
491
-	mdelay(100);
492
-
493
-	val = RALINK_PCIE0_RST;
494
-	val |= RALINK_PCIE1_RST;
495
-	val |= RALINK_PCIE2_RST;
496
-
497
-	DEASSERT_SYSRST_PCIE(val);
498
-
499
-	if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
500
-		bypass_pipe_rst(pcie);
501
-	set_phy_for_ssc(pcie);
502
-
503
-	val = read_config(pcie, 0, 0x70c);
504
-	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
505
-
506
-	val = read_config(pcie, 1, 0x70c);
507
-	printk("Port 1 N_FTS = %x\n", (unsigned int)val);
508
-
509
-	val = read_config(pcie, 2, 0x70c);
510
-	printk("Port 2 N_FTS = %x\n", (unsigned int)val);
511
-
512
-	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
513
-	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
514
-
515
-	rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN);
516
-	rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1);
517
-	rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN);
518
-
519
-	mdelay(50);
520
-	rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
521
-
522
-	/* Use GPIO control instead of PERST_N */
523
-	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA
524
-	mdelay(1000);
525
-
526
-	if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
527
-		printk("PCIE0 no card, disable it(RST&CLK)\n");
528
-		ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
529
-		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
530
-		pcie_link_status &= ~(1<<0);
531
-	} else {
532
-		pcie_link_status |= 1<<0;
533
-		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
534
-		val |= (1<<20); // enable pcie1 interrupt
535
-		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
536
-	}
537
-
538
-	if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
539
-		printk("PCIE1 no card, disable it(RST&CLK)\n");
540
-		ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
541
-		rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
542
-		pcie_link_status &= ~(1<<1);
543
-	} else {
544
-		pcie_link_status |= 1<<1;
545
-		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
546
-		val |= (1<<21); // enable pcie1 interrupt
547
-		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
548
-	}
549
-
550
-	if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
551
-		printk("PCIE2 no card, disable it(RST&CLK)\n");
552
-		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
553
-		rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
554
-		pcie_link_status &= ~(1<<2);
555
-	} else {
556
-		pcie_link_status |= 1<<2;
557
-		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
558
-		val |= (1<<22); // enable pcie2 interrupt
559
-		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
560
-	}
561
-
562
-	if (pcie_link_status == 0)
563
-		return 0;
564
-
565
-/*
566
-pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
567
-3'b000			x		x		x
568
-3'b001			x		x		0
569
-3'b010			x		0		x
570
-3'b011			x		1		0
571
-3'b100			0		x		x
572
-3'b101			1		x		0
573
-3'b110			1		0		x
574
-3'b111			2		1		0
575
-*/
576
-	switch (pcie_link_status) {
577
-	case 2:
578
-		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
579
-		val &= ~0x00ff0000;
580
-		val |= 0x1 << 16;	// port 0
581
-		val |= 0x0 << 20;	// port 1
582
-		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
583
-		break;
584
-	case 4:
585
-		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
586
-		val &= ~0x0fff0000;
587
-		val |= 0x1 << 16;	//port0
588
-		val |= 0x2 << 20;	//port1
589
-		val |= 0x0 << 24;	//port2
590
-		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
591
-		break;
592
-	case 5:
593
-		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
594
-		val &= ~0x0fff0000;
595
-		val |= 0x0 << 16;	//port0
596
-		val |= 0x2 << 20;	//port1
597
-		val |= 0x1 << 24;	//port2
598
-		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
599
-		break;
600
-	case 6:
601
-		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
602
-		val &= ~0x0fff0000;
603
-		val |= 0x2 << 16;	//port0
604
-		val |= 0x0 << 20;	//port1
605
-		val |= 0x1 << 24;	//port2
606
-		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
607
-		break;
608
-	}
609
-
610
-/*
611
-	ioport_resource.start = mt7621_res_pci_io1.start;
612
-	ioport_resource.end = mt7621_res_pci_io1.end;
613
-*/
614
-
615
-	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
616
-	pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
617
-
618
-	//PCIe0
619
-	if ((pcie_link_status & 0x1) != 0) {
620
-		/* open 7FFF:2G; ENABLE */
621
-		pcie_write(pcie, 0x7FFF0001,
622
-			   RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
623
-		pcie_write(pcie, MEMORY_BASE,
624
-			   RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
625
-		pcie_write(pcie, 0x06040001,
626
-			   RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
627
-		printk("PCIE0 enabled\n");
628
-	}
629
-
630
-	//PCIe1
631
-	if ((pcie_link_status & 0x2) != 0) {
632
-		/* open 7FFF:2G; ENABLE */
633
-		pcie_write(pcie, 0x7FFF0001,
634
-			   RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
635
-		pcie_write(pcie, MEMORY_BASE,
636
-			   RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
637
-		pcie_write(pcie, 0x06040001,
638
-			   RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
639
-		printk("PCIE1 enabled\n");
640
-	}
641
-
642
-	//PCIe2
643
-	if ((pcie_link_status & 0x4) != 0) {
644
-		/* open 7FFF:2G; ENABLE */
645
-		pcie_write(pcie, 0x7FFF0001,
646
-			   RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
647
-		pcie_write(pcie, MEMORY_BASE,
648
-			   RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
649
-		pcie_write(pcie, 0x06040001,
650
-			   RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
651
-		printk("PCIE2 enabled\n");
652
-	}
653
-
654
-	switch (pcie_link_status) {
655
-	case 7:
656
-		val = read_config(pcie, 2, 0x4);
657
-		write_config(pcie, 2, 0x4, val|0x4);
658
-		val = read_config(pcie, 2, 0x70c);
659
-		val &= ~(0xff)<<8;
660
-		val |= 0x50<<8;
661
-		write_config(pcie, 2, 0x70c, val);
662
-	case 3:
663
-	case 5:
664
-	case 6:
665
-		val = read_config(pcie, 1, 0x4);
666
-		write_config(pcie, 1, 0x4, val|0x4);
667
-		val = read_config(pcie, 1, 0x70c);
668
-		val &= ~(0xff)<<8;
669
-		val |= 0x50<<8;
670
-		write_config(pcie, 1, 0x70c, val);
671
-	default:
672
-		val = read_config(pcie, 0, 0x4);
673
-		write_config(pcie, 0, 0x4, val|0x4); //bus master enable
674
-		val = read_config(pcie, 0, 0x70c);
675
-		val &= ~(0xff)<<8;
676
-		val |= 0x50<<8;
677
-		write_config(pcie, 0, 0x70c, val);
678712 	}
679713 
680714 	err = mt7621_pci_parse_request_of_pci_ranges(pcie);
....@@ -683,13 +717,23 @@
683717 		return err;
684718 	}
685719 
686
-	setup_cm_memory_region(&pcie->mem);
720
+	/* set resources limits */
721
+	ioport_resource.start = pcie->io.start;
722
+	ioport_resource.end = pcie->io.end;
687723 
688
-	err = mt7621_pcie_request_resources(pcie, &res);
724
+	mt7621_pcie_init_ports(pcie);
725
+
726
+	err = mt7621_pcie_init_virtual_bridges(pcie);
689727 	if (err) {
690
-		dev_err(dev, "Error requesting resources\n");
691
-		return err;
728
+		dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
729
+		return 0;
692730 	}
731
+
732
+	mt7621_pcie_enable_ports(pcie);
733
+
734
+	setup_cm_memory_region(pcie);
735
+
736
+	mt7621_pcie_add_resources(pcie, &res);
693737 
694738 	err = mt7621_pcie_register_host(bridge, &res);
695739 	if (err) {
....@@ -714,9 +758,4 @@
714758 	},
715759 };
716760 
717
-static int __init mt7621_pci_init(void)
718
-{
719
-	return platform_driver_register(&mt7621_pci_driver);
720
-}
721
-
722
-arch_initcall(mt7621_pci_init);
761
+builtin_platform_driver(mt7621_pci_driver);