add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/staging/most/dim2/hal.c
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@@ -13,6 +13,7 @@
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 #include "reg.h"
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 #include <linux/stddef.h>
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 #include <linux/kernel.h>
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+#include <linux/io.h>
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17
 
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 /*
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  * Size factor for isochronous DBR buffer.
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@@ -143,13 +144,13 @@
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144
 
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 static void dim2_transfer_madr(u32 val)
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 {
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-	dimcb_io_write(&g.dim2->MADR, val);
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+	writel(val, &g.dim2->MADR);
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 	/* wait for transfer completion */
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-	while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1)
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+	while ((readl(&g.dim2->MCTL) & 1) != 1)
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 		continue;
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-	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */
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+	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
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 }
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 static void dim2_clear_dbr(u16 addr, u16 size)
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@@ -159,8 +160,8 @@
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 	u16 const end_addr = addr + size;
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 	u32 const cmd = bit_mask(MADR_WNR_BIT) | bit_mask(MADR_TB_BIT);
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-	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */
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-	dimcb_io_write(&g.dim2->MDAT0, 0);
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+	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
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+	writel(0, &g.dim2->MDAT0);
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 	for (; addr < end_addr; addr++)
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 		dim2_transfer_madr(cmd | addr);
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@@ -170,28 +171,28 @@
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 {
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 	dim2_transfer_madr(ctr_addr);
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-	return dimcb_io_read((&g.dim2->MDAT0) + mdat_idx);
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+	return readl((&g.dim2->MDAT0) + mdat_idx);
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 }
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 static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value)
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 {
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 	enum { MADR_WNR_BIT = 31 };
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-	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */
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+	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
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 	if (mask[0] != 0)
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-		dimcb_io_write(&g.dim2->MDAT0, value[0]);
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+		writel(value[0], &g.dim2->MDAT0);
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 	if (mask[1] != 0)
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-		dimcb_io_write(&g.dim2->MDAT1, value[1]);
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+		writel(value[1], &g.dim2->MDAT1);
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 	if (mask[2] != 0)
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-		dimcb_io_write(&g.dim2->MDAT2, value[2]);
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+		writel(value[2], &g.dim2->MDAT2);
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 	if (mask[3] != 0)
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-		dimcb_io_write(&g.dim2->MDAT3, value[3]);
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+		writel(value[3], &g.dim2->MDAT3);
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-	dimcb_io_write(&g.dim2->MDWE0, mask[0]);
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-	dimcb_io_write(&g.dim2->MDWE1, mask[1]);
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-	dimcb_io_write(&g.dim2->MDWE2, mask[2]);
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-	dimcb_io_write(&g.dim2->MDWE3, mask[3]);
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+	writel(mask[0], &g.dim2->MDWE0);
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+	writel(mask[1], &g.dim2->MDWE1);
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+	writel(mask[2], &g.dim2->MDWE2);
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+	writel(mask[3], &g.dim2->MDWE3);
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 	dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr);
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 }
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@@ -356,15 +357,13 @@
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 	dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1);
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 	/* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */
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-	dimcb_io_write(&g.dim2->ACMR0,
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-		       dimcb_io_read(&g.dim2->ACMR0) | bit_mask(ch_addr));
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+	writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0);
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 }
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 static void dim2_clear_channel(u8 ch_addr)
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 {
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 	/* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */
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-	dimcb_io_write(&g.dim2->ACMR0,
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-		       dimcb_io_read(&g.dim2->ACMR0) & ~bit_mask(ch_addr));
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+	writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0);
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 	dim2_clear_cat(AHB_CAT, ch_addr);
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 	dim2_clear_adt(ch_addr);
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@@ -373,7 +372,7 @@
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 	dim2_clear_cdt(ch_addr);
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 	/* clear channel status bit */
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-	dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr));
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+	writel(bit_mask(ch_addr), &g.dim2->ACSR0);
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 }
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 /* -------------------------------------------------------------------------- */
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@@ -471,7 +470,7 @@
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 	return true;
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 }
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472
 
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-static inline u16 norm_ctrl_async_buffer_size(u16 buf_size)
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+u16 dim_norm_ctrl_async_buffer_size(u16 buf_size)
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 {
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 	u16 const max_size = (u16)ADT1_CTRL_ASYNC_BD_MASK + 1u;
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476
 
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@@ -517,20 +516,20 @@
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 static void dim2_cleanup(void)
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 {
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 	/* disable MediaLB */
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-	dimcb_io_write(&g.dim2->MLBC0, false << MLBC0_MLBEN_BIT);
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+	writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0);
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520
 
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 	dim2_clear_ctram();
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 	/* disable mlb_int interrupt */
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-	dimcb_io_write(&g.dim2->MIEN, 0);
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+	writel(0, &g.dim2->MIEN);
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525
 
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 	/* clear status for all dma channels */
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-	dimcb_io_write(&g.dim2->ACSR0, 0xFFFFFFFF);
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-	dimcb_io_write(&g.dim2->ACSR1, 0xFFFFFFFF);
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+	writel(0xFFFFFFFF, &g.dim2->ACSR0);
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+	writel(0xFFFFFFFF, &g.dim2->ACSR1);
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 	/* mask interrupts for all channels */
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-	dimcb_io_write(&g.dim2->ACMR0, 0);
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-	dimcb_io_write(&g.dim2->ACMR1, 0);
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+	writel(0, &g.dim2->ACMR0);
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+	writel(0, &g.dim2->ACMR1);
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 }
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534
 
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 static void dim2_initialize(bool enable_6pin, u8 mlb_clock)
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@@ -538,23 +537,22 @@
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 	dim2_cleanup();
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538
 
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 	/* configure and enable MediaLB */
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-	dimcb_io_write(&g.dim2->MLBC0,
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-		       enable_6pin << MLBC0_MLBPEN_BIT |
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-		       mlb_clock << MLBC0_MLBCLK_SHIFT |
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-		       g.fcnt << MLBC0_FCNT_SHIFT |
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-		       true << MLBC0_MLBEN_BIT);
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+	writel(enable_6pin << MLBC0_MLBPEN_BIT |
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+	       mlb_clock << MLBC0_MLBCLK_SHIFT |
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+	       g.fcnt << MLBC0_FCNT_SHIFT |
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+	       true << MLBC0_MLBEN_BIT,
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+	       &g.dim2->MLBC0);
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545
 
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 	/* activate all HBI channels */
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-	dimcb_io_write(&g.dim2->HCMR0, 0xFFFFFFFF);
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-	dimcb_io_write(&g.dim2->HCMR1, 0xFFFFFFFF);
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+	writel(0xFFFFFFFF, &g.dim2->HCMR0);
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+	writel(0xFFFFFFFF, &g.dim2->HCMR1);
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 	/* enable HBI */
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-	dimcb_io_write(&g.dim2->HCTL, bit_mask(HCTL_EN_BIT));
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+	writel(bit_mask(HCTL_EN_BIT), &g.dim2->HCTL);
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 	/* configure DMA */
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-	dimcb_io_write(&g.dim2->ACTL,
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-		       ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT |
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-		       true << ACTL_SCE_BIT);
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+	writel(ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT |
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+	       true << ACTL_SCE_BIT, &g.dim2->ACTL);
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 }
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 static bool dim2_is_mlb_locked(void)
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@@ -562,12 +560,12 @@
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 	u32 const mask0 = bit_mask(MLBC0_MLBLK_BIT);
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 	u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) |
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 			  bit_mask(MLBC1_LOCKERR_BIT);
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-	u32 const c1 = dimcb_io_read(&g.dim2->MLBC1);
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+	u32 const c1 = readl(&g.dim2->MLBC1);
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 	u32 const nda_mask = (u32)MLBC1_NDA_MASK << MLBC1_NDA_SHIFT;
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565
 
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-	dimcb_io_write(&g.dim2->MLBC1, c1 & nda_mask);
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-	return (dimcb_io_read(&g.dim2->MLBC1) & mask1) == 0 &&
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-	       (dimcb_io_read(&g.dim2->MLBC0) & mask0) != 0;
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+	writel(c1 & nda_mask, &g.dim2->MLBC1);
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+	return (readl(&g.dim2->MLBC1) & mask1) == 0 &&
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+	       (readl(&g.dim2->MLBC0) & mask0) != 0;
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 }
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 /* -------------------------------------------------------------------------- */
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@@ -590,7 +588,7 @@
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 	dim2_write_ctr_mask(ADT + ch_addr, mask, adt_w);
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589
 
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 	/* clear channel status bit */
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-	dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr));
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+	writel(bit_mask(ch_addr), &g.dim2->ACSR0);
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 	return true;
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 }
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@@ -652,7 +650,7 @@
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 		return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, "Bad buffer size");
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651
 
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 	if (ch->packet_length == 0 && ch->bytes_per_frame == 0 &&
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-	    buf_size != norm_ctrl_async_buffer_size(buf_size))
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+	    buf_size != dim_norm_ctrl_async_buffer_size(buf_size))
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 		return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE,
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 				    "Bad control/async buffer size");
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@@ -776,13 +774,8 @@
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 void dim_service_mlb_int_irq(void)
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 {
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-	dimcb_io_write(&g.dim2->MS0, 0);
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-	dimcb_io_write(&g.dim2->MS1, 0);
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-}
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-
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-u16 dim_norm_ctrl_async_buffer_size(u16 buf_size)
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-{
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-	return norm_ctrl_async_buffer_size(buf_size);
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+	writel(0, &g.dim2->MS0);
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+	writel(0, &g.dim2->MS1);
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 }
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 /**
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@@ -829,7 +822,7 @@
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 	if (is_tx && !g.atx_dbr.ch_addr) {
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 		g.atx_dbr.ch_addr = ch->addr;
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 		dbrcnt_init(ch->addr, ch->dbr_size);
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-		dimcb_io_write(&g.dim2->MIEN, bit_mask(20));
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+		writel(bit_mask(20), &g.dim2->MIEN);
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 	}
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827
 
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 	return ret;
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@@ -896,7 +889,7 @@
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 		return DIM_ERR_DRIVER_NOT_INITIALIZED;
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890
 
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 	if (ch->addr == g.atx_dbr.ch_addr) {
899
-		dimcb_io_write(&g.dim2->MIEN, 0);
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+		writel(0, &g.dim2->MIEN);
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 		g.atx_dbr.ch_addr = 0;
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 	}
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