~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0
1	2	/*
2	3	* SH RSPI driver
3	4	*
..	..	@@ -6,15 +7,6 @@
6	7	*
7	8	* Based on spi-sh.c:
8	9	* Copyright (C) 2011 Renesas Solutions Corp.
9		- *
10		- * This program is free software; you can redistribute it and/or modify
11		- * it under the terms of the GNU General Public License as published by
12		- * the Free Software Foundation; version 2 of the License.
13		- *
14		- * This program is distributed in the hope that it will be useful,
15		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
16		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17		- * GNU General Public License for more details.
18	10	*/
19	11
20	12	#include <linux/module.h>
..	..	@@ -32,6 +24,7 @@
32	24	#include <linux/sh_dma.h>
33	25	#include <linux/spi/spi.h>
34	26	#include <linux/spi/rspi.h>
	27	+#include <linux/spinlock.h>
35	28
36	29	#define RSPI_SPCR 0x00 /* Control Register */
37	30	#define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
..	..	@@ -87,8 +80,7 @@
87	80	#define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
88	81
89	82	/* SSLP - Slave Select Polarity Register */
90		-#define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
91		-#define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
	83	+#define SSLP_SSLP(i) BIT(i) /* SSLi Signal Polarity Setting */
92	84
93	85	/* SPPCR - Pin Control Register */
94	86	#define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
..	..	@@ -167,8 +159,9 @@
167	159	#define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
168	160	#define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
169	161	#define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
170		-#define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
	162	+#define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */
171	163	#define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
	164	+#define SPCMD_BRDV(brdv) ((brdv) << 2)
172	165	#define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
173	166	#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
174	167
..	..	@@ -187,9 +180,11 @@
187	180
188	181	struct rspi_data {
189	182	void __iomem *addr;
190		- u32 max_speed_hz;
191		- struct spi_master *master;
	183	+ u32 speed_hz;
	184	+ struct spi_controller *ctlr;
	185	+ struct platform_device *pdev;
192	186	wait_queue_head_t wait;
	187	+ spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */
193	188	struct clk *clk;
194	189	u16 spcmd;
195	190	u8 spsr;
..	..	@@ -245,27 +240,43 @@
245	240	/* optional functions */
246	241	struct spi_ops {
247	242	int (set_config_register)(struct rspi_data rspi, int access_size);
248		- int (transfer_one)(struct spi_master master, struct spi_device *spi,
249		- struct spi_transfer *xfer);
250		- u16 mode_bits;
	243	+ int (transfer_one)(struct spi_controller ctlr,
	244	+ struct spi_device spi, struct spi_transfer xfer);
	245	+ u16 extra_mode_bits;
	246	+ u16 min_div;
	247	+ u16 max_div;
251	248	u16 flags;
252	249	u16 fifo_size;
	250	+ u8 num_hw_ss;
253	251	};
	252	+
	253	+static void rspi_set_rate(struct rspi_data *rspi)
	254	+{
	255	+ unsigned long clksrc;
	256	+ int brdv = 0, spbr;
	257	+
	258	+ clksrc = clk_get_rate(rspi->clk);
	259	+ spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
	260	+ while (spbr > 255 && brdv < 3) {
	261	+ brdv++;
	262	+ spbr = DIV_ROUND_UP(spbr + 1, 2) - 1;
	263	+ }
	264	+
	265	+ rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
	266	+ rspi->spcmd \|= SPCMD_BRDV(brdv);
	267	+ rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1));
	268	+}
254	269
255	270	/*
256	271	* functions for RSPI on legacy SH
257	272	*/
258	273	static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
259	274	{
260		- int spbr;
261		-
262	275	/* Sets output mode, MOSI signal, and (optionally) loopback */
263	276	rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
264	277
265	278	/* Sets transfer bit rate */
266		- spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
267		- 2 * rspi->max_speed_hz) - 1;
268		- rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
	279	+ rspi_set_rate(rspi);
269	280
270	281	/* Disable dummy transmission, set 16-bit word access, 1 frame */
271	282	rspi_write8(rspi, 0, RSPI_SPDCR);
..	..	@@ -295,25 +306,11 @@
295	306	*/
296	307	static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
297	308	{
298		- int spbr;
299		- int div = 0;
300		- unsigned long clksrc;
301		-
302	309	/* Sets output mode, MOSI signal, and (optionally) loopback */
303	310	rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
304	311
305		- clksrc = clk_get_rate(rspi->clk);
306		- while (div < 3) {
307		- if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
308		- break;
309		- div++;
310		- clksrc /= 2;
311		- }
312		-
313	312	/* Sets transfer bit rate */
314		- spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;
315		- rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
316		- rspi->spcmd \|= div << 2;
	313	+ rspi_set_rate(rspi);
317	314
318	315	/* Disable dummy transmission, set byte access */
319	316	rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
..	..	@@ -340,14 +337,28 @@
340	337	*/
341	338	static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
342	339	{
343		- int spbr;
	340	+ unsigned long clksrc;
	341	+ int brdv = 0, spbr;
344	342
345	343	/* Sets output mode, MOSI signal, and (optionally) loopback */
346	344	rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
347	345
348	346	/* Sets transfer bit rate */
349		- spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
350		- rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
	347	+ clksrc = clk_get_rate(rspi->clk);
	348	+ if (rspi->speed_hz >= clksrc) {
	349	+ spbr = 0;
	350	+ rspi->speed_hz = clksrc;
	351	+ } else {
	352	+ spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);
	353	+ while (spbr > 255 && brdv < 3) {
	354	+ brdv++;
	355	+ spbr = DIV_ROUND_UP(spbr, 2);
	356	+ }
	357	+ spbr = clamp(spbr, 0, 255);
	358	+ rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);
	359	+ }
	360	+ rspi_write8(rspi, spbr, RSPI_SPBR);
	361	+ rspi->spcmd \|= SPCMD_BRDV(brdv);
351	362
352	363	/* Disable dummy transmission, set byte access */
353	364	rspi_write8(rspi, 0, RSPI_SPDCR);
..	..	@@ -434,8 +445,6 @@
434	445	return n;
435	446	}
436	447
437		-#define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
438		-
439	448	static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
440	449	{
441	450	rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) \| enable, RSPI_SPCR);
..	..	@@ -477,7 +486,7 @@
477	486	{
478	487	int error = rspi_wait_for_tx_empty(rspi);
479	488	if (error < 0) {
480		- dev_err(&rspi->master->dev, "transmit timeout\n");
	489	+ dev_err(&rspi->ctlr->dev, "transmit timeout\n");
481	490	return error;
482	491	}
483	492	rspi_write_data(rspi, data);
..	..	@@ -491,7 +500,7 @@
491	500
492	501	error = rspi_wait_for_rx_full(rspi);
493	502	if (error < 0) {
494		- dev_err(&rspi->master->dev, "receive timeout\n");
	503	+ dev_err(&rspi->ctlr->dev, "receive timeout\n");
495	504	return error;
496	505	}
497	506	data = rspi_read_data(rspi);
..	..	@@ -537,8 +546,8 @@
537	546
538	547	/* First prepare and submit the DMA request(s), as this may fail */
539	548	if (rx) {
540		- desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
541		- rx->sgl, rx->nents, DMA_DEV_TO_MEM,
	549	+ desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
	550	+ rx->nents, DMA_DEV_TO_MEM,
542	551	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
543	552	if (!desc_rx) {
544	553	ret = -EAGAIN;
..	..	@@ -557,8 +566,8 @@
557	566	}
558	567
559	568	if (tx) {
560		- desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
561		- tx->sgl, tx->nents, DMA_MEM_TO_DEV,
	569	+ desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
	570	+ tx->nents, DMA_MEM_TO_DEV,
562	571	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
563	572	if (!desc_tx) {
564	573	ret = -EAGAIN;
..	..	@@ -595,23 +604,27 @@
595	604
596	605	/* Now start DMA */
597	606	if (rx)
598		- dma_async_issue_pending(rspi->master->dma_rx);
	607	+ dma_async_issue_pending(rspi->ctlr->dma_rx);
599	608	if (tx)
600		- dma_async_issue_pending(rspi->master->dma_tx);
	609	+ dma_async_issue_pending(rspi->ctlr->dma_tx);
601	610
602	611	ret = wait_event_interruptible_timeout(rspi->wait,
603	612	rspi->dma_callbacked, HZ);
604	613	if (ret > 0 && rspi->dma_callbacked) {
605	614	ret = 0;
	615	+ if (tx)
	616	+ dmaengine_synchronize(rspi->ctlr->dma_tx);
	617	+ if (rx)
	618	+ dmaengine_synchronize(rspi->ctlr->dma_rx);
606	619	} else {
607	620	if (!ret) {
608		- dev_err(&rspi->master->dev, "DMA timeout\n");
	621	+ dev_err(&rspi->ctlr->dev, "DMA timeout\n");
609	622	ret = -ETIMEDOUT;
610	623	}
611	624	if (tx)
612		- dmaengine_terminate_all(rspi->master->dma_tx);
	625	+ dmaengine_terminate_all(rspi->ctlr->dma_tx);
613	626	if (rx)
614		- dmaengine_terminate_all(rspi->master->dma_rx);
	627	+ dmaengine_terminate_all(rspi->ctlr->dma_rx);
615	628	}
616	629
617	630	rspi_disable_irq(rspi, irq_mask);
..	..	@@ -625,12 +638,11 @@
625	638
626	639	no_dma_tx:
627	640	if (rx)
628		- dmaengine_terminate_all(rspi->master->dma_rx);
	641	+ dmaengine_terminate_all(rspi->ctlr->dma_rx);
629	642	no_dma_rx:
630	643	if (ret == -EAGAIN) {
631		- pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
632		- dev_driver_string(&rspi->master->dev),
633		- dev_name(&rspi->master->dev));
	644	+ dev_warn_once(&rspi->ctlr->dev,
	645	+ "DMA not available, falling back to PIO\n");
634	646	}
635	647	return ret;
636	648	}
..	..	@@ -671,10 +683,10 @@
671	683	return xfer->len > rspi->ops->fifo_size;
672	684	}
673	685
674		-static bool rspi_can_dma(struct spi_master master, struct spi_device spi,
	686	+static bool rspi_can_dma(struct spi_controller ctlr, struct spi_device spi,
675	687	struct spi_transfer *xfer)
676	688	{
677		- struct rspi_data *rspi = spi_master_get_devdata(master);
	689	+ struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
678	690
679	691	return __rspi_can_dma(rspi, xfer);
680	692	}
..	..	@@ -682,7 +694,7 @@
682	694	static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
683	695	struct spi_transfer *xfer)
684	696	{
685		- if (!rspi->master->can_dma \|\| !__rspi_can_dma(rspi, xfer))
	697	+ if (!rspi->ctlr->can_dma \|\| !__rspi_can_dma(rspi, xfer))
686	698	return -EAGAIN;
687	699
688	700	/* rx_buf can be NULL on RSPI on SH in TX-only Mode */
..	..	@@ -694,6 +706,8 @@
694	706	struct spi_transfer *xfer)
695	707	{
696	708	int ret;
	709	+
	710	+ xfer->effective_speed_hz = rspi->speed_hz;
697	711
698	712	ret = rspi_dma_check_then_transfer(rspi, xfer);
699	713	if (ret != -EAGAIN)
..	..	@@ -709,10 +723,10 @@
709	723	return 0;
710	724	}
711	725
712		-static int rspi_transfer_one(struct spi_master master, struct spi_device spi,
713		- struct spi_transfer *xfer)
	726	+static int rspi_transfer_one(struct spi_controller *ctlr,
	727	+ struct spi_device spi, struct spi_transfer xfer)
714	728	{
715		- struct rspi_data *rspi = spi_master_get_devdata(master);
	729	+ struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
716	730	u8 spcr;
717	731
718	732	spcr = rspi_read8(rspi, RSPI_SPCR);
..	..	@@ -727,11 +741,11 @@
727	741	return rspi_common_transfer(rspi, xfer);
728	742	}
729	743
730		-static int rspi_rz_transfer_one(struct spi_master *master,
	744	+static int rspi_rz_transfer_one(struct spi_controller *ctlr,
731	745	struct spi_device *spi,
732	746	struct spi_transfer *xfer)
733	747	{
734		- struct rspi_data *rspi = spi_master_get_devdata(master);
	748	+ struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
735	749
736	750	rspi_rz_receive_init(rspi);
737	751
..	..	@@ -747,27 +761,22 @@
747	761	while (len > 0) {
748	762	n = qspi_set_send_trigger(rspi, len);
749	763	qspi_set_receive_trigger(rspi, len);
750		- if (n == QSPI_BUFFER_SIZE) {
751		- ret = rspi_wait_for_tx_empty(rspi);
752		- if (ret < 0) {
753		- dev_err(&rspi->master->dev, "transmit timeout\n");
754		- return ret;
755		- }
756		- for (i = 0; i < n; i++)
757		- rspi_write_data(rspi, *tx++);
758		-
759		- ret = rspi_wait_for_rx_full(rspi);
760		- if (ret < 0) {
761		- dev_err(&rspi->master->dev, "receive timeout\n");
762		- return ret;
763		- }
764		- for (i = 0; i < n; i++)
765		- *rx++ = rspi_read_data(rspi);
766		- } else {
767		- ret = rspi_pio_transfer(rspi, tx, rx, n);
768		- if (ret < 0)
769		- return ret;
	764	+ ret = rspi_wait_for_tx_empty(rspi);
	765	+ if (ret < 0) {
	766	+ dev_err(&rspi->ctlr->dev, "transmit timeout\n");
	767	+ return ret;
770	768	}
	769	+ for (i = 0; i < n; i++)
	770	+ rspi_write_data(rspi, *tx++);
	771	+
	772	+ ret = rspi_wait_for_rx_full(rspi);
	773	+ if (ret < 0) {
	774	+ dev_err(&rspi->ctlr->dev, "receive timeout\n");
	775	+ return ret;
	776	+ }
	777	+ for (i = 0; i < n; i++)
	778	+ *rx++ = rspi_read_data(rspi);
	779	+
771	780	len -= n;
772	781	}
773	782
..	..	@@ -796,7 +805,7 @@
796	805	unsigned int i, len;
797	806	int ret;
798	807
799		- if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
	808	+ if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
800	809	ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
801	810	if (ret != -EAGAIN)
802	811	return ret;
..	..	@@ -804,19 +813,14 @@
804	813
805	814	while (n > 0) {
806	815	len = qspi_set_send_trigger(rspi, n);
807		- if (len == QSPI_BUFFER_SIZE) {
808		- ret = rspi_wait_for_tx_empty(rspi);
809		- if (ret < 0) {
810		- dev_err(&rspi->master->dev, "transmit timeout\n");
811		- return ret;
812		- }
813		- for (i = 0; i < len; i++)
814		- rspi_write_data(rspi, *tx++);
815		- } else {
816		- ret = rspi_pio_transfer(rspi, tx, NULL, len);
817		- if (ret < 0)
818		- return ret;
	816	+ ret = rspi_wait_for_tx_empty(rspi);
	817	+ if (ret < 0) {
	818	+ dev_err(&rspi->ctlr->dev, "transmit timeout\n");
	819	+ return ret;
819	820	}
	821	+ for (i = 0; i < len; i++)
	822	+ rspi_write_data(rspi, *tx++);
	823	+
820	824	n -= len;
821	825	}
822	826
..	..	@@ -833,7 +837,7 @@
833	837	unsigned int i, len;
834	838	int ret;
835	839
836		- if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
	840	+ if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
837	841	int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
838	842	if (ret != -EAGAIN)
839	843	return ret;
..	..	@@ -841,30 +845,26 @@
841	845
842	846	while (n > 0) {
843	847	len = qspi_set_receive_trigger(rspi, n);
844		- if (len == QSPI_BUFFER_SIZE) {
845		- ret = rspi_wait_for_rx_full(rspi);
846		- if (ret < 0) {
847		- dev_err(&rspi->master->dev, "receive timeout\n");
848		- return ret;
849		- }
850		- for (i = 0; i < len; i++)
851		- *rx++ = rspi_read_data(rspi);
852		- } else {
853		- ret = rspi_pio_transfer(rspi, NULL, rx, len);
854		- if (ret < 0)
855		- return ret;
	848	+ ret = rspi_wait_for_rx_full(rspi);
	849	+ if (ret < 0) {
	850	+ dev_err(&rspi->ctlr->dev, "receive timeout\n");
	851	+ return ret;
856	852	}
	853	+ for (i = 0; i < len; i++)
	854	+ *rx++ = rspi_read_data(rspi);
	855	+
857	856	n -= len;
858	857	}
859	858
860	859	return 0;
861	860	}
862	861
863		-static int qspi_transfer_one(struct spi_master master, struct spi_device spi,
864		- struct spi_transfer *xfer)
	862	+static int qspi_transfer_one(struct spi_controller *ctlr,
	863	+ struct spi_device spi, struct spi_transfer xfer)
865	864	{
866		- struct rspi_data *rspi = spi_master_get_devdata(master);
	865	+ struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
867	866
	867	+ xfer->effective_speed_hz = rspi->speed_hz;
868	868	if (spi->mode & SPI_LOOP) {
869	869	return qspi_transfer_out_in(rspi, xfer);
870	870	} else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
..	..	@@ -877,28 +877,6 @@
877	877	/* Single SPI Transfer */
878	878	return qspi_transfer_out_in(rspi, xfer);
879	879	}
880		-}
881		-
882		-static int rspi_setup(struct spi_device *spi)
883		-{
884		- struct rspi_data *rspi = spi_master_get_devdata(spi->master);
885		-
886		- rspi->max_speed_hz = spi->max_speed_hz;
887		-
888		- rspi->spcmd = SPCMD_SSLKP;
889		- if (spi->mode & SPI_CPOL)
890		- rspi->spcmd \|= SPCMD_CPOL;
891		- if (spi->mode & SPI_CPHA)
892		- rspi->spcmd \|= SPCMD_CPHA;
893		-
894		- /* CMOS output mode and MOSI signal from previous transfer */
895		- rspi->sppcr = 0;
896		- if (spi->mode & SPI_LOOP)
897		- rspi->sppcr \|= SPPCR_SPLP;
898		-
899		- set_config_register(rspi, 8);
900		-
901		- return 0;
902	880	}
903	881
904	882	static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
..	..	@@ -966,11 +944,71 @@
966	944	return 0;
967	945	}
968	946
969		-static int rspi_prepare_message(struct spi_master *master,
	947	+static int rspi_setup(struct spi_device *spi)
	948	+{
	949	+ struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
	950	+ u8 sslp;
	951	+
	952	+ if (spi->cs_gpiod)
	953	+ return 0;
	954	+
	955	+ pm_runtime_get_sync(&rspi->pdev->dev);
	956	+ spin_lock_irq(&rspi->lock);
	957	+
	958	+ sslp = rspi_read8(rspi, RSPI_SSLP);
	959	+ if (spi->mode & SPI_CS_HIGH)
	960	+ sslp \|= SSLP_SSLP(spi->chip_select);
	961	+ else
	962	+ sslp &= ~SSLP_SSLP(spi->chip_select);
	963	+ rspi_write8(rspi, sslp, RSPI_SSLP);
	964	+
	965	+ spin_unlock_irq(&rspi->lock);
	966	+ pm_runtime_put(&rspi->pdev->dev);
	967	+ return 0;
	968	+}
	969	+
	970	+static int rspi_prepare_message(struct spi_controller *ctlr,
970	971	struct spi_message *msg)
971	972	{
972		- struct rspi_data *rspi = spi_master_get_devdata(master);
	973	+ struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
	974	+ struct spi_device *spi = msg->spi;
	975	+ const struct spi_transfer *xfer;
973	976	int ret;
	977	+
	978	+ /*
	979	+ * As the Bit Rate Register must not be changed while the device is
	980	+ * active, all transfers in a message must use the same bit rate.
	981	+ * In theory, the sequencer could be enabled, and each Command Register
	982	+ * could divide the base bit rate by a different value.
	983	+ * However, most RSPI variants do not have Transfer Data Length
	984	+ * Multiplier Setting Registers, so each sequence step would be limited
	985	+ * to a single word, making this feature unsuitable for large
	986	+ * transfers, which would gain most from it.
	987	+ */
	988	+ rspi->speed_hz = spi->max_speed_hz;
	989	+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
	990	+ if (xfer->speed_hz < rspi->speed_hz)
	991	+ rspi->speed_hz = xfer->speed_hz;
	992	+ }
	993	+
	994	+ rspi->spcmd = SPCMD_SSLKP;
	995	+ if (spi->mode & SPI_CPOL)
	996	+ rspi->spcmd \|= SPCMD_CPOL;
	997	+ if (spi->mode & SPI_CPHA)
	998	+ rspi->spcmd \|= SPCMD_CPHA;
	999	+ if (spi->mode & SPI_LSB_FIRST)
	1000	+ rspi->spcmd \|= SPCMD_LSBF;
	1001	+
	1002	+ /* Configure slave signal to assert */
	1003	+ rspi->spcmd \|= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs
	1004	+ : spi->chip_select);
	1005	+
	1006	+ /* CMOS output mode and MOSI signal from previous transfer */
	1007	+ rspi->sppcr = 0;
	1008	+ if (spi->mode & SPI_LOOP)
	1009	+ rspi->sppcr \|= SPPCR_SPLP;
	1010	+
	1011	+ rspi->ops->set_config_register(rspi, 8);
974	1012
975	1013	if (msg->spi->mode &
976	1014	(SPI_TX_DUAL \| SPI_TX_QUAD \| SPI_RX_DUAL \| SPI_RX_QUAD)) {
..	..	@@ -985,10 +1023,10 @@
985	1023	return 0;
986	1024	}
987	1025
988		-static int rspi_unprepare_message(struct spi_master *master,
	1026	+static int rspi_unprepare_message(struct spi_controller *ctlr,
989	1027	struct spi_message *msg)
990	1028	{
991		- struct rspi_data *rspi = spi_master_get_devdata(master);
	1029	+ struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
992	1030
993	1031	/* Disable SPI function */
994	1032	rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
..	..	@@ -1073,14 +1111,11 @@
1073	1111	}
1074	1112
1075	1113	memset(&cfg, 0, sizeof(cfg));
	1114	+ cfg.dst_addr = port_addr + RSPI_SPDR;
	1115	+ cfg.src_addr = port_addr + RSPI_SPDR;
	1116	+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	1117	+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1076	1118	cfg.direction = dir;
1077		- if (dir == DMA_MEM_TO_DEV) {
1078		- cfg.dst_addr = port_addr;
1079		- cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1080		- } else {
1081		- cfg.src_addr = port_addr;
1082		- cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1083		- }
1084	1119
1085	1120	ret = dmaengine_slave_config(chan, &cfg);
1086	1121	if (ret) {
..	..	@@ -1092,7 +1127,7 @@
1092	1127	return chan;
1093	1128	}
1094	1129
1095		-static int rspi_request_dma(struct device dev, struct spi_master master,
	1130	+static int rspi_request_dma(struct device dev, struct spi_controller ctlr,
1096	1131	const struct resource *res)
1097	1132	{
1098	1133	const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
..	..	@@ -1110,37 +1145,37 @@
1110	1145	return 0;
1111	1146	}
1112	1147
1113		- master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1114		- res->start + RSPI_SPDR);
1115		- if (!master->dma_tx)
	1148	+ ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
	1149	+ res->start);
	1150	+ if (!ctlr->dma_tx)
1116	1151	return -ENODEV;
1117	1152
1118		- master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1119		- res->start + RSPI_SPDR);
1120		- if (!master->dma_rx) {
1121		- dma_release_channel(master->dma_tx);
1122		- master->dma_tx = NULL;
	1153	+ ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
	1154	+ res->start);
	1155	+ if (!ctlr->dma_rx) {
	1156	+ dma_release_channel(ctlr->dma_tx);
	1157	+ ctlr->dma_tx = NULL;
1123	1158	return -ENODEV;
1124	1159	}
1125	1160
1126		- master->can_dma = rspi_can_dma;
	1161	+ ctlr->can_dma = rspi_can_dma;
1127	1162	dev_info(dev, "DMA available");
1128	1163	return 0;
1129	1164	}
1130	1165
1131		-static void rspi_release_dma(struct spi_master *master)
	1166	+static void rspi_release_dma(struct spi_controller *ctlr)
1132	1167	{
1133		- if (master->dma_tx)
1134		- dma_release_channel(master->dma_tx);
1135		- if (master->dma_rx)
1136		- dma_release_channel(master->dma_rx);
	1168	+ if (ctlr->dma_tx)
	1169	+ dma_release_channel(ctlr->dma_tx);
	1170	+ if (ctlr->dma_rx)
	1171	+ dma_release_channel(ctlr->dma_rx);
1137	1172	}
1138	1173
1139	1174	static int rspi_remove(struct platform_device *pdev)
1140	1175	{
1141	1176	struct rspi_data *rspi = platform_get_drvdata(pdev);
1142	1177
1143		- rspi_release_dma(rspi->master);
	1178	+ rspi_release_dma(rspi->ctlr);
1144	1179	pm_runtime_disable(&pdev->dev);
1145	1180
1146	1181	return 0;
..	..	@@ -1149,27 +1184,33 @@
1149	1184	static const struct spi_ops rspi_ops = {
1150	1185	.set_config_register = rspi_set_config_register,
1151	1186	.transfer_one = rspi_transfer_one,
1152		- .mode_bits = SPI_CPHA \| SPI_CPOL \| SPI_LOOP,
1153		- .flags = SPI_MASTER_MUST_TX,
	1187	+ .min_div = 2,
	1188	+ .max_div = 4096,
	1189	+ .flags = SPI_CONTROLLER_MUST_TX,
1154	1190	.fifo_size = 8,
	1191	+ .num_hw_ss = 2,
1155	1192	};
1156	1193
1157	1194	static const struct spi_ops rspi_rz_ops = {
1158	1195	.set_config_register = rspi_rz_set_config_register,
1159	1196	.transfer_one = rspi_rz_transfer_one,
1160		- .mode_bits = SPI_CPHA \| SPI_CPOL \| SPI_LOOP,
1161		- .flags = SPI_MASTER_MUST_RX \| SPI_MASTER_MUST_TX,
	1197	+ .min_div = 2,
	1198	+ .max_div = 4096,
	1199	+ .flags = SPI_CONTROLLER_MUST_RX \| SPI_CONTROLLER_MUST_TX,
1162	1200	.fifo_size = 8, /* 8 for TX, 32 for RX */
	1201	+ .num_hw_ss = 1,
1163	1202	};
1164	1203
1165	1204	static const struct spi_ops qspi_ops = {
1166	1205	.set_config_register = qspi_set_config_register,
1167	1206	.transfer_one = qspi_transfer_one,
1168		- .mode_bits = SPI_CPHA \| SPI_CPOL \| SPI_LOOP \|
1169		- SPI_TX_DUAL \| SPI_TX_QUAD \|
	1207	+ .extra_mode_bits = SPI_TX_DUAL \| SPI_TX_QUAD \|
1170	1208	SPI_RX_DUAL \| SPI_RX_QUAD,
1171		- .flags = SPI_MASTER_MUST_RX \| SPI_MASTER_MUST_TX,
	1209	+ .min_div = 1,
	1210	+ .max_div = 4080,
	1211	+ .flags = SPI_CONTROLLER_MUST_RX \| SPI_CONTROLLER_MUST_TX,
1172	1212	.fifo_size = 32,
	1213	+ .num_hw_ss = 1,
1173	1214	};
1174	1215
1175	1216	#ifdef CONFIG_OF
..	..	@@ -1185,7 +1226,7 @@
1185	1226
1186	1227	MODULE_DEVICE_TABLE(of, rspi_of_match);
1187	1228
1188		-static int rspi_parse_dt(struct device dev, struct spi_master master)
	1229	+static int rspi_parse_dt(struct device dev, struct spi_controller ctlr)
1189	1230	{
1190	1231	u32 num_cs;
1191	1232	int error;
..	..	@@ -1197,12 +1238,12 @@
1197	1238	return error;
1198	1239	}
1199	1240
1200		- master->num_chipselect = num_cs;
	1241	+ ctlr->num_chipselect = num_cs;
1201	1242	return 0;
1202	1243	}
1203	1244	#else
1204	1245	#define rspi_of_match NULL
1205		-static inline int rspi_parse_dt(struct device dev, struct spi_master master)
	1246	+static inline int rspi_parse_dt(struct device dev, struct spi_controller ctlr)
1206	1247	{
1207	1248	return -EINVAL;
1208	1249	}
..	..	@@ -1223,41 +1264,35 @@
1223	1264	static int rspi_probe(struct platform_device *pdev)
1224	1265	{
1225	1266	struct resource *res;
1226		- struct spi_master *master;
	1267	+ struct spi_controller *ctlr;
1227	1268	struct rspi_data *rspi;
1228	1269	int ret;
1229	1270	const struct rspi_plat_data *rspi_pd;
1230	1271	const struct spi_ops *ops;
	1272	+ unsigned long clksrc;
1231	1273
1232		- master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1233		- if (master == NULL)
	1274	+ ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
	1275	+ if (ctlr == NULL)
1234	1276	return -ENOMEM;
1235	1277
1236	1278	ops = of_device_get_match_data(&pdev->dev);
1237	1279	if (ops) {
1238		- ret = rspi_parse_dt(&pdev->dev, master);
	1280	+ ret = rspi_parse_dt(&pdev->dev, ctlr);
1239	1281	if (ret)
1240	1282	goto error1;
1241	1283	} else {
1242	1284	ops = (struct spi_ops *)pdev->id_entry->driver_data;
1243	1285	rspi_pd = dev_get_platdata(&pdev->dev);
1244	1286	if (rspi_pd && rspi_pd->num_chipselect)
1245		- master->num_chipselect = rspi_pd->num_chipselect;
	1287	+ ctlr->num_chipselect = rspi_pd->num_chipselect;
1246	1288	else
1247		- master->num_chipselect = 2; /* default */
	1289	+ ctlr->num_chipselect = 2; /* default */
1248	1290	}
1249	1291
1250		- /* ops parameter check */
1251		- if (!ops->set_config_register) {
1252		- dev_err(&pdev->dev, "there is no set_config_register\n");
1253		- ret = -ENODEV;
1254		- goto error1;
1255		- }
1256		-
1257		- rspi = spi_master_get_devdata(master);
	1292	+ rspi = spi_controller_get_devdata(ctlr);
1258	1293	platform_set_drvdata(pdev, rspi);
1259	1294	rspi->ops = ops;
1260		- rspi->master = master;
	1295	+ rspi->ctlr = ctlr;
1261	1296
1262	1297	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1263	1298	rspi->addr = devm_ioremap_resource(&pdev->dev, res);
..	..	@@ -1273,23 +1308,31 @@
1273	1308	goto error1;
1274	1309	}
1275	1310
	1311	+ rspi->pdev = pdev;
1276	1312	pm_runtime_enable(&pdev->dev);
1277	1313
1278	1314	init_waitqueue_head(&rspi->wait);
	1315	+ spin_lock_init(&rspi->lock);
1279	1316
1280		- master->bus_num = pdev->id;
1281		- master->setup = rspi_setup;
1282		- master->auto_runtime_pm = true;
1283		- master->transfer_one = ops->transfer_one;
1284		- master->prepare_message = rspi_prepare_message;
1285		- master->unprepare_message = rspi_unprepare_message;
1286		- master->mode_bits = ops->mode_bits;
1287		- master->flags = ops->flags;
1288		- master->dev.of_node = pdev->dev.of_node;
	1317	+ ctlr->bus_num = pdev->id;
	1318	+ ctlr->setup = rspi_setup;
	1319	+ ctlr->auto_runtime_pm = true;
	1320	+ ctlr->transfer_one = ops->transfer_one;
	1321	+ ctlr->prepare_message = rspi_prepare_message;
	1322	+ ctlr->unprepare_message = rspi_unprepare_message;
	1323	+ ctlr->mode_bits = SPI_CPHA \| SPI_CPOL \| SPI_CS_HIGH \| SPI_LSB_FIRST \|
	1324	+ SPI_LOOP \| ops->extra_mode_bits;
	1325	+ clksrc = clk_get_rate(rspi->clk);
	1326	+ ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div);
	1327	+ ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div);
	1328	+ ctlr->flags = ops->flags;
	1329	+ ctlr->dev.of_node = pdev->dev.of_node;
	1330	+ ctlr->use_gpio_descriptors = true;
	1331	+ ctlr->max_native_cs = rspi->ops->num_hw_ss;
1289	1332
1290		- ret = platform_get_irq_byname(pdev, "rx");
	1333	+ ret = platform_get_irq_byname_optional(pdev, "rx");
1291	1334	if (ret < 0) {
1292		- ret = platform_get_irq_byname(pdev, "mux");
	1335	+ ret = platform_get_irq_byname_optional(pdev, "mux");
1293	1336	if (ret < 0)
1294	1337	ret = platform_get_irq(pdev, 0);
1295	1338	if (ret >= 0)
..	..	@@ -1299,10 +1342,6 @@
1299	1342	ret = platform_get_irq_byname(pdev, "tx");
1300	1343	if (ret >= 0)
1301	1344	rspi->tx_irq = ret;
1302		- }
1303		- if (ret < 0) {
1304		- dev_err(&pdev->dev, "platform_get_irq error\n");
1305		- goto error2;
1306	1345	}
1307	1346
1308	1347	if (rspi->rx_irq == rspi->tx_irq) {
..	..	@@ -1322,13 +1361,13 @@
1322	1361	goto error2;
1323	1362	}
1324	1363
1325		- ret = rspi_request_dma(&pdev->dev, master, res);
	1364	+ ret = rspi_request_dma(&pdev->dev, ctlr, res);
1326	1365	if (ret < 0)
1327	1366	dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1328	1367
1329		- ret = devm_spi_register_master(&pdev->dev, master);
	1368	+ ret = devm_spi_register_controller(&pdev->dev, ctlr);
1330	1369	if (ret < 0) {
1331		- dev_err(&pdev->dev, "spi_register_master error.\n");
	1370	+ dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1332	1371	goto error3;
1333	1372	}
1334	1373
..	..	@@ -1337,19 +1376,17 @@
1337	1376	return 0;
1338	1377
1339	1378	error3:
1340		- rspi_release_dma(master);
	1379	+ rspi_release_dma(ctlr);
1341	1380	error2:
1342	1381	pm_runtime_disable(&pdev->dev);
1343	1382	error1:
1344		- spi_master_put(master);
	1383	+ spi_controller_put(ctlr);
1345	1384
1346	1385	return ret;
1347	1386	}
1348	1387
1349	1388	static const struct platform_device_id spi_driver_ids[] = {
1350	1389	{ "rspi", (kernel_ulong_t)&rspi_ops },
1351		- { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1352		- { "qspi", (kernel_ulong_t)&qspi_ops },
1353	1390	{},
1354	1391	};
1355	1392
..	..	@@ -1358,18 +1395,16 @@
1358	1395	#ifdef CONFIG_PM_SLEEP
1359	1396	static int rspi_suspend(struct device *dev)
1360	1397	{
1361		- struct platform_device *pdev = to_platform_device(dev);
1362		- struct rspi_data *rspi = platform_get_drvdata(pdev);
	1398	+ struct rspi_data *rspi = dev_get_drvdata(dev);
1363	1399
1364		- return spi_master_suspend(rspi->master);
	1400	+ return spi_controller_suspend(rspi->ctlr);
1365	1401	}
1366	1402
1367	1403	static int rspi_resume(struct device *dev)
1368	1404	{
1369		- struct platform_device *pdev = to_platform_device(dev);
1370		- struct rspi_data *rspi = platform_get_drvdata(pdev);
	1405	+ struct rspi_data *rspi = dev_get_drvdata(dev);
1371	1406
1372		- return spi_master_resume(rspi->master);
	1407	+ return spi_controller_resume(rspi->ctlr);
1373	1408	}
1374	1409
1375	1410	static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);