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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/spi/spi-lantiq-ssc.c
....@@ -1,10 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
34  * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
4
- *
5
- * This program is free software; you can distribute it and/or modify it
6
- * under the terms of the GNU General Public License (Version 2) as
7
- * published by the Free Software Foundation.
85  */
96 
107 #include <linux/kernel.h>
....@@ -18,7 +15,6 @@
1815 #include <linux/completion.h>
1916 #include <linux/spinlock.h>
2017 #include <linux/err.h>
21
-#include <linux/gpio.h>
2218 #include <linux/pm_runtime.h>
2319 #include <linux/spi/spi.h>
2420 
....@@ -53,8 +49,6 @@
5349 #define LTQ_SPI_RXCNT		0x84
5450 #define LTQ_SPI_DMACON		0xec
5551 #define LTQ_SPI_IRNEN		0xf4
56
-#define LTQ_SPI_IRNICR		0xf8
57
-#define LTQ_SPI_IRNCR		0xfc
5852 
5953 #define LTQ_SPI_CLC_SMC_S	16	/* Clock divider for sleep mode */
6054 #define LTQ_SPI_CLC_SMC_M	(0xFF << LTQ_SPI_CLC_SMC_S)
....@@ -64,9 +58,7 @@
6458 #define LTQ_SPI_CLC_DISR	BIT(0)	/* Disable request bit */
6559 
6660 #define LTQ_SPI_ID_TXFS_S	24	/* Implemented TX FIFO size */
67
-#define LTQ_SPI_ID_TXFS_M	(0x3F << LTQ_SPI_ID_TXFS_S)
6861 #define LTQ_SPI_ID_RXFS_S	16	/* Implemented RX FIFO size */
69
-#define LTQ_SPI_ID_RXFS_M	(0x3F << LTQ_SPI_ID_RXFS_S)
7062 #define LTQ_SPI_ID_MOD_S	8	/* Module ID */
7163 #define LTQ_SPI_ID_MOD_M	(0xff << LTQ_SPI_ID_MOD_S)
7264 #define LTQ_SPI_ID_CFG_S	5	/* DMA interface support */
....@@ -129,19 +121,15 @@
129121 					 LTQ_SPI_WHBSTATE_CLRTUE)
130122 
131123 #define LTQ_SPI_RXFCON_RXFITL_S	8	/* FIFO interrupt trigger level */
132
-#define LTQ_SPI_RXFCON_RXFITL_M	(0x3F << LTQ_SPI_RXFCON_RXFITL_S)
133124 #define LTQ_SPI_RXFCON_RXFLU	BIT(1)	/* FIFO flush */
134125 #define LTQ_SPI_RXFCON_RXFEN	BIT(0)	/* FIFO enable */
135126 
136127 #define LTQ_SPI_TXFCON_TXFITL_S	8	/* FIFO interrupt trigger level */
137
-#define LTQ_SPI_TXFCON_TXFITL_M	(0x3F << LTQ_SPI_TXFCON_TXFITL_S)
138128 #define LTQ_SPI_TXFCON_TXFLU	BIT(1)	/* FIFO flush */
139129 #define LTQ_SPI_TXFCON_TXFEN	BIT(0)	/* FIFO enable */
140130 
141131 #define LTQ_SPI_FSTAT_RXFFL_S	0
142
-#define LTQ_SPI_FSTAT_RXFFL_M	(0x3f << LTQ_SPI_FSTAT_RXFFL_S)
143132 #define LTQ_SPI_FSTAT_TXFFL_S	8
144
-#define LTQ_SPI_FSTAT_TXFFL_M	(0x3f << LTQ_SPI_FSTAT_TXFFL_S)
145133 
146134 #define LTQ_SPI_GPOCON_ISCSBN_S	8
147135 #define LTQ_SPI_GPOCON_INVOUTN_S	0
....@@ -161,9 +149,16 @@
161149 #define LTQ_SPI_IRNEN_T_XRX	BIT(0)	/* Receive end interrupt request */
162150 #define LTQ_SPI_IRNEN_ALL	0x1F
163151 
152
+struct lantiq_ssc_spi;
153
+
164154 struct lantiq_ssc_hwcfg {
165
-	unsigned int irnen_r;
166
-	unsigned int irnen_t;
155
+	int (*cfg_irq)(struct platform_device *pdev, struct lantiq_ssc_spi *spi);
156
+	unsigned int	irnen_r;
157
+	unsigned int	irnen_t;
158
+	unsigned int	irncr;
159
+	unsigned int	irnicr;
160
+	bool		irq_ack;
161
+	u32		fifo_size_mask;
167162 };
168163 
169164 struct lantiq_ssc_spi {
....@@ -213,16 +208,18 @@
213208 
214209 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
215210 {
211
+	const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
216212 	u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
217213 
218
-	return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S;
214
+	return (fstat >> LTQ_SPI_FSTAT_TXFFL_S) & hwcfg->fifo_size_mask;
219215 }
220216 
221217 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
222218 {
219
+	const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
223220 	u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
224221 
225
-	return fstat & LTQ_SPI_FSTAT_RXFFL_M;
222
+	return (fstat >> LTQ_SPI_FSTAT_RXFFL_S) & hwcfg->fifo_size_mask;
226223 }
227224 
228225 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
....@@ -395,7 +392,7 @@
395392 	u32 gpocon;
396393 
397394 	/* GPIOs are used for CS */
398
-	if (gpio_is_valid(spidev->cs_gpio))
395
+	if (spidev->cs_gpiod)
399396 		return 0;
400397 
401398 	dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
....@@ -626,6 +623,12 @@
626623 static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
627624 {
628625 	struct lantiq_ssc_spi *spi = data;
626
+	const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
627
+	u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
628
+
629
+	spin_lock(&spi->lock);
630
+	if (hwcfg->irq_ack)
631
+		lantiq_ssc_writel(spi, val, hwcfg->irncr);
629632 
630633 	if (spi->tx) {
631634 		if (spi->rx && spi->rx_todo)
....@@ -648,10 +651,12 @@
648651 		}
649652 	}
650653 
654
+	spin_unlock(&spi->lock);
651655 	return IRQ_HANDLED;
652656 
653657 completed:
654658 	queue_work(spi->wq, &spi->work);
659
+	spin_unlock(&spi->lock);
655660 
656661 	return IRQ_HANDLED;
657662 }
....@@ -659,10 +664,16 @@
659664 static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
660665 {
661666 	struct lantiq_ssc_spi *spi = data;
667
+	const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
662668 	u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
669
+	u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
663670 
664671 	if (!(stat & LTQ_SPI_STAT_ERRORS))
665672 		return IRQ_NONE;
673
+
674
+	spin_lock(&spi->lock);
675
+	if (hwcfg->irq_ack)
676
+		lantiq_ssc_writel(spi, val, hwcfg->irncr);
666677 
667678 	if (stat & LTQ_SPI_STAT_RUE)
668679 		dev_err(spi->dev, "receive underflow error\n");
....@@ -684,6 +695,25 @@
684695 	if (spi->master->cur_msg)
685696 		spi->master->cur_msg->status = -EIO;
686697 	queue_work(spi->wq, &spi->work);
698
+	spin_unlock(&spi->lock);
699
+
700
+	return IRQ_HANDLED;
701
+}
702
+
703
+static irqreturn_t intel_lgm_ssc_isr(int irq, void *data)
704
+{
705
+	struct lantiq_ssc_spi *spi = data;
706
+	const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
707
+	u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
708
+
709
+	if (!(val & LTQ_SPI_IRNEN_ALL))
710
+		return IRQ_NONE;
711
+
712
+	if (val & LTQ_SPI_IRNEN_E)
713
+		return lantiq_ssc_err_interrupt(irq, data);
714
+
715
+	if ((val & hwcfg->irnen_t) || (val & hwcfg->irnen_r))
716
+		return lantiq_ssc_xmit_interrupt(irq, data);
687717 
688718 	return IRQ_HANDLED;
689719 }
....@@ -788,20 +818,84 @@
788818 	return transfer_start(spi, spidev, t);
789819 }
790820 
821
+static int intel_lgm_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
822
+{
823
+	int irq;
824
+
825
+	irq = platform_get_irq(pdev, 0);
826
+	if (irq < 0)
827
+		return irq;
828
+
829
+	return devm_request_irq(&pdev->dev, irq, intel_lgm_ssc_isr, 0, "spi", spi);
830
+}
831
+
832
+static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
833
+{
834
+	int irq, err;
835
+
836
+	irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
837
+	if (irq < 0)
838
+		return irq;
839
+
840
+	err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt,
841
+			       0, LTQ_SPI_RX_IRQ_NAME, spi);
842
+	if (err)
843
+		return err;
844
+
845
+	irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
846
+	if (irq < 0)
847
+		return irq;
848
+
849
+	err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt,
850
+			       0, LTQ_SPI_TX_IRQ_NAME, spi);
851
+
852
+	if (err)
853
+		return err;
854
+
855
+	irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
856
+	if (irq < 0)
857
+		return irq;
858
+
859
+	err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_err_interrupt,
860
+			       0, LTQ_SPI_ERR_IRQ_NAME, spi);
861
+	return err;
862
+}
863
+
791864 static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
792
-	.irnen_r = LTQ_SPI_IRNEN_R_XWAY,
793
-	.irnen_t = LTQ_SPI_IRNEN_T_XWAY,
865
+	.cfg_irq	= lantiq_cfg_irq,
866
+	.irnen_r	= LTQ_SPI_IRNEN_R_XWAY,
867
+	.irnen_t	= LTQ_SPI_IRNEN_T_XWAY,
868
+	.irnicr		= 0xF8,
869
+	.irncr		= 0xFC,
870
+	.fifo_size_mask	= GENMASK(5, 0),
871
+	.irq_ack	= false,
794872 };
795873 
796874 static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
797
-	.irnen_r = LTQ_SPI_IRNEN_R_XRX,
798
-	.irnen_t = LTQ_SPI_IRNEN_T_XRX,
875
+	.cfg_irq	= lantiq_cfg_irq,
876
+	.irnen_r	= LTQ_SPI_IRNEN_R_XRX,
877
+	.irnen_t	= LTQ_SPI_IRNEN_T_XRX,
878
+	.irnicr		= 0xF8,
879
+	.irncr		= 0xFC,
880
+	.fifo_size_mask	= GENMASK(5, 0),
881
+	.irq_ack	= false,
882
+};
883
+
884
+static const struct lantiq_ssc_hwcfg intel_ssc_lgm = {
885
+	.cfg_irq	= intel_lgm_cfg_irq,
886
+	.irnen_r	= LTQ_SPI_IRNEN_R_XRX,
887
+	.irnen_t	= LTQ_SPI_IRNEN_T_XRX,
888
+	.irnicr		= 0xFC,
889
+	.irncr		= 0xF8,
890
+	.fifo_size_mask	= GENMASK(7, 0),
891
+	.irq_ack	= true,
799892 };
800893 
801894 static const struct of_device_id lantiq_ssc_match[] = {
802895 	{ .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
803896 	{ .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
804897 	{ .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
898
+	{ .compatible = "intel,lgm-spi", .data = &intel_ssc_lgm, },
805899 	{},
806900 };
807901 MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
....@@ -810,13 +904,12 @@
810904 {
811905 	struct device *dev = &pdev->dev;
812906 	struct spi_master *master;
813
-	struct resource *res;
814907 	struct lantiq_ssc_spi *spi;
815908 	const struct lantiq_ssc_hwcfg *hwcfg;
816909 	const struct of_device_id *match;
817
-	int err, rx_irq, tx_irq, err_irq;
818910 	u32 id, supports_dma, revision;
819911 	unsigned int num_cs;
912
+	int err;
820913 
821914 	match = of_match_device(lantiq_ssc_match, dev);
822915 	if (!match) {
....@@ -824,30 +917,6 @@
824917 		return -EINVAL;
825918 	}
826919 	hwcfg = match->data;
827
-
828
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
829
-	if (!res) {
830
-		dev_err(dev, "failed to get resources\n");
831
-		return -ENXIO;
832
-	}
833
-
834
-	rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
835
-	if (rx_irq < 0) {
836
-		dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME);
837
-		return -ENXIO;
838
-	}
839
-
840
-	tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
841
-	if (tx_irq < 0) {
842
-		dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME);
843
-		return -ENXIO;
844
-	}
845
-
846
-	err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
847
-	if (err_irq < 0) {
848
-		dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME);
849
-		return -ENXIO;
850
-	}
851920 
852921 	master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
853922 	if (!master)
....@@ -858,25 +927,13 @@
858927 	spi->dev = dev;
859928 	spi->hwcfg = hwcfg;
860929 	platform_set_drvdata(pdev, spi);
861
-
862
-	spi->regbase = devm_ioremap_resource(dev, res);
930
+	spi->regbase = devm_platform_ioremap_resource(pdev, 0);
863931 	if (IS_ERR(spi->regbase)) {
864932 		err = PTR_ERR(spi->regbase);
865933 		goto err_master_put;
866934 	}
867935 
868
-	err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
869
-			       0, LTQ_SPI_RX_IRQ_NAME, spi);
870
-	if (err)
871
-		goto err_master_put;
872
-
873
-	err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
874
-			       0, LTQ_SPI_TX_IRQ_NAME, spi);
875
-	if (err)
876
-		goto err_master_put;
877
-
878
-	err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
879
-			       0, LTQ_SPI_ERR_IRQ_NAME, spi);
936
+	err = hwcfg->cfg_irq(pdev, spi);
880937 	if (err)
881938 		goto err_master_put;
882939 
....@@ -915,6 +972,7 @@
915972 
916973 	master->dev.of_node = pdev->dev.of_node;
917974 	master->num_chipselect = num_cs;
975
+	master->use_gpio_descriptors = true;
918976 	master->setup = lantiq_ssc_setup;
919977 	master->set_cs = lantiq_ssc_set_cs;
920978 	master->handle_err = lantiq_ssc_handle_err;
....@@ -926,7 +984,7 @@
926984 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
927985 				     SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
928986 
929
-	spi->wq = alloc_ordered_workqueue(dev_name(dev), 0);
987
+	spi->wq = alloc_ordered_workqueue(dev_name(dev), WQ_MEM_RECLAIM);
930988 	if (!spi->wq) {
931989 		err = -ENOMEM;
932990 		goto err_clk_put;
....@@ -934,8 +992,8 @@
934992 	INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
935993 
936994 	id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
937
-	spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;
938
-	spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;
995
+	spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask;
996
+	spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask;
939997 	supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
940998 	revision = id & LTQ_SPI_ID_REV_M;
941999