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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/soc/rockchip/pm_domains.c
....@@ -1,11 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Rockchip Generic power domain support.
34  *
45  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96  */
107 
118 #include <linux/module.h>
....@@ -30,16 +27,22 @@
3027 #include <dt-bindings/power/rv1126-power.h>
3128 #include <dt-bindings/power/rk1808-power.h>
3229 #include <dt-bindings/power/rk3036-power.h>
30
+#include <dt-bindings/power/rk3066-power.h>
3331 #include <dt-bindings/power/rk3128-power.h>
32
+#include <dt-bindings/power/rk3188-power.h>
3433 #include <dt-bindings/power/rk3228-power.h>
3534 #include <dt-bindings/power/rk3288-power.h>
3635 #include <dt-bindings/power/rk3328-power.h>
3736 #include <dt-bindings/power/rk3366-power.h>
3837 #include <dt-bindings/power/rk3368-power.h>
3938 #include <dt-bindings/power/rk3399-power.h>
39
+#include <dt-bindings/power/rk3528-power.h>
40
+#include <dt-bindings/power/rk3562-power.h>
4041 #include <dt-bindings/power/rk3568-power.h>
42
+#include <dt-bindings/power/rk3588-power.h>
4143 
4244 struct rockchip_domain_info {
45
+	const char *name;
4346 	int pwr_mask;
4447 	int status_mask;
4548 	int req_mask;
....@@ -48,9 +51,15 @@
4851 	bool active_wakeup;
4952 	int pwr_w_mask;
5053 	int req_w_mask;
54
+	int mem_status_mask;
55
+	int repair_status_mask;
56
+	int clk_ungate_mask;
57
+	int clk_ungate_w_mask;
58
+	int mem_num;
5159 	bool keepon_startup;
5260 	bool always_on;
5361 	u32 pwr_offset;
62
+	u32 mem_offset;
5463 	u32 req_offset;
5564 };
5665 
....@@ -60,6 +69,12 @@
6069 	u32 req_offset;
6170 	u32 idle_offset;
6271 	u32 ack_offset;
72
+	u32 mem_pwr_offset;
73
+	u32 chain_status_offset;
74
+	u32 mem_status_offset;
75
+	u32 repair_status_offset;
76
+	u32 clk_ungate_offset;
77
+	u32 mem_sd_offset;
6378 
6479 	u32 core_pwrcnt_offset;
6580 	u32 gpu_pwrcnt_offset;
....@@ -85,10 +100,12 @@
85100 	int num_qos;
86101 	struct regmap **qos_regmap;
87102 	u32 *qos_save_regs[MAX_QOS_REGS_NUM];
103
+	bool *qos_is_need_init[MAX_QOS_REGS_NUM];
88104 	int num_clks;
89105 	struct clk_bulk_data *clks;
90106 	bool is_ignore_pwr;
91107 	bool is_qos_saved;
108
+	bool is_qos_need_init;
92109 	struct regulator *supply;
93110 };
94111 
....@@ -108,6 +125,35 @@
108125 MODULE_PARM_DESC(always_on,
109126 		 "Always keep pm domains power on except for system suspend.");
110127 
128
+#ifdef MODULE
129
+static bool keepon_startup = true;
130
+static void rockchip_pd_keepon_do_release(void);
131
+
132
+static int pd_param_set_keepon_startup(const char *val,
133
+				       const struct kernel_param *kp)
134
+{
135
+	int ret;
136
+
137
+	ret = param_set_bool(val, kp);
138
+	if (ret)
139
+		return ret;
140
+
141
+	if (!keepon_startup)
142
+		rockchip_pd_keepon_do_release();
143
+
144
+	return 0;
145
+}
146
+
147
+static const struct kernel_param_ops pd_keepon_startup_ops = {
148
+	.set	= pd_param_set_keepon_startup,
149
+	.get	= param_get_bool,
150
+};
151
+
152
+module_param_cb(keepon_startup, &pd_keepon_startup_ops, &keepon_startup, 0644);
153
+MODULE_PARM_DESC(keepon_startup,
154
+		 "Keep pm domains power on during system startup.");
155
+#endif
156
+
111157 static void rockchip_pmu_lock(struct rockchip_pm_domain *pd)
112158 {
113159 	mutex_lock(&pd->pmu->mutex);
....@@ -122,8 +168,9 @@
122168 
123169 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
124170 
125
-#define DOMAIN(pwr, status, req, idle, ack, wakeup, keepon)	\
171
+#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup, keepon)	\
126172 {							\
173
+	.name = _name,					\
127174 	.pwr_mask = (pwr),				\
128175 	.status_mask = (status),			\
129176 	.req_mask = (req),				\
....@@ -133,8 +180,9 @@
133180 	.keepon_startup = (keepon),			\
134181 }
135182 
136
-#define DOMAIN_M(pwr, status, req, idle, ack, wakeup, keepon)	\
183
+#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup, keepon)	\
137184 {							\
185
+	.name = _name,					\
138186 	.pwr_w_mask = (pwr) << 16,			\
139187 	.pwr_mask = (pwr),				\
140188 	.status_mask = (status),			\
....@@ -146,8 +194,40 @@
146194 	.keepon_startup = keepon,			\
147195 }
148196 
149
-#define DOMAIN_M_O(pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon)	\
197
+#define DOMAIN_M_A(pwr, status, req, idle, ack, always, wakeup, keepon)	\
150198 {							\
199
+	.pwr_w_mask = (pwr) << 16,			\
200
+	.pwr_mask = (pwr),				\
201
+	.status_mask = (status),			\
202
+	.req_w_mask = (req) << 16,			\
203
+	.req_mask = (req),				\
204
+	.idle_mask = (idle),				\
205
+	.ack_mask = (ack),				\
206
+	.always_on = always,				\
207
+	.active_wakeup = wakeup,			\
208
+	.keepon_startup = keepon,			\
209
+}
210
+
211
+#define DOMAIN_M_C_SD(_name, pwr, status, req, idle, ack, clk, mem, wakeup, keepon)	\
212
+{							\
213
+	.name = _name,					\
214
+	.pwr_w_mask = (pwr) << 16,			\
215
+	.pwr_mask = (pwr),				\
216
+	.status_mask = (status),			\
217
+	.req_w_mask = (req) << 16,			\
218
+	.req_mask = (req),				\
219
+	.idle_mask = (idle),				\
220
+	.ack_mask = (ack),				\
221
+	.clk_ungate_mask = (clk),			\
222
+	.clk_ungate_w_mask = (clk) << 16,		\
223
+	.mem_num = (mem),				\
224
+	.active_wakeup = wakeup,			\
225
+	.keepon_startup = keepon,			\
226
+}
227
+
228
+#define DOMAIN_M_O(_name, pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon)	\
229
+{							\
230
+	.name = _name,					\
151231 	.pwr_w_mask = (pwr) << 16,			\
152232 	.pwr_mask = (pwr),				\
153233 	.status_mask = (status),			\
....@@ -161,8 +241,28 @@
161241 	.req_offset = r_offset,				\
162242 }
163243 
164
-#define DOMAIN_RK3036(req, ack, idle, wakeup)		\
244
+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, keepon)	\
165245 {							\
246
+	.name = _name,					\
247
+	.pwr_offset = p_offset,				\
248
+	.pwr_w_mask = (pwr) << 16,			\
249
+	.pwr_mask = (pwr),				\
250
+	.status_mask = (status),			\
251
+	.mem_offset = m_offset,				\
252
+	.mem_status_mask = (m_status),			\
253
+	.repair_status_mask = (r_status),		\
254
+	.req_offset = r_offset,				\
255
+	.req_w_mask = (req) << 16,			\
256
+	.req_mask = (req),				\
257
+	.idle_mask = (idle),				\
258
+	.ack_mask = (ack),				\
259
+	.active_wakeup = wakeup,			\
260
+	.keepon_startup = keepon,			\
261
+}
262
+
263
+#define DOMAIN_RK3036(_name, req, ack, idle, wakeup)	\
264
+{							\
265
+	.name = _name,					\
166266 	.req_mask = (req),				\
167267 	.req_w_mask = (req) << 16,			\
168268 	.ack_mask = (ack),				\
....@@ -170,47 +270,62 @@
170270 	.active_wakeup = wakeup,			\
171271 }
172272 
173
-#define DOMAIN_PX30(pwr, status, req, wakeup)		\
174
-	DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup, false)
273
+#define DOMAIN_PX30(name, pwr, status, req, wakeup)		\
274
+	DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup, false)
175275 
176
-#define DOMAIN_PX30_PROTECT(pwr, status, req, wakeup)	\
177
-	DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup, true)
276
+#define DOMAIN_PX30_PROTECT(name, pwr, status, req, wakeup)	\
277
+	DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup, true)
178278 
179
-#define DOMAIN_RV1126(pwr, req, idle, wakeup)		\
180
-	DOMAIN_M(pwr, pwr, req, idle, idle, wakeup, false)
279
+#define DOMAIN_RV1126(name, pwr, req, idle, wakeup)		\
280
+	DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup, false)
181281 
182
-#define DOMAIN_RV1126_PROTECT(pwr, req, idle, wakeup)	\
183
-	DOMAIN_M(pwr, pwr, req, idle, idle, wakeup, true)
282
+#define DOMAIN_RV1126_PROTECT(name, pwr, req, idle, wakeup)	\
283
+	DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup, true)
184284 
185
-#define DOMAIN_RV1126_O(pwr, req, idle, r_offset, wakeup)	\
186
-	DOMAIN_M_O(pwr, pwr, 0, req, idle, idle, r_offset, wakeup, false)
285
+#define DOMAIN_RV1126_O(name, pwr, req, idle, r_offset, wakeup)	\
286
+	DOMAIN_M_O(name, pwr, pwr, 0, req, idle, idle, r_offset, wakeup, false)
187287 
188
-#define DOMAIN_RK3288(pwr, status, req, wakeup)		\
189
-	DOMAIN(pwr, status, req, req, (req) << 16, wakeup, false)
288
+#define DOMAIN_RK3288(name, pwr, status, req, wakeup)		\
289
+	DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup, false)
190290 
191
-#define DOMAIN_RK3288_PROTECT(pwr, status, req, wakeup)	\
192
-	DOMAIN(pwr, status, req, req, (req) << 16, wakeup, true)
291
+#define DOMAIN_RK3288_PROTECT(name, pwr, status, req, wakeup)	\
292
+	DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup, true)
193293 
194
-#define DOMAIN_RK3328(pwr, status, req, wakeup)		\
195
-	DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup, false)
294
+#define DOMAIN_RK3328(name, pwr, status, req, wakeup)		\
295
+	DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup, false)
196296 
197
-#define DOMAIN_RK3368(pwr, status, req, wakeup)		\
198
-	DOMAIN(pwr, status, req, (req) << 16, req, wakeup, false)
297
+#define DOMAIN_RK3368(name, pwr, status, req, wakeup)		\
298
+	DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup, false)
199299 
200
-#define DOMAIN_RK3368_PROTECT(pwr, status, req, wakeup)	\
201
-	DOMAIN(pwr, status, req, (req) << 16, req, wakeup, true)
300
+#define DOMAIN_RK3368_PROTECT(name, pwr, status, req, wakeup)	\
301
+	DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup, true)
202302 
203
-#define DOMAIN_RK3399(pwr, status, req, wakeup)		\
204
-	DOMAIN(pwr, status, req, req, req, wakeup, false)
303
+#define DOMAIN_RK3399(name, pwr, status, req, wakeup)		\
304
+	DOMAIN(name, pwr, status, req, req, req, wakeup, false)
205305 
206
-#define DOMAIN_RK3399_PROTECT(pwr, status, req, wakeup)	\
207
-	DOMAIN(pwr, status, req, req, req, wakeup, true)
306
+#define DOMAIN_RK3399_PROTECT(name, pwr, status, req, wakeup)	\
307
+	DOMAIN(name, pwr, status, req, req, req, wakeup, true)
208308 
209
-#define DOMAIN_RK3568(pwr, req, wakeup)		\
210
-	DOMAIN_M(pwr, pwr, req, req, req, wakeup, false)
309
+#define DOMAIN_RK3528(pwr, req, always, wakeup) \
310
+	DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false)
211311 
212
-#define DOMAIN_RK3568_PROTECT(pwr, req, wakeup)		\
213
-	DOMAIN_M(pwr, pwr, req, req, req, wakeup, true)
312
+#define DOMAIN_RK3562(name, pwr, req, mem, wakeup)		\
313
+	DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, false)
314
+
315
+#define DOMAIN_RK3562_PROTECT(name, pwr, req, mem, wakeup)		\
316
+	DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, true)
317
+
318
+#define DOMAIN_RK3568(name, pwr, req, wakeup)			\
319
+	DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false)
320
+
321
+#define DOMAIN_RK3568_PROTECT(name, pwr, req, wakeup)		\
322
+	DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, true)
323
+
324
+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup)	\
325
+	DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, false)
326
+
327
+#define DOMAIN_RK3588_P(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup)	\
328
+	DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, true)
214329 
215330 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
216331 {
....@@ -228,6 +343,42 @@
228343 
229344 	regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
230345 	return val;
346
+}
347
+
348
+static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
349
+{
350
+	const struct rockchip_domain_info *pd_info = pd->info;
351
+	struct rockchip_pmu *pmu = pd->pmu;
352
+	unsigned int val;
353
+
354
+	if (!pd_info->clk_ungate_mask)
355
+		return 0;
356
+	if (!pmu->info->clk_ungate_offset)
357
+		return 0;
358
+
359
+	val = ungate ? (pd_info->clk_ungate_mask | pd_info->clk_ungate_w_mask) :
360
+			pd_info->clk_ungate_w_mask;
361
+	regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
362
+
363
+	return 0;
364
+}
365
+
366
+static int rockchip_pmu_mem_shut_down(struct rockchip_pm_domain *pd, bool sd)
367
+{
368
+	const struct rockchip_domain_info *pd_info = pd->info;
369
+	struct rockchip_pmu *pmu = pd->pmu;
370
+	unsigned int i;
371
+
372
+	if (!pd_info->mem_num)
373
+		return 0;
374
+	if (!pmu->info->mem_sd_offset)
375
+		return 0;
376
+
377
+	for (i = 0; i < pd_info->mem_num; i++)
378
+		regmap_write(pmu->regmap, pmu->info->mem_sd_offset,
379
+			     (sd << i) | (1 << (i + 16)));
380
+
381
+	return 0;
231382 }
232383 
233384 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
....@@ -357,6 +508,45 @@
357508 	return 0;
358509 }
359510 
511
+static void rockchip_pmu_init_qos(struct rockchip_pm_domain *pd)
512
+{
513
+	int i;
514
+
515
+	if (!pd->is_qos_need_init)
516
+		return;
517
+
518
+	for (i = 0; i < pd->num_qos; i++) {
519
+		if (pd->qos_is_need_init[0][i])
520
+			regmap_write(pd->qos_regmap[i],
521
+				     QOS_PRIORITY,
522
+				     pd->qos_save_regs[0][i]);
523
+
524
+		if (pd->qos_is_need_init[1][i])
525
+			regmap_write(pd->qos_regmap[i],
526
+				     QOS_MODE,
527
+				     pd->qos_save_regs[1][i]);
528
+
529
+		if (pd->qos_is_need_init[2][i])
530
+			regmap_write(pd->qos_regmap[i],
531
+				     QOS_BANDWIDTH,
532
+				     pd->qos_save_regs[2][i]);
533
+
534
+		if (pd->qos_is_need_init[3][i])
535
+			regmap_write(pd->qos_regmap[i],
536
+				     QOS_SATURATION,
537
+				     pd->qos_save_regs[3][i]);
538
+
539
+		if (pd->qos_is_need_init[4][i])
540
+			regmap_write(pd->qos_regmap[i],
541
+				     QOS_EXTCONTROL,
542
+				     pd->qos_save_regs[4][i]);
543
+	}
544
+
545
+	kfree(pd->qos_is_need_init[0]);
546
+	pd->qos_is_need_init[0] = NULL;
547
+	pd->is_qos_need_init = false;
548
+}
549
+
360550 int rockchip_save_qos(struct device *dev)
361551 {
362552 	struct generic_pm_domain *genpd;
....@@ -403,10 +593,88 @@
403593 }
404594 EXPORT_SYMBOL(rockchip_restore_qos);
405595 
596
+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
597
+{
598
+	struct rockchip_pmu *pmu = pd->pmu;
599
+	unsigned int val;
600
+
601
+	regmap_read(pmu->regmap,
602
+		    pmu->info->mem_status_offset + pd->info->mem_offset, &val);
603
+
604
+	/* 1'b0: power on, 1'b1: power off */
605
+	return !(val & pd->info->mem_status_mask);
606
+}
607
+
608
+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
609
+{
610
+	struct rockchip_pmu *pmu = pd->pmu;
611
+	unsigned int val;
612
+
613
+	regmap_read(pmu->regmap,
614
+		    pmu->info->chain_status_offset + pd->info->mem_offset, &val);
615
+
616
+	/* 1'b1: power on, 1'b0: power off */
617
+	return val & pd->info->mem_status_mask;
618
+}
619
+
620
+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
621
+{
622
+	struct rockchip_pmu *pmu = pd->pmu;
623
+	struct generic_pm_domain *genpd = &pd->genpd;
624
+	bool is_on;
625
+	int ret = 0;
626
+
627
+	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
628
+					is_on == true, 0, 10000);
629
+	if (ret) {
630
+		dev_err(pmu->dev,
631
+			"failed to get chain status '%s', target_on=1, val=%d\n",
632
+			genpd->name, is_on);
633
+		goto error;
634
+	}
635
+
636
+	udelay(60);
637
+
638
+	regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
639
+		     (pd->info->pwr_mask | pd->info->pwr_w_mask));
640
+	dsb(sy);
641
+
642
+	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
643
+					is_on == false, 0, 10000);
644
+	if (ret) {
645
+		dev_err(pmu->dev,
646
+			"failed to get mem status '%s', target_on=0, val=%d\n",
647
+			genpd->name, is_on);
648
+		goto error;
649
+	}
650
+
651
+	regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
652
+		     pd->info->pwr_w_mask);
653
+	dsb(sy);
654
+
655
+	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
656
+					is_on == true, 0, 10000);
657
+	if (ret) {
658
+		dev_err(pmu->dev,
659
+			"failed to get mem status '%s', target_on=1, val=%d\n",
660
+			genpd->name, is_on);
661
+	}
662
+
663
+error:
664
+
665
+	return ret;
666
+}
667
+
406668 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
407669 {
408670 	struct rockchip_pmu *pmu = pd->pmu;
409671 	unsigned int val;
672
+
673
+	if (pd->info->repair_status_mask) {
674
+		regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
675
+		/* 1'b1: power on, 1'b0: power off */
676
+		return val & pd->info->repair_status_mask;
677
+	}
410678 
411679 	/* check idle status for idle-only domains */
412680 	if (pd->info->status_mask == 0)
....@@ -424,15 +692,19 @@
424692 	struct rockchip_pmu *pmu = pd->pmu;
425693 	struct generic_pm_domain *genpd = &pd->genpd;
426694 	u32 pd_pwr_offset = 0;
427
-	bool is_on;
695
+	bool is_on, is_mem_on = false;
428696 	int ret = 0;
697
+
698
+	if (pd->info->pwr_mask == 0)
699
+		return 0;
700
+
701
+	if (on && pd->info->mem_status_mask)
702
+		is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
429703 
430704 	if (pd->info->pwr_offset)
431705 		pd_pwr_offset = pd->info->pwr_offset;
432706 
433
-	if (pd->info->pwr_mask == 0)
434
-		return 0;
435
-	else if (pd->info->pwr_w_mask)
707
+	if (pd->info->pwr_w_mask)
436708 		regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
437709 			     on ? pd->info->pwr_w_mask :
438710 			     (pd->info->pwr_mask | pd->info->pwr_w_mask));
....@@ -442,6 +714,12 @@
442714 				   on ? 0 : -1U);
443715 
444716 	dsb(sy);
717
+
718
+	if (is_mem_on) {
719
+		ret = rockchip_pmu_domain_mem_reset(pd);
720
+		if (ret)
721
+			goto error;
722
+	}
445723 
446724 	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
447725 					is_on == on, 0, 10000);
....@@ -467,8 +745,8 @@
467745 	if (pm_domain_always_on && !power_on)
468746 		return 0;
469747 
470
-	if (!power_on && (soc_is_px30s())) {
471
-		if (genpd->name && !strcmp(genpd->name, "pd_gpu"))
748
+	if (!power_on && soc_is_px30s()) {
749
+		if (genpd->name && !strcmp(genpd->name, "gpu"))
472750 			return 0;
473751 	}
474752 
....@@ -496,6 +774,7 @@
496774 			rockchip_pmu_unlock(pd);
497775 			return ret;
498776 		}
777
+		rockchip_pmu_ungate_clk(pd, true);
499778 
500779 		if (!power_on) {
501780 			rockchip_pmu_save_qos(pd);
....@@ -508,6 +787,7 @@
508787 					genpd->name);
509788 				goto out;
510789 			}
790
+			rockchip_pmu_mem_shut_down(pd, true);
511791 		}
512792 
513793 		ret = rockchip_do_pmu_set_power_domain(pd, power_on);
....@@ -518,6 +798,7 @@
518798 		}
519799 
520800 		if (power_on) {
801
+			rockchip_pmu_mem_shut_down(pd, false);
521802 			/* if powering up, leave idle mode */
522803 			ret = rockchip_pmu_set_idle_request(pd, false);
523804 			if (ret) {
....@@ -528,9 +809,12 @@
528809 
529810 			if (pd->is_qos_saved)
530811 				rockchip_pmu_restore_qos(pd);
812
+			if (pd->is_qos_need_init)
813
+				rockchip_pmu_init_qos(pd);
531814 		}
532815 
533816 out:
817
+		rockchip_pmu_ungate_clk(pd, false);
534818 		clk_bulk_disable(pd->num_clks, pd->clks);
535819 
536820 		if (!power_on && !IS_ERR(pd->supply))
....@@ -658,44 +942,26 @@
658942 	pm_clk_destroy(dev);
659943 }
660944 
661
-static void rockchip_pd_qos_init(struct rockchip_pm_domain *pd,
662
-				 bool **qos_is_need_init)
945
+static void rockchip_pd_qos_init(struct rockchip_pm_domain *pd)
663946 {
664
-	int i, is_pd_on;
947
+	int is_pd_on, ret = 0;
665948 
666
-	is_pd_on = rockchip_pmu_domain_is_on(pd);
667
-	if (!is_pd_on)
668
-		rockchip_pd_power(pd, true);
669
-
670
-	for (i = 0; i < pd->num_qos; i++) {
671
-		if (qos_is_need_init[0][i])
672
-			regmap_write(pd->qos_regmap[i],
673
-				     QOS_PRIORITY,
674
-				     pd->qos_save_regs[0][i]);
675
-
676
-		if (qos_is_need_init[1][i])
677
-			regmap_write(pd->qos_regmap[i],
678
-				     QOS_MODE,
679
-				     pd->qos_save_regs[1][i]);
680
-
681
-		if (qos_is_need_init[2][i])
682
-			regmap_write(pd->qos_regmap[i],
683
-				     QOS_BANDWIDTH,
684
-				     pd->qos_save_regs[2][i]);
685
-
686
-		if (qos_is_need_init[3][i])
687
-			regmap_write(pd->qos_regmap[i],
688
-				     QOS_SATURATION,
689
-				     pd->qos_save_regs[3][i]);
690
-
691
-		if (qos_is_need_init[4][i])
692
-			regmap_write(pd->qos_regmap[i],
693
-				     QOS_EXTCONTROL,
694
-				     pd->qos_save_regs[4][i]);
949
+	if (!pd->is_qos_need_init) {
950
+		kfree(pd->qos_is_need_init[0]);
951
+		pd->qos_is_need_init[0] = NULL;
952
+		return;
695953 	}
696954 
697
-	if (!is_pd_on)
698
-		rockchip_pd_power(pd, false);
955
+	is_pd_on = rockchip_pmu_domain_is_on(pd);
956
+	if (is_pd_on) {
957
+		ret = clk_bulk_enable(pd->num_clks, pd->clks);
958
+		if (ret < 0) {
959
+			dev_err(pd->pmu->dev, "failed to enable clocks\n");
960
+			return;
961
+		}
962
+		rockchip_pmu_init_qos(pd);
963
+		clk_bulk_disable(pd->num_clks, pd->clks);
964
+	}
699965 }
700966 
701967 static int rockchip_pd_add_alwasy_on_flag(struct rockchip_pm_domain *pd)
....@@ -728,27 +994,27 @@
728994 	int i, j;
729995 	u32 id, val;
730996 	int error;
731
-	bool *qos_is_need_init[MAX_QOS_REGS_NUM] = { NULL };
732
-	bool is_qos_need_init = false;
733997 
734998 	error = of_property_read_u32(node, "reg", &id);
735999 	if (error) {
7361000 		dev_err(pmu->dev,
737
-			"%s: failed to retrieve domain id (reg): %d\n",
738
-			node->name, error);
1001
+			"%pOFn: failed to retrieve domain id (reg): %d\n",
1002
+			node, error);
7391003 		return -EINVAL;
7401004 	}
7411005 
7421006 	if (id >= pmu->info->num_domains) {
743
-		dev_err(pmu->dev, "%s: invalid domain id %d\n",
744
-			node->name, id);
1007
+		dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
1008
+			node, id);
7451009 		return -EINVAL;
7461010 	}
1011
+	if (pmu->genpd_data.domains[id])
1012
+		return 0;
7471013 
7481014 	pd_info = &pmu->info->domain_info[id];
7491015 	if (!pd_info) {
750
-		dev_err(pmu->dev, "%s: undefined domain id %d\n",
751
-			node->name, id);
1016
+		dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
1017
+			node, id);
7521018 		return -EINVAL;
7531019 	}
7541020 
....@@ -768,8 +1034,8 @@
7681034 		if (!pd->clks)
7691035 			return -ENOMEM;
7701036 	} else {
771
-		dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n",
772
-			node->name, pd->num_clks);
1037
+		dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
1038
+			node, pd->num_clks);
7731039 		pd->num_clks = 0;
7741040 	}
7751041 
....@@ -778,8 +1044,8 @@
7781044 		if (IS_ERR(pd->clks[i].clk)) {
7791045 			error = PTR_ERR(pd->clks[i].clk);
7801046 			dev_err(pmu->dev,
781
-				"%s: failed to get clk at index %d: %d\n",
782
-				node->name, i, error);
1047
+				"%pOFn: failed to get clk at index %d: %d\n",
1048
+				node, i, error);
7831049 			return error;
7841050 		}
7851051 	}
....@@ -815,18 +1081,19 @@
8151081 			error = -ENOMEM;
8161082 			goto err_unprepare_clocks;
8171083 		}
818
-		qos_is_need_init[0] = kzalloc(sizeof(bool) *
819
-					      MAX_QOS_REGS_NUM *
820
-					      pd->num_qos,
821
-					      GFP_KERNEL);
822
-		if (!qos_is_need_init[0]) {
1084
+		pd->qos_is_need_init[0] = kzalloc(sizeof(bool) *
1085
+						  MAX_QOS_REGS_NUM *
1086
+						  pd->num_qos,
1087
+						  GFP_KERNEL);
1088
+		if (!pd->qos_is_need_init[0]) {
8231089 			error = -ENOMEM;
8241090 			goto err_unprepare_clocks;
8251091 		}
8261092 		for (i = 1; i < MAX_QOS_REGS_NUM; i++) {
8271093 			pd->qos_save_regs[i] = pd->qos_save_regs[i - 1] +
8281094 					       num_qos;
829
-			qos_is_need_init[i] = qos_is_need_init[i - 1] + num_qos;
1095
+			pd->qos_is_need_init[i] = pd->qos_is_need_init[i - 1] +
1096
+						  num_qos;
8301097 		}
8311098 
8321099 		for (j = 0; j < num_qos; j++) {
....@@ -847,71 +1114,68 @@
8471114 							  "priority-init",
8481115 							  &val)) {
8491116 					pd->qos_save_regs[0][j] = val;
850
-					qos_is_need_init[0][j] = true;
851
-					is_qos_need_init = true;
1117
+					pd->qos_is_need_init[0][j] = true;
1118
+					pd->is_qos_need_init = true;
8521119 				}
8531120 
8541121 				if (!of_property_read_u32(qos_node,
8551122 							  "mode-init",
8561123 							  &val)) {
8571124 					pd->qos_save_regs[1][j] = val;
858
-					qos_is_need_init[1][j] = true;
859
-					is_qos_need_init = true;
1125
+					pd->qos_is_need_init[1][j] = true;
1126
+					pd->is_qos_need_init = true;
8601127 				}
8611128 
8621129 				if (!of_property_read_u32(qos_node,
8631130 							  "bandwidth-init",
8641131 							  &val)) {
8651132 					pd->qos_save_regs[2][j] = val;
866
-					qos_is_need_init[2][j] = true;
867
-					is_qos_need_init = true;
1133
+					pd->qos_is_need_init[2][j] = true;
1134
+					pd->is_qos_need_init = true;
8681135 				}
8691136 
8701137 				if (!of_property_read_u32(qos_node,
8711138 							  "saturation-init",
8721139 							  &val)) {
8731140 					pd->qos_save_regs[3][j] = val;
874
-					qos_is_need_init[3][j] = true;
875
-					is_qos_need_init = true;
1141
+					pd->qos_is_need_init[3][j] = true;
1142
+					pd->is_qos_need_init = true;
8761143 				}
8771144 
8781145 				if (!of_property_read_u32(qos_node,
8791146 							  "extcontrol-init",
8801147 							  &val)) {
8811148 					pd->qos_save_regs[4][j] = val;
882
-					qos_is_need_init[4][j] = true;
883
-					is_qos_need_init = true;
1149
+					pd->qos_is_need_init[4][j] = true;
1150
+					pd->is_qos_need_init = true;
8841151 				}
8851152 
8861153 				num_qos_reg++;
8871154 			}
8881155 			of_node_put(qos_node);
889
-			if (num_qos_reg > pd->num_qos)
1156
+			if (num_qos_reg > pd->num_qos) {
1157
+				error = -EINVAL;
8901158 				goto err_unprepare_clocks;
1159
+			}
8911160 		}
8921161 	}
8931162 
894
-	pd->genpd.name = node->name;
1163
+	if (pd->info->name)
1164
+		pd->genpd.name = pd->info->name;
1165
+	else
1166
+		pd->genpd.name = kbasename(node->full_name);
8951167 	pd->genpd.power_off = rockchip_pd_power_off;
8961168 	pd->genpd.power_on = rockchip_pd_power_on;
8971169 	pd->genpd.attach_dev = rockchip_pd_attach_dev;
8981170 	pd->genpd.detach_dev = rockchip_pd_detach_dev;
8991171 	if (pd_info->active_wakeup)
9001172 		pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
901
-	if (pd_info->always_on) {
902
-		if (rockchip_pd_add_alwasy_on_flag(pd))
1173
+	if (pd_info->always_on || pd_info->keepon_startup) {
1174
+		error = rockchip_pd_add_alwasy_on_flag(pd);
1175
+		if (error)
9031176 			goto err_unprepare_clocks;
9041177 	}
905
-#ifndef MODULE
906
-	if (pd_info->keepon_startup) {
907
-		if (rockchip_pd_add_alwasy_on_flag(pd))
908
-			goto err_unprepare_clocks;
909
-	}
910
-#endif
911
-	if (is_qos_need_init)
912
-		rockchip_pd_qos_init(pd, &qos_is_need_init[0]);
913
-
914
-	kfree(qos_is_need_init[0]);
1178
+	rockchip_pd_qos_init(pd);
9151179 
9161180 	pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
9171181 
....@@ -919,7 +1183,8 @@
9191183 	return 0;
9201184 
9211185 err_unprepare_clocks:
922
-	kfree(qos_is_need_init[0]);
1186
+	kfree(pd->qos_is_need_init[0]);
1187
+	pd->qos_is_need_init[0] = NULL;
9231188 	clk_bulk_unprepare(pd->num_clks, pd->clks);
9241189 err_put_clocks:
9251190 	clk_bulk_put(pd->num_clks, pd->clks);
....@@ -991,24 +1256,24 @@
9911256 		error = of_property_read_u32(parent, "reg", &idx);
9921257 		if (error) {
9931258 			dev_err(pmu->dev,
994
-				"%s: failed to retrieve domain id (reg): %d\n",
995
-				parent->name, error);
1259
+				"%pOFn: failed to retrieve domain id (reg): %d\n",
1260
+				parent, error);
9961261 			goto err_out;
9971262 		}
9981263 		parent_domain = pmu->genpd_data.domains[idx];
9991264 
10001265 		error = rockchip_pm_add_one_domain(pmu, np);
10011266 		if (error) {
1002
-			dev_err(pmu->dev, "failed to handle node %s: %d\n",
1003
-				np->name, error);
1267
+			dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
1268
+				np, error);
10041269 			goto err_out;
10051270 		}
10061271 
10071272 		error = of_property_read_u32(np, "reg", &idx);
10081273 		if (error) {
10091274 			dev_err(pmu->dev,
1010
-				"%s: failed to retrieve domain id (reg): %d\n",
1011
-				np->name, error);
1275
+				"%pOFn: failed to retrieve domain id (reg): %d\n",
1276
+				np, error);
10121277 			goto err_out;
10131278 		}
10141279 		child_domain = pmu->genpd_data.domains[idx];
....@@ -1044,37 +1309,14 @@
10441309 	return error;
10451310 }
10461311 
1047
-#ifndef MODULE
1048
-static void rockchip_pd_keepon_do_release(struct generic_pm_domain *genpd,
1049
-					  struct rockchip_pm_domain *pd)
1050
-{
1051
-	struct pm_domain_data *pm_data;
1052
-	int enable_count;
1053
-
1054
-	pd->genpd.flags &= (~GENPD_FLAG_ALWAYS_ON);
1055
-	list_for_each_entry(pm_data, &genpd->dev_list, list_node) {
1056
-		if (!atomic_read(&pm_data->dev->power.usage_count)) {
1057
-			enable_count = 0;
1058
-			if (!pm_runtime_enabled(pm_data->dev)) {
1059
-				pm_runtime_enable(pm_data->dev);
1060
-				enable_count = 1;
1061
-			}
1062
-			pm_runtime_get_sync(pm_data->dev);
1063
-			pm_runtime_put_sync(pm_data->dev);
1064
-			if (enable_count)
1065
-				pm_runtime_disable(pm_data->dev);
1066
-		}
1067
-	}
1068
-}
1069
-
1070
-static int __init rockchip_pd_keepon_release(void)
1312
+static void rockchip_pd_keepon_do_release(void)
10711313 {
10721314 	struct generic_pm_domain *genpd;
10731315 	struct rockchip_pm_domain *pd;
10741316 	int i;
10751317 
10761318 	if (!g_pmu)
1077
-		return 0;
1319
+		return;
10781320 
10791321 	for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
10801322 		genpd = g_pmu->genpd_data.domains[i];
....@@ -1082,10 +1324,21 @@
10821324 			pd = to_rockchip_pd(genpd);
10831325 			if (pd->info->always_on)
10841326 				continue;
1085
-			if (pd->info->keepon_startup)
1086
-				rockchip_pd_keepon_do_release(genpd, pd);
1327
+			if (!pd->info->keepon_startup)
1328
+				continue;
1329
+			if (!(genpd->flags & GENPD_FLAG_ALWAYS_ON))
1330
+				continue;
1331
+			genpd->flags &= (~GENPD_FLAG_ALWAYS_ON);
1332
+			queue_work(pm_wq, &genpd->power_off_work);
10871333 		}
10881334 	}
1335
+}
1336
+
1337
+#ifndef MODULE
1338
+static int __init rockchip_pd_keepon_release(void)
1339
+{
1340
+	rockchip_pd_keepon_do_release();
1341
+
10891342 	return 0;
10901343 }
10911344 late_initcall_sync(rockchip_pd_keepon_release);
....@@ -1093,14 +1346,32 @@
10931346 
10941347 static void __iomem *pd_base;
10951348 
1349
+static void dump_offset(const char *name, u32 offset)
1350
+{
1351
+	if (!offset)
1352
+		return;
1353
+
1354
+	pr_warn("%-9s 0x%04x: ", name, offset);
1355
+	print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 4, pd_base + offset, 16, false);
1356
+}
1357
+
10961358 void rockchip_dump_pmu(void)
10971359 {
1098
-	if (pd_base) {
1099
-		pr_warn("PMU:\n");
1100
-		print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1101
-			       32, 4, pd_base,
1102
-			       0x100, false);
1103
-	}
1360
+	if (!pd_base)
1361
+		return;
1362
+
1363
+	pr_warn("PMU:\n");
1364
+	dump_offset("pwr", g_pmu->info->pwr_offset);
1365
+	dump_offset("status", g_pmu->info->status_offset);
1366
+	dump_offset("req", g_pmu->info->req_offset);
1367
+	dump_offset("idle", g_pmu->info->idle_offset);
1368
+	dump_offset("ack", g_pmu->info->ack_offset);
1369
+	dump_offset("mem_pwr", g_pmu->info->mem_pwr_offset);
1370
+	dump_offset("chain_st", g_pmu->info->chain_status_offset);
1371
+	dump_offset("mem_st", g_pmu->info->mem_status_offset);
1372
+	dump_offset("repair_st", g_pmu->info->repair_status_offset);
1373
+	dump_offset("clkungate", g_pmu->info->clk_ungate_offset);
1374
+	dump_offset("mem_sd", g_pmu->info->mem_sd_offset);
11041375 }
11051376 EXPORT_SYMBOL_GPL(rockchip_dump_pmu);
11061377 
....@@ -1190,16 +1461,16 @@
11901461 	for_each_available_child_of_node(np, node) {
11911462 		error = rockchip_pm_add_one_domain(pmu, node);
11921463 		if (error) {
1193
-			dev_err(dev, "failed to handle node %s: %d\n",
1194
-				node->name, error);
1464
+			dev_err(dev, "failed to handle node %pOFn: %d\n",
1465
+				node, error);
11951466 			of_node_put(node);
11961467 			goto err_out;
11971468 		}
11981469 
11991470 		error = rockchip_pm_add_subdomain(pmu, node);
12001471 		if (error < 0) {
1201
-			dev_err(dev, "failed to handle subdomain node %s: %d\n",
1202
-				node->name, error);
1472
+			dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
1473
+				node, error);
12031474 			of_node_put(node);
12041475 			goto err_out;
12051476 		}
....@@ -1228,145 +1499,217 @@
12281499 }
12291500 
12301501 static const struct rockchip_domain_info px30_pm_domains[] = {
1231
-	[PX30_PD_USB]		= DOMAIN_PX30(BIT(5),  BIT(5),  BIT(10), true),
1232
-	[PX30_PD_SDCARD]	= DOMAIN_PX30(BIT(8),  BIT(8),  BIT(9),  false),
1233
-	[PX30_PD_GMAC]		= DOMAIN_PX30(BIT(10), BIT(10), BIT(6),  false),
1234
-	[PX30_PD_MMC_NAND]	= DOMAIN_PX30(BIT(11), BIT(11), BIT(5),  false),
1235
-	[PX30_PD_VPU]		= DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false),
1236
-	[PX30_PD_VO]		= DOMAIN_PX30_PROTECT(BIT(13), BIT(13), BIT(7),  false),
1237
-	[PX30_PD_VI]		= DOMAIN_PX30_PROTECT(BIT(14), BIT(14), BIT(8),  false),
1238
-	[PX30_PD_GPU]		= DOMAIN_PX30(BIT(15), BIT(15), BIT(2),  false),
1502
+	[PX30_PD_USB]		= DOMAIN_PX30("usb",        BIT(5),  BIT(5),  BIT(10), true),
1503
+	[PX30_PD_SDCARD]	= DOMAIN_PX30("sdcard",     BIT(8),  BIT(8),  BIT(9),  false),
1504
+	[PX30_PD_GMAC]		= DOMAIN_PX30("gmac",       BIT(10), BIT(10), BIT(6),  false),
1505
+	[PX30_PD_MMC_NAND]	= DOMAIN_PX30("mmc_nand",   BIT(11), BIT(11), BIT(5),  false),
1506
+	[PX30_PD_VPU]		= DOMAIN_PX30("vpu",        BIT(12), BIT(12), BIT(14), false),
1507
+	[PX30_PD_VO]		= DOMAIN_PX30_PROTECT("vo", BIT(13), BIT(13), BIT(7),  false),
1508
+	[PX30_PD_VI]		= DOMAIN_PX30_PROTECT("vi", BIT(14), BIT(14), BIT(8),  false),
1509
+	[PX30_PD_GPU]		= DOMAIN_PX30("gpu",        BIT(15), BIT(15), BIT(2),  false),
12391510 };
12401511 
12411512 static const struct rockchip_domain_info rv1126_pm_domains[] = {
1242
-	[RV1126_PD_CRYPTO]	= DOMAIN_RV1126_O(BIT(10), BIT(4), BIT(20), 0x4, false),
1243
-	[RV1126_PD_VEPU]	= DOMAIN_RV1126(BIT(2),  BIT(9),  BIT(9), false),
1244
-	[RV1126_PD_VI]		= DOMAIN_RV1126(BIT(4),  BIT(6),  BIT(6),  false),
1245
-	[RV1126_PD_VO]		= DOMAIN_RV1126_PROTECT(BIT(5), BIT(7), BIT(7),  false),
1246
-	[RV1126_PD_ISPP]	= DOMAIN_RV1126(BIT(1), BIT(8), BIT(8),  false),
1247
-	[RV1126_PD_VDPU]	= DOMAIN_RV1126(BIT(3), BIT(10), BIT(10), false),
1248
-	[RV1126_PD_NVM]		= DOMAIN_RV1126(BIT(7), BIT(11), BIT(11),  false),
1249
-	[RV1126_PD_SDIO]	= DOMAIN_RV1126(BIT(8), BIT(13), BIT(13),  false),
1250
-	[RV1126_PD_USB]		= DOMAIN_RV1126(BIT(9), BIT(15), BIT(15),  true),
1251
-	[RV1126_PD_NPU]		= DOMAIN_RV1126_O(BIT(0), BIT(2), BIT(18), 0x4, false),
1513
+	[RV1126_PD_CRYPTO]	= DOMAIN_RV1126_O("crypto",   BIT(10), BIT(4),  BIT(20), 0x4, false),
1514
+	[RV1126_PD_VEPU]	= DOMAIN_RV1126("vepu",       BIT(2),  BIT(9),  BIT(9),  false),
1515
+	[RV1126_PD_VI]		= DOMAIN_RV1126("vi",         BIT(4),  BIT(6),  BIT(6),  false),
1516
+	[RV1126_PD_VO]		= DOMAIN_RV1126_PROTECT("vo", BIT(5),  BIT(7),  BIT(7),  false),
1517
+	[RV1126_PD_ISPP]	= DOMAIN_RV1126("ispp",       BIT(1),  BIT(8),  BIT(8),  false),
1518
+	[RV1126_PD_VDPU]	= DOMAIN_RV1126("vdpu",       BIT(3),  BIT(10), BIT(10), false),
1519
+	[RV1126_PD_NVM]		= DOMAIN_RV1126("nvm",        BIT(7),  BIT(11), BIT(11), false),
1520
+	[RV1126_PD_SDIO]	= DOMAIN_RV1126("sdio",       BIT(8),  BIT(13), BIT(13), false),
1521
+	[RV1126_PD_USB]		= DOMAIN_RV1126("usb",        BIT(9),  BIT(15), BIT(15), true),
1522
+	[RV1126_PD_NPU]		= DOMAIN_RV1126_O("npu",      BIT(0),  BIT(2),  BIT(18), 0x4, false),
12521523 };
12531524 
12541525 static const struct rockchip_domain_info rk1808_pm_domains[] = {
1255
-	[RK1808_VD_NPU]		= DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false),
1256
-	[RK1808_PD_PCIE]	= DOMAIN_PX30(BIT(9),  BIT(9),  BIT(4), true),
1257
-	[RK1808_PD_VPU]		= DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false),
1258
-	[RK1808_PD_VIO]		= DOMAIN_PX30_PROTECT(BIT(14), BIT(14), BIT(8), false),
1526
+	[RK1808_VD_NPU]		= DOMAIN_PX30("npu",         BIT(15), BIT(15), BIT(2), false),
1527
+	[RK1808_PD_PCIE]	= DOMAIN_PX30("pcie",        BIT(9),  BIT(9),  BIT(4), true),
1528
+	[RK1808_PD_VPU]		= DOMAIN_PX30("vpu",         BIT(13), BIT(13), BIT(7), false),
1529
+	[RK1808_PD_VIO]		= DOMAIN_PX30_PROTECT("vio", BIT(14), BIT(14), BIT(8), false),
12591530 };
12601531 
12611532 static const struct rockchip_domain_info rk3036_pm_domains[] = {
1262
-	[RK3036_PD_MSCH]	= DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true),
1263
-	[RK3036_PD_CORE]	= DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false),
1264
-	[RK3036_PD_PERI]	= DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false),
1265
-	[RK3036_PD_VIO]		= DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false),
1266
-	[RK3036_PD_VPU]		= DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false),
1267
-	[RK3036_PD_GPU]		= DOMAIN_RK3036(BIT(9),  BIT(21), BIT(28), false),
1268
-	[RK3036_PD_SYS]		= DOMAIN_RK3036(BIT(8),  BIT(22), BIT(29), false),
1533
+	[RK3036_PD_MSCH]	= DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
1534
+	[RK3036_PD_CORE]	= DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
1535
+	[RK3036_PD_PERI]	= DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
1536
+	[RK3036_PD_VIO]		= DOMAIN_RK3036("vio",  BIT(11), BIT(19), BIT(26), false),
1537
+	[RK3036_PD_VPU]		= DOMAIN_RK3036("vpu",  BIT(10), BIT(20), BIT(27), false),
1538
+	[RK3036_PD_GPU]		= DOMAIN_RK3036("gpu",  BIT(9),  BIT(21), BIT(28), false),
1539
+	[RK3036_PD_SYS]		= DOMAIN_RK3036("sys",  BIT(8),  BIT(22), BIT(29), false),
1540
+};
1541
+
1542
+static const struct rockchip_domain_info rk3066_pm_domains[] = {
1543
+	[RK3066_PD_GPU]		= DOMAIN("gpu",   BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false, false),
1544
+	[RK3066_PD_VIDEO]	= DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false, false),
1545
+	[RK3066_PD_VIO]		= DOMAIN("vio",   BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false, true),
1546
+	[RK3066_PD_PERI]	= DOMAIN("peri",  BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false, false),
1547
+	[RK3066_PD_CPU]		= DOMAIN("cpu",   0,      BIT(5), BIT(1), BIT(26), BIT(31), false, false),
12691548 };
12701549 
12711550 static const struct rockchip_domain_info rk3128_pm_domains[] = {
1272
-	[RK3128_PD_CORE]	= DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false),
1273
-	[RK3128_PD_MSCH]	= DOMAIN_RK3288(0,      0,      BIT(6), true),
1274
-	[RK3128_PD_VIO]		= DOMAIN_RK3288_PROTECT(BIT(3), BIT(3), BIT(2), false),
1275
-	[RK3128_PD_VIDEO]	= DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false),
1276
-	[RK3128_PD_GPU]		= DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false),
1551
+	[RK3128_PD_CORE]        = DOMAIN_RK3288("core",        BIT(0), BIT(0), BIT(4), false),
1552
+	[RK3128_PD_MSCH]        = DOMAIN_RK3288("msch",        0,      0,      BIT(6), true),
1553
+	[RK3128_PD_VIO]         = DOMAIN_RK3288_PROTECT("vio", BIT(3), BIT(3), BIT(2), false),
1554
+	[RK3128_PD_VIDEO]       = DOMAIN_RK3288("video",       BIT(2), BIT(2), BIT(1), false),
1555
+	[RK3128_PD_GPU]         = DOMAIN_RK3288("gpu",         BIT(1), BIT(1), BIT(3), false),
1556
+};
1557
+
1558
+static const struct rockchip_domain_info rk3188_pm_domains[] = {
1559
+	[RK3188_PD_GPU]         = DOMAIN("gpu",   BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false, false),
1560
+	[RK3188_PD_VIDEO]	= DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false, false),
1561
+	[RK3188_PD_VIO]		= DOMAIN("vio",   BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false, true),
1562
+	[RK3188_PD_PERI]	= DOMAIN("peri",  BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false, false),
1563
+	[RK3188_PD_CPU]		= DOMAIN("cpu",   BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false, false),
12771564 };
12781565 
12791566 static const struct rockchip_domain_info rk3228_pm_domains[] = {
1280
-	[RK3228_PD_CORE]	= DOMAIN_RK3036(BIT(0),  BIT(0),  BIT(16), true),
1281
-	[RK3228_PD_MSCH]	= DOMAIN_RK3036(BIT(1),  BIT(1),  BIT(17), true),
1282
-	[RK3228_PD_BUS]		= DOMAIN_RK3036(BIT(2),  BIT(2),  BIT(18), true),
1283
-	[RK3228_PD_SYS]		= DOMAIN_RK3036(BIT(3),  BIT(3),  BIT(19), true),
1284
-	[RK3228_PD_VIO]		= DOMAIN_RK3036(BIT(4),  BIT(4),  BIT(20), false),
1285
-	[RK3228_PD_VOP]		= DOMAIN_RK3036(BIT(5),  BIT(5),  BIT(21), false),
1286
-	[RK3228_PD_VPU]		= DOMAIN_RK3036(BIT(6),  BIT(6),  BIT(22), false),
1287
-	[RK3228_PD_RKVDEC]	= DOMAIN_RK3036(BIT(7),  BIT(7),  BIT(23), false),
1288
-	[RK3228_PD_GPU]		= DOMAIN_RK3036(BIT(8),  BIT(8),  BIT(24), false),
1289
-	[RK3228_PD_PERI]	= DOMAIN_RK3036(BIT(9),  BIT(9),  BIT(25), true),
1290
-	[RK3228_PD_GMAC]	= DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false),
1567
+	[RK3228_PD_CORE]	= DOMAIN_RK3036("core", BIT(0),  BIT(0),  BIT(16), true),
1568
+	[RK3228_PD_MSCH]	= DOMAIN_RK3036("msch", BIT(1),  BIT(1),  BIT(17), true),
1569
+	[RK3228_PD_BUS]		= DOMAIN_RK3036("bus",  BIT(2),  BIT(2),  BIT(18), true),
1570
+	[RK3228_PD_SYS]		= DOMAIN_RK3036("sys",  BIT(3),  BIT(3),  BIT(19), true),
1571
+	[RK3228_PD_VIO]		= DOMAIN_RK3036("vio",  BIT(4),  BIT(4),  BIT(20), false),
1572
+	[RK3228_PD_VOP]		= DOMAIN_RK3036("vop",  BIT(5),  BIT(5),  BIT(21), false),
1573
+	[RK3228_PD_VPU]		= DOMAIN_RK3036("vpu",  BIT(6),  BIT(6),  BIT(22), false),
1574
+	[RK3228_PD_RKVDEC]	= DOMAIN_RK3036("vdec", BIT(7),  BIT(7),  BIT(23), false),
1575
+	[RK3228_PD_GPU]		= DOMAIN_RK3036("gpu",  BIT(8),  BIT(8),  BIT(24), false),
1576
+	[RK3228_PD_PERI]	= DOMAIN_RK3036("peri", BIT(9),  BIT(9),  BIT(25), true),
1577
+	[RK3228_PD_GMAC]	= DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
12911578 };
12921579 
12931580 static const struct rockchip_domain_info rk3288_pm_domains[] = {
1294
-	[RK3288_PD_VIO]		= DOMAIN_RK3288_PROTECT(BIT(7),  BIT(7),  BIT(4), false),
1295
-	[RK3288_PD_HEVC]	= DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false),
1296
-	[RK3288_PD_VIDEO]	= DOMAIN_RK3288(BIT(8),  BIT(8),  BIT(3), false),
1297
-	[RK3288_PD_GPU]		= DOMAIN_RK3288(BIT(9),  BIT(9),  BIT(2), false),
1581
+	[RK3288_PD_VIO]		= DOMAIN_RK3288_PROTECT("vio", BIT(7),  BIT(7),  BIT(4), false),
1582
+	[RK3288_PD_HEVC]	= DOMAIN_RK3288("hevc",        BIT(14), BIT(10), BIT(9), false),
1583
+	[RK3288_PD_VIDEO]	= DOMAIN_RK3288("video",       BIT(8),  BIT(8),  BIT(3), false),
1584
+	[RK3288_PD_GPU]		= DOMAIN_RK3288("gpu",         BIT(9),  BIT(9),  BIT(2), false),
12981585 };
12991586 
13001587 static const struct rockchip_domain_info rk3328_pm_domains[] = {
1301
-	[RK3328_PD_CORE]	= DOMAIN_RK3328(0, BIT(0), BIT(0), false),
1302
-	[RK3328_PD_GPU]		= DOMAIN_RK3328(0, BIT(1), BIT(1), false),
1303
-	[RK3328_PD_BUS]		= DOMAIN_RK3328(0, BIT(2), BIT(2), true),
1304
-	[RK3328_PD_MSCH]	= DOMAIN_RK3328(0, BIT(3), BIT(3), true),
1305
-	[RK3328_PD_PERI]	= DOMAIN_RK3328(0, BIT(4), BIT(4), true),
1306
-	[RK3328_PD_VIDEO]	= DOMAIN_RK3328(0, BIT(5), BIT(5), false),
1307
-	[RK3328_PD_HEVC]	= DOMAIN_RK3328(0, BIT(6), BIT(6), false),
1308
-	[RK3328_PD_VIO]		= DOMAIN_RK3328(0, BIT(8), BIT(8), false),
1309
-	[RK3328_PD_VPU]		= DOMAIN_RK3328(0, BIT(9), BIT(9), false),
1588
+	[RK3328_PD_CORE]	= DOMAIN_RK3328("core",  0, BIT(0), BIT(0), false),
1589
+	[RK3328_PD_GPU]		= DOMAIN_RK3328("gpu",   0, BIT(1), BIT(1), false),
1590
+	[RK3328_PD_BUS]		= DOMAIN_RK3328("bus",   0, BIT(2), BIT(2), true),
1591
+	[RK3328_PD_MSCH]	= DOMAIN_RK3328("msch",  0, BIT(3), BIT(3), true),
1592
+	[RK3328_PD_PERI]	= DOMAIN_RK3328("peri",  0, BIT(4), BIT(4), true),
1593
+	[RK3328_PD_VIDEO]	= DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1594
+	[RK3328_PD_HEVC]	= DOMAIN_RK3328("hevc",  0, BIT(6), BIT(6), false),
1595
+	[RK3328_PD_VIO]		= DOMAIN_RK3328("vio",   0, BIT(8), BIT(8), false),
1596
+	[RK3328_PD_VPU]		= DOMAIN_RK3328("vpu",   0, BIT(9), BIT(9), false),
13101597 };
13111598 
13121599 static const struct rockchip_domain_info rk3366_pm_domains[] = {
1313
-	[RK3366_PD_PERI]	= DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true),
1314
-	[RK3366_PD_VIO]		= DOMAIN_RK3368_PROTECT(BIT(14), BIT(14), BIT(8), false),
1315
-	[RK3366_PD_VIDEO]	= DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false),
1316
-	[RK3366_PD_RKVDEC]	= DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false),
1317
-	[RK3366_PD_WIFIBT]	= DOMAIN_RK3368(BIT(8),  BIT(8),  BIT(9), false),
1318
-	[RK3366_PD_VPU]		= DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false),
1319
-	[RK3366_PD_GPU]		= DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false),
1600
+	[RK3366_PD_PERI]	= DOMAIN_RK3368("peri",        BIT(10), BIT(10), BIT(6), true),
1601
+	[RK3366_PD_VIO]		= DOMAIN_RK3368_PROTECT("vio", BIT(14), BIT(14), BIT(8), false),
1602
+	[RK3366_PD_VIDEO]	= DOMAIN_RK3368("video",       BIT(13), BIT(13), BIT(7), false),
1603
+	[RK3366_PD_RKVDEC]	= DOMAIN_RK3368("rkvdec",      BIT(11), BIT(11), BIT(7), false),
1604
+	[RK3366_PD_WIFIBT]	= DOMAIN_RK3368("wifibt",      BIT(8),  BIT(8),  BIT(9), false),
1605
+	[RK3366_PD_VPU]		= DOMAIN_RK3368("vpu",         BIT(12), BIT(12), BIT(7), false),
1606
+	[RK3366_PD_GPU]		= DOMAIN_RK3368("gpu",         BIT(15), BIT(15), BIT(2), false),
13201607 };
13211608 
13221609 static const struct rockchip_domain_info rk3368_pm_domains[] = {
1323
-	[RK3368_PD_PERI]	= DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true),
1324
-	[RK3368_PD_VIO]		= DOMAIN_RK3368_PROTECT(BIT(15), BIT(14), BIT(8), false),
1325
-	[RK3368_PD_VIDEO]	= DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false),
1326
-	[RK3368_PD_GPU_0]	= DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false),
1327
-	[RK3368_PD_GPU_1]	= DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false),
1610
+	[RK3368_PD_PERI]	= DOMAIN_RK3368("peri",        BIT(13), BIT(12), BIT(6), true),
1611
+	[RK3368_PD_VIO]		= DOMAIN_RK3368_PROTECT("vio", BIT(15), BIT(14), BIT(8), false),
1612
+	[RK3368_PD_VIDEO]	= DOMAIN_RK3368("video",       BIT(14), BIT(13), BIT(7), false),
1613
+	[RK3368_PD_GPU_0]	= DOMAIN_RK3368("gpu_0",       BIT(16), BIT(15), BIT(2), false),
1614
+	[RK3368_PD_GPU_1]	= DOMAIN_RK3368("gpu_1",       BIT(17), BIT(16), BIT(2), false),
13281615 };
13291616 
13301617 static const struct rockchip_domain_info rk3399_pm_domains[] = {
1331
-	[RK3399_PD_TCPD0]	= DOMAIN_RK3399(BIT(8),  BIT(8),  0,	   false),
1332
-	[RK3399_PD_TCPD1]	= DOMAIN_RK3399(BIT(9),  BIT(9),  0,	   false),
1333
-	[RK3399_PD_CCI]		= DOMAIN_RK3399(BIT(10), BIT(10), 0,	   true),
1334
-	[RK3399_PD_CCI0]	= DOMAIN_RK3399(0,	 0,	  BIT(15), true),
1335
-	[RK3399_PD_CCI1]	= DOMAIN_RK3399(0,	 0,	  BIT(16), true),
1336
-	[RK3399_PD_PERILP]	= DOMAIN_RK3399(BIT(11), BIT(11), BIT(1),  true),
1337
-	[RK3399_PD_PERIHP]	= DOMAIN_RK3399(BIT(12), BIT(12), BIT(2),  true),
1338
-	[RK3399_PD_CENTER]	= DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true),
1339
-	[RK3399_PD_VIO]		= DOMAIN_RK3399_PROTECT(BIT(14), BIT(14), BIT(17), false),
1340
-	[RK3399_PD_GPU]		= DOMAIN_RK3399(BIT(15), BIT(15), BIT(0),  false),
1341
-	[RK3399_PD_VCODEC]	= DOMAIN_RK3399(BIT(16), BIT(16), BIT(3),  false),
1342
-	[RK3399_PD_VDU]		= DOMAIN_RK3399(BIT(17), BIT(17), BIT(4),  false),
1343
-	[RK3399_PD_RGA]		= DOMAIN_RK3399(BIT(18), BIT(18), BIT(5),  false),
1344
-	[RK3399_PD_IEP]		= DOMAIN_RK3399(BIT(19), BIT(19), BIT(6),  false),
1345
-	[RK3399_PD_VO]		= DOMAIN_RK3399_PROTECT(BIT(20), BIT(20), 0,	   false),
1346
-	[RK3399_PD_VOPB]	= DOMAIN_RK3399_PROTECT(0,	 0,	  BIT(7),  false),
1347
-	[RK3399_PD_VOPL]	= DOMAIN_RK3399_PROTECT(0, 	 0,	  BIT(8),  false),
1348
-	[RK3399_PD_ISP0]	= DOMAIN_RK3399(BIT(22), BIT(22), BIT(9),  false),
1349
-	[RK3399_PD_ISP1]	= DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false),
1350
-	[RK3399_PD_HDCP]	= DOMAIN_RK3399_PROTECT(BIT(24), BIT(24), BIT(11), false),
1351
-	[RK3399_PD_GMAC]	= DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true),
1352
-	[RK3399_PD_EMMC]	= DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true),
1353
-	[RK3399_PD_USB3]	= DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true),
1354
-	[RK3399_PD_EDP]		= DOMAIN_RK3399_PROTECT(BIT(28), BIT(28), BIT(22), false),
1355
-	[RK3399_PD_GIC]		= DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true),
1356
-	[RK3399_PD_SD]		= DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true),
1357
-	[RK3399_PD_SDIOAUDIO]	= DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true),
1618
+	[RK3399_PD_TCPD0]	= DOMAIN_RK3399("tcpd0",        BIT(8),  BIT(8),  0,       false),
1619
+	[RK3399_PD_TCPD1]	= DOMAIN_RK3399("tcpd1",        BIT(9),  BIT(9),  0,       false),
1620
+	[RK3399_PD_CCI]		= DOMAIN_RK3399("cci",          BIT(10), BIT(10), 0,       true),
1621
+	[RK3399_PD_CCI0]	= DOMAIN_RK3399("cci0",         0,       0,       BIT(15), true),
1622
+	[RK3399_PD_CCI1]	= DOMAIN_RK3399("cci1",         0,       0,       BIT(16), true),
1623
+	[RK3399_PD_PERILP]	= DOMAIN_RK3399("perilp",       BIT(11), BIT(11), BIT(1),  true),
1624
+	[RK3399_PD_PERIHP]	= DOMAIN_RK3399("perihp",       BIT(12), BIT(12), BIT(2),  true),
1625
+	[RK3399_PD_CENTER]	= DOMAIN_RK3399("center",       BIT(13), BIT(13), BIT(14), true),
1626
+	[RK3399_PD_VIO]		= DOMAIN_RK3399_PROTECT("vio",  BIT(14), BIT(14), BIT(17), false),
1627
+	[RK3399_PD_GPU]		= DOMAIN_RK3399("gpu",          BIT(15), BIT(15), BIT(0),  false),
1628
+	[RK3399_PD_VCODEC]	= DOMAIN_RK3399("vcodec",       BIT(16), BIT(16), BIT(3),  false),
1629
+	[RK3399_PD_VDU]		= DOMAIN_RK3399("vdu",          BIT(17), BIT(17), BIT(4),  false),
1630
+	[RK3399_PD_RGA]		= DOMAIN_RK3399("rga",          BIT(18), BIT(18), BIT(5),  false),
1631
+	[RK3399_PD_IEP]		= DOMAIN_RK3399("iep",          BIT(19), BIT(19), BIT(6),  false),
1632
+	[RK3399_PD_VO]		= DOMAIN_RK3399_PROTECT("vo",   BIT(20), BIT(20), 0,       false),
1633
+	[RK3399_PD_VOPB]	= DOMAIN_RK3399_PROTECT("vopb", 0,       0,       BIT(7),  false),
1634
+	[RK3399_PD_VOPL]	= DOMAIN_RK3399_PROTECT("vopl", 0,       0,       BIT(8),  false),
1635
+	[RK3399_PD_ISP0]	= DOMAIN_RK3399("isp0",         BIT(22), BIT(22), BIT(9),  false),
1636
+	[RK3399_PD_ISP1]	= DOMAIN_RK3399("isp1",         BIT(23), BIT(23), BIT(10), false),
1637
+	[RK3399_PD_HDCP]	= DOMAIN_RK3399_PROTECT("hdcp", BIT(24), BIT(24), BIT(11), false),
1638
+	[RK3399_PD_GMAC]	= DOMAIN_RK3399("gmac",         BIT(25), BIT(25), BIT(23), true),
1639
+	[RK3399_PD_EMMC]	= DOMAIN_RK3399("emmc",         BIT(26), BIT(26), BIT(24), true),
1640
+	[RK3399_PD_USB3]	= DOMAIN_RK3399("usb3",         BIT(27), BIT(27), BIT(12), true),
1641
+	[RK3399_PD_EDP]		= DOMAIN_RK3399_PROTECT("edp",  BIT(28), BIT(28), BIT(22), false),
1642
+	[RK3399_PD_GIC]		= DOMAIN_RK3399("gic",          BIT(29), BIT(29), BIT(27), true),
1643
+	[RK3399_PD_SD]		= DOMAIN_RK3399("sd",           BIT(30), BIT(30), BIT(28), true),
1644
+	[RK3399_PD_SDIOAUDIO]	= DOMAIN_RK3399("sdioaudio",    BIT(31), BIT(31), BIT(29), true),
1645
+};
1646
+
1647
+static const struct rockchip_domain_info rk3528_pm_domains[] = {
1648
+	[RK3528_PD_PMU]		= DOMAIN_RK3528(0, BIT(0), true, false),
1649
+	[RK3528_PD_BUS]		= DOMAIN_RK3528(0, BIT(1), true, false),
1650
+	[RK3528_PD_DDR]		= DOMAIN_RK3528(0, BIT(2), true, false),
1651
+	[RK3528_PD_MSCH]	= DOMAIN_RK3528(0, BIT(3), true, false),
1652
+	[RK3528_PD_GPU]		= DOMAIN_RK3528(BIT(0), BIT(4), true, false),
1653
+	[RK3528_PD_RKVDEC]	= DOMAIN_RK3528(0, BIT(5), true, false),
1654
+	[RK3528_PD_RKVENC]	= DOMAIN_RK3528(0, BIT(6), true, false),
1655
+	[RK3528_PD_VO]		= DOMAIN_RK3528(0,  BIT(7), true, false),
1656
+	[RK3528_PD_VPU]		= DOMAIN_RK3528(0, BIT(8), true, false),
1657
+};
1658
+
1659
+static const struct rockchip_domain_info rk3562_pm_domains[] = {
1660
+	[RK3562_PD_GPU]		= DOMAIN_RK3562("gpu",         BIT(0), BIT(1), 0, false),
1661
+	[RK3562_PD_NPU]		= DOMAIN_RK3562("npu",         BIT(1), BIT(2), 0, false),
1662
+	[RK3562_PD_VDPU]	= DOMAIN_RK3562("vdpu",        BIT(2), BIT(6), 0, false),
1663
+	[RK3562_PD_VEPU]	= DOMAIN_RK3562("vepu",        BIT(3), BIT(7), 0, false),
1664
+	[RK3562_PD_RGA]		= DOMAIN_RK3562("rga",         BIT(4), BIT(5), 0, false),
1665
+	[RK3562_PD_VI]		= DOMAIN_RK3562("vi",          BIT(5), BIT(3), 0, false),
1666
+	[RK3562_PD_VO]		= DOMAIN_RK3562_PROTECT("vo",  BIT(6), BIT(4), 16, false),
1667
+	[RK3562_PD_PHP]		= DOMAIN_RK3562("php",         BIT(7), BIT(8), 0, false),
13581668 };
13591669 
13601670 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1361
-	[RK3568_PD_NPU]		= DOMAIN_RK3568(BIT(1), BIT(2), false),
1362
-	[RK3568_PD_GPU]		= DOMAIN_RK3568(BIT(0), BIT(1), false),
1363
-	[RK3568_PD_VI]		= DOMAIN_RK3568(BIT(6), BIT(3), false),
1364
-	[RK3568_PD_VO]		= DOMAIN_RK3568_PROTECT(BIT(7),  BIT(4), false),
1365
-	[RK3568_PD_RGA]		= DOMAIN_RK3568(BIT(5),  BIT(5), false),
1366
-	[RK3568_PD_VPU]		= DOMAIN_RK3568(BIT(2), BIT(6), false),
1367
-	[RK3568_PD_RKVDEC]	= DOMAIN_RK3568(BIT(4), BIT(8), false),
1368
-	[RK3568_PD_RKVENC]	= DOMAIN_RK3568(BIT(3), BIT(7), false),
1369
-	[RK3568_PD_PIPE]	= DOMAIN_RK3568(BIT(8), BIT(11), false),
1671
+	[RK3568_PD_NPU]		= DOMAIN_RK3568("npu",        BIT(1), BIT(2),  false),
1672
+	[RK3568_PD_GPU]		= DOMAIN_RK3568("gpu",        BIT(0), BIT(1),  false),
1673
+	[RK3568_PD_VI]		= DOMAIN_RK3568("vi",         BIT(6), BIT(3),  false),
1674
+	[RK3568_PD_VO]		= DOMAIN_RK3568_PROTECT("vo", BIT(7), BIT(4),  false),
1675
+	[RK3568_PD_RGA]		= DOMAIN_RK3568("rga",        BIT(5), BIT(5),  false),
1676
+	[RK3568_PD_VPU]		= DOMAIN_RK3568("vpu",        BIT(2), BIT(6),  false),
1677
+	[RK3568_PD_RKVDEC]	= DOMAIN_RK3568("rkvdec",     BIT(4), BIT(8),  false),
1678
+	[RK3568_PD_RKVENC]	= DOMAIN_RK3568("rkvenc",     BIT(3), BIT(7),  false),
1679
+	[RK3568_PD_PIPE]	= DOMAIN_RK3568("pipe",       BIT(8), BIT(11), false),
1680
+};
1681
+
1682
+static const struct rockchip_domain_info rk3588_pm_domains[] = {
1683
+					     /* name   p_offset pwr   status  m_offset m_status r_status r_offset req  idle     wakeup */
1684
+	[RK3588_PD_GPU]		= DOMAIN_RK3588("gpu",     0x0, BIT(0),  0,       0x0, 0,       BIT(1),  0x0, BIT(0),  BIT(0),  false),
1685
+	[RK3588_PD_NPU]		= DOMAIN_RK3588("npu",     0x0, BIT(1),  BIT(1),  0x0, 0,       0,       0x0, 0,       0,       false),
1686
+	[RK3588_PD_VCODEC]	= DOMAIN_RK3588("vcodec",  0x0, BIT(2),  BIT(2),  0x0, 0,       0,       0x0, 0,       0,       false),
1687
+	[RK3588_PD_NPUTOP]	= DOMAIN_RK3588("nputop",  0x0, BIT(3),  0,       0x0, BIT(11), BIT(2),  0x0, BIT(1),  BIT(1),  false),
1688
+	[RK3588_PD_NPU1]	= DOMAIN_RK3588("npu1",    0x0, BIT(4),  0,       0x0, BIT(12), BIT(3),  0x0, BIT(2),  BIT(2),  false),
1689
+	[RK3588_PD_NPU2]	= DOMAIN_RK3588("npu2",    0x0, BIT(5),  0,       0x0, BIT(13), BIT(4),  0x0, BIT(3),  BIT(3),  false),
1690
+	[RK3588_PD_VENC0]	= DOMAIN_RK3588("venc0",   0x0, BIT(6),  0,       0x0, BIT(14), BIT(5),  0x0, BIT(4),  BIT(4),  false),
1691
+	[RK3588_PD_VENC1]	= DOMAIN_RK3588("venc1",   0x0, BIT(7),  0,       0x0, BIT(15), BIT(6),  0x0, BIT(5),  BIT(5),  false),
1692
+	[RK3588_PD_RKVDEC0]	= DOMAIN_RK3588("rkvdec0", 0x0, BIT(8),  0,       0x0, BIT(16), BIT(7),  0x0, BIT(6),  BIT(6),  false),
1693
+	[RK3588_PD_RKVDEC1]	= DOMAIN_RK3588("rkvdec1", 0x0, BIT(9),  0,       0x0, BIT(17), BIT(8),  0x0, BIT(7),  BIT(7),  false),
1694
+	[RK3588_PD_VDPU]	= DOMAIN_RK3588("vdpu",    0x0, BIT(10), 0,       0x0, BIT(18), BIT(9),  0x0, BIT(8),  BIT(8),  false),
1695
+	[RK3588_PD_RGA30]	= DOMAIN_RK3588("rga30",   0x0, BIT(11), 0,       0x0, BIT(19), BIT(10), 0x0, 0,       0,       false),
1696
+	[RK3588_PD_AV1]		= DOMAIN_RK3588("av1",     0x0, BIT(12), 0,       0x0, BIT(20), BIT(11), 0x0, BIT(9),  BIT(9),  false),
1697
+	[RK3588_PD_VI]		= DOMAIN_RK3588("vi",      0x0, BIT(13), 0,       0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
1698
+	[RK3588_PD_FEC]		= DOMAIN_RK3588("fec",     0x0, BIT(14), 0,       0x0, BIT(22), BIT(13), 0x0, 0,       0,       false),
1699
+	[RK3588_PD_ISP1]	= DOMAIN_RK3588("isp1",    0x0, BIT(15), 0,       0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
1700
+	[RK3588_PD_RGA31]	= DOMAIN_RK3588("rga31",   0x4, BIT(0),  0,       0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
1701
+	[RK3588_PD_VOP]		= DOMAIN_RK3588_P("vop",   0x4, BIT(1),  0,       0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
1702
+	[RK3588_PD_VO0]		= DOMAIN_RK3588_P("vo0",   0x4, BIT(2),  0,       0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
1703
+	[RK3588_PD_VO1]		= DOMAIN_RK3588_P("vo1",   0x4, BIT(3),  0,       0x0, BIT(27), BIT(18), 0x4, BIT(0),  BIT(16), false),
1704
+	[RK3588_PD_AUDIO]	= DOMAIN_RK3588("audio",   0x4, BIT(4),  0,       0x0, BIT(28), BIT(19), 0x4, BIT(1),  BIT(17), false),
1705
+	[RK3588_PD_PHP]		= DOMAIN_RK3588("php",     0x4, BIT(5),  0,       0x0, BIT(29), BIT(20), 0x4, BIT(5),  BIT(21), false),
1706
+	[RK3588_PD_GMAC]	= DOMAIN_RK3588("gmac",    0x4, BIT(6),  0,       0x0, BIT(30), BIT(21), 0x0, 0,       0,       false),
1707
+	[RK3588_PD_PCIE]	= DOMAIN_RK3588("pcie",    0x4, BIT(7),  0,       0x0, BIT(31), BIT(22), 0x0, 0,       0,       true),
1708
+	[RK3588_PD_NVM]		= DOMAIN_RK3588("nvm",     0x4, BIT(8),  BIT(24), 0x4, 0,       0,       0x4, BIT(2),  BIT(18), false),
1709
+	[RK3588_PD_NVM0]	= DOMAIN_RK3588("nvm0",    0x4, BIT(9),  0,       0x4, BIT(1),  BIT(23), 0x0, 0,       0,       false),
1710
+	[RK3588_PD_SDIO]	= DOMAIN_RK3588("sdio",    0x4, BIT(10), 0,       0x4, BIT(2),  BIT(24), 0x4, BIT(3),  BIT(19), false),
1711
+	[RK3588_PD_USB]		= DOMAIN_RK3588("usb",     0x4, BIT(11), 0,       0x4, BIT(3),  BIT(25), 0x4, BIT(4),  BIT(20), true),
1712
+	[RK3588_PD_SDMMC]	= DOMAIN_RK3588("sdmmc",   0x4, BIT(13), 0,       0x4, BIT(5),  BIT(26), 0x0, 0,       0,       false),
13701713 };
13711714 
13721715 static const struct rockchip_pmu_info px30_pmu = {
....@@ -1378,17 +1721,6 @@
13781721 
13791722 	.num_domains = ARRAY_SIZE(px30_pm_domains),
13801723 	.domain_info = px30_pm_domains,
1381
-};
1382
-
1383
-static const struct rockchip_pmu_info rv1126_pmu = {
1384
-	.pwr_offset = 0x110,
1385
-	.status_offset = 0x108,
1386
-	.req_offset = 0xc0,
1387
-	.idle_offset = 0xd8,
1388
-	.ack_offset = 0xd0,
1389
-
1390
-	.num_domains = ARRAY_SIZE(rv1126_pm_domains),
1391
-	.domain_info = rv1126_pm_domains,
13921724 };
13931725 
13941726 static const struct rockchip_pmu_info rk1808_pmu = {
....@@ -1411,6 +1743,17 @@
14111743 	.domain_info = rk3036_pm_domains,
14121744 };
14131745 
1746
+static const struct rockchip_pmu_info rk3066_pmu = {
1747
+	.pwr_offset = 0x08,
1748
+	.status_offset = 0x0c,
1749
+	.req_offset = 0x38, /* PMU_MISC_CON1 */
1750
+	.idle_offset = 0x0c,
1751
+	.ack_offset = 0x0c,
1752
+
1753
+	.num_domains = ARRAY_SIZE(rk3066_pm_domains),
1754
+	.domain_info = rk3066_pm_domains,
1755
+};
1756
+
14141757 static const struct rockchip_pmu_info rk3128_pmu = {
14151758 	.pwr_offset = 0x04,
14161759 	.status_offset = 0x08,
....@@ -1420,6 +1763,17 @@
14201763 
14211764 	.num_domains = ARRAY_SIZE(rk3128_pm_domains),
14221765 	.domain_info = rk3128_pm_domains,
1766
+};
1767
+
1768
+static const struct rockchip_pmu_info rk3188_pmu = {
1769
+	.pwr_offset = 0x08,
1770
+	.status_offset = 0x0c,
1771
+	.req_offset = 0x38, /* PMU_MISC_CON1 */
1772
+	.idle_offset = 0x0c,
1773
+	.ack_offset = 0x0c,
1774
+
1775
+	.num_domains = ARRAY_SIZE(rk3188_pm_domains),
1776
+	.domain_info = rk3188_pm_domains,
14231777 };
14241778 
14251779 static const struct rockchip_pmu_info rk3228_pmu = {
....@@ -1498,14 +1852,34 @@
14981852 	.idle_offset = 0x64,
14991853 	.ack_offset = 0x68,
15001854 
1501
-	.core_pwrcnt_offset = 0xac,
1502
-	.gpu_pwrcnt_offset = 0xac,
1503
-
1504
-	.core_power_transition_time = 6, /* 0.25us */
1505
-	.gpu_power_transition_time = 6, /* 0.25us */
1855
+	/* ARM Trusted Firmware manages power transition times */
15061856 
15071857 	.num_domains = ARRAY_SIZE(rk3399_pm_domains),
15081858 	.domain_info = rk3399_pm_domains,
1859
+};
1860
+
1861
+static const struct rockchip_pmu_info rk3528_pmu = {
1862
+	.pwr_offset = 0x1210,
1863
+	.status_offset = 0x1230,
1864
+	.req_offset = 0x1110,
1865
+	.idle_offset = 0x1128,
1866
+	.ack_offset = 0x1120,
1867
+
1868
+	.num_domains = ARRAY_SIZE(rk3528_pm_domains),
1869
+	.domain_info = rk3528_pm_domains,
1870
+};
1871
+
1872
+static const struct rockchip_pmu_info rk3562_pmu = {
1873
+	.pwr_offset = 0x210,
1874
+	.status_offset = 0x230,
1875
+	.req_offset = 0x110,
1876
+	.idle_offset = 0x128,
1877
+	.ack_offset = 0x120,
1878
+	.clk_ungate_offset = 0x140,
1879
+	.mem_sd_offset = 0x300,
1880
+
1881
+	.num_domains = ARRAY_SIZE(rk3562_pm_domains),
1882
+	.domain_info = rk3562_pm_domains,
15091883 };
15101884 
15111885 static const struct rockchip_pmu_info rk3568_pmu = {
....@@ -1519,79 +1893,103 @@
15191893 	.domain_info = rk3568_pm_domains,
15201894 };
15211895 
1896
+static const struct rockchip_pmu_info rk3588_pmu = {
1897
+	.pwr_offset = 0x14c,
1898
+	.status_offset = 0x180,
1899
+	.req_offset = 0x10c,
1900
+	.idle_offset = 0x120,
1901
+	.ack_offset = 0x118,
1902
+	.mem_pwr_offset = 0x1a0,
1903
+	.chain_status_offset = 0x1f0,
1904
+	.mem_status_offset = 0x1f8,
1905
+	.repair_status_offset = 0x290,
1906
+
1907
+	.num_domains = ARRAY_SIZE(rk3588_pm_domains),
1908
+	.domain_info = rk3588_pm_domains,
1909
+};
1910
+
1911
+static const struct rockchip_pmu_info rv1126_pmu = {
1912
+	.pwr_offset = 0x110,
1913
+	.status_offset = 0x108,
1914
+	.req_offset = 0xc0,
1915
+	.idle_offset = 0xd8,
1916
+	.ack_offset = 0xd0,
1917
+
1918
+	.num_domains = ARRAY_SIZE(rv1126_pm_domains),
1919
+	.domain_info = rv1126_pm_domains,
1920
+};
1921
+
15221922 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1523
-#ifdef CONFIG_CPU_PX30
15241923 	{
15251924 		.compatible = "rockchip,px30-power-controller",
15261925 		.data = (void *)&px30_pmu,
15271926 	},
1528
-#endif
1529
-#ifdef CONFIG_CPU_RV1126
1530
-	{
1531
-		.compatible = "rockchip,rv1126-power-controller",
1532
-		.data = (void *)&rv1126_pmu,
1533
-	},
1534
-#endif
1535
-#ifdef CONFIG_CPU_RK1808
15361927 	{
15371928 		.compatible = "rockchip,rk1808-power-controller",
15381929 		.data = (void *)&rk1808_pmu,
15391930 	},
1540
-#endif
1541
-#ifdef CONFIG_CPU_RK3036
15421931 	{
15431932 		.compatible = "rockchip,rk3036-power-controller",
15441933 		.data = (void *)&rk3036_pmu,
15451934 	},
1546
-#endif
1547
-#ifdef CONFIG_CPU_RK312X
1935
+	{
1936
+		.compatible = "rockchip,rk3066-power-controller",
1937
+		.data = (void *)&rk3066_pmu,
1938
+	},
15481939 	{
15491940 		.compatible = "rockchip,rk3128-power-controller",
15501941 		.data = (void *)&rk3128_pmu,
15511942 	},
1552
-#endif
1553
-#ifdef CONFIG_CPU_RK322X
1943
+	{
1944
+		.compatible = "rockchip,rk3188-power-controller",
1945
+		.data = (void *)&rk3188_pmu,
1946
+	},
15541947 	{
15551948 		.compatible = "rockchip,rk3228-power-controller",
15561949 		.data = (void *)&rk3228_pmu,
15571950 	},
1558
-#endif
1559
-#ifdef CONFIG_CPU_RK3288
15601951 	{
15611952 		.compatible = "rockchip,rk3288-power-controller",
15621953 		.data = (void *)&rk3288_pmu,
15631954 	},
1564
-#endif
1565
-#ifdef CONFIG_CPU_RK3328
15661955 	{
15671956 		.compatible = "rockchip,rk3328-power-controller",
15681957 		.data = (void *)&rk3328_pmu,
15691958 	},
1570
-#endif
1571
-#ifdef CONFIG_CPU_RK3366
15721959 	{
15731960 		.compatible = "rockchip,rk3366-power-controller",
15741961 		.data = (void *)&rk3366_pmu,
15751962 	},
1576
-#endif
1577
-#ifdef CONFIG_CPU_RK3368
15781963 	{
15791964 		.compatible = "rockchip,rk3368-power-controller",
15801965 		.data = (void *)&rk3368_pmu,
15811966 	},
1582
-#endif
1583
-#ifdef CONFIG_CPU_RK3399
15841967 	{
15851968 		.compatible = "rockchip,rk3399-power-controller",
15861969 		.data = (void *)&rk3399_pmu,
15871970 	},
1971
+#ifdef CONFIG_CPU_RK3528
1972
+	{
1973
+		.compatible = "rockchip,rk3528-power-controller",
1974
+		.data = (void *)&rk3528_pmu,
1975
+	},
15881976 #endif
1589
-#ifdef CONFIG_CPU_RK3568
1977
+	{
1978
+		.compatible = "rockchip,rk3562-power-controller",
1979
+		.data = (void *)&rk3562_pmu,
1980
+	},
15901981 	{
15911982 		.compatible = "rockchip,rk3568-power-controller",
15921983 		.data = (void *)&rk3568_pmu,
15931984 	},
1594
-#endif
1985
+	{
1986
+		.compatible = "rockchip,rk3588-power-controller",
1987
+		.data = (void *)&rk3588_pmu,
1988
+	},
1989
+	{
1990
+		.compatible = "rockchip,rv1126-power-controller",
1991
+		.data = (void *)&rv1126_pmu,
1992
+	},
15951993 	{ /* sentinel */ },
15961994 };
15971995 MODULE_DEVICE_TABLE(of, rockchip_pm_domain_dt_match);
....@@ -1624,4 +2022,3 @@
16242022 
16252023 MODULE_DESCRIPTION("ROCKCHIP PM Domain Driver");
16262024 MODULE_LICENSE("GPL");
1627
-MODULE_ALIAS("platform:rockchip-pm-domain");