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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
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1 | 2 | /* |
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2 | 3 | * R-Car SYSC Power management support |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2014 Magnus Damm |
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5 | 6 | * Copyright (C) 2015-2017 Glider bvba |
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6 | | - * |
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7 | | - * This file is subject to the terms and conditions of the GNU General Public |
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8 | | - * License. See the file "COPYING" in the main directory of this archive |
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9 | | - * for more details. |
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10 | 7 | */ |
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11 | 8 | |
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12 | 9 | #include <linux/clk/renesas.h> |
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.. | .. |
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66 | 63 | |
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67 | 64 | static void __iomem *rcar_sysc_base; |
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68 | 65 | static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ |
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| 66 | +static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val; |
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69 | 67 | |
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70 | 68 | static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on) |
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71 | 69 | { |
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.. | .. |
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108 | 106 | |
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109 | 107 | spin_lock_irqsave(&rcar_sysc_lock, flags); |
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110 | 108 | |
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| 109 | + /* |
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| 110 | + * Mask external power requests for CPU or 3DG domains |
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| 111 | + */ |
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| 112 | + if (rcar_sysc_extmask_val) { |
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| 113 | + iowrite32(rcar_sysc_extmask_val, |
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| 114 | + rcar_sysc_base + rcar_sysc_extmask_offs); |
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| 115 | + } |
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| 116 | + |
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| 117 | + /* |
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| 118 | + * The interrupt source needs to be enabled, but masked, to prevent the |
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| 119 | + * CPU from receiving it. |
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| 120 | + */ |
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| 121 | + iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask, |
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| 122 | + rcar_sysc_base + SYSCIMR); |
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| 123 | + iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask, |
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| 124 | + rcar_sysc_base + SYSCIER); |
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| 125 | + |
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111 | 126 | iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); |
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112 | 127 | |
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113 | 128 | /* Submit power shutoff or resume request until it was accepted */ |
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.. | .. |
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142 | 157 | iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); |
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143 | 158 | |
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144 | 159 | out: |
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| 160 | + if (rcar_sysc_extmask_val) |
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| 161 | + iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs); |
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| 162 | + |
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145 | 163 | spin_unlock_irqrestore(&rcar_sysc_lock, flags); |
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146 | 164 | |
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147 | 165 | pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off", |
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148 | 166 | sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret); |
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149 | 167 | return ret; |
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150 | | -} |
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151 | | - |
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152 | | -static int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch) |
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153 | | -{ |
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154 | | - return rcar_sysc_power(sysc_ch, false); |
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155 | | -} |
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156 | | - |
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157 | | -static int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch) |
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158 | | -{ |
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159 | | - return rcar_sysc_power(sysc_ch, true); |
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160 | 168 | } |
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161 | 169 | |
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162 | 170 | static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch) |
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.. | .. |
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174 | 182 | struct generic_pm_domain genpd; |
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175 | 183 | struct rcar_sysc_ch ch; |
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176 | 184 | unsigned int flags; |
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177 | | - char name[0]; |
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| 185 | + char name[]; |
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178 | 186 | }; |
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179 | 187 | |
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180 | 188 | static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d) |
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.. | .. |
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187 | 195 | struct rcar_sysc_pd *pd = to_rcar_pd(genpd); |
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188 | 196 | |
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189 | 197 | pr_debug("%s: %s\n", __func__, genpd->name); |
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190 | | - return rcar_sysc_power_down(&pd->ch); |
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| 198 | + return rcar_sysc_power(&pd->ch, false); |
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191 | 199 | } |
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192 | 200 | |
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193 | 201 | static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd) |
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.. | .. |
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195 | 203 | struct rcar_sysc_pd *pd = to_rcar_pd(genpd); |
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196 | 204 | |
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197 | 205 | pr_debug("%s: %s\n", __func__, genpd->name); |
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198 | | - return rcar_sysc_power_up(&pd->ch); |
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| 206 | + return rcar_sysc_power(&pd->ch, true); |
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199 | 207 | } |
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200 | 208 | |
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201 | 209 | static bool has_cpg_mstp; |
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.. | .. |
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204 | 212 | { |
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205 | 213 | struct generic_pm_domain *genpd = &pd->genpd; |
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206 | 214 | const char *name = pd->genpd.name; |
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207 | | - struct dev_power_governor *gov = &simple_qos_governor; |
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208 | 215 | int error; |
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209 | 216 | |
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210 | 217 | if (pd->flags & PD_CPU) { |
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.. | .. |
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255 | 262 | goto finalize; |
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256 | 263 | } |
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257 | 264 | |
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258 | | - rcar_sysc_power_up(&pd->ch); |
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| 265 | + rcar_sysc_power(&pd->ch, true); |
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259 | 266 | |
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260 | 267 | finalize: |
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261 | | - error = pm_genpd_init(genpd, gov, false); |
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| 268 | + error = pm_genpd_init(genpd, &simple_qos_governor, false); |
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262 | 269 | if (error) |
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263 | 270 | pr_err("Failed to init PM domain %s: %d\n", name, error); |
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264 | 271 | |
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.. | .. |
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266 | 273 | } |
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267 | 274 | |
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268 | 275 | static const struct of_device_id rcar_sysc_matches[] __initconst = { |
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| 276 | +#ifdef CONFIG_SYSC_R8A7742 |
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| 277 | + { .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info }, |
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| 278 | +#endif |
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269 | 279 | #ifdef CONFIG_SYSC_R8A7743 |
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270 | 280 | { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info }, |
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| 281 | + /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */ |
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| 282 | + { .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info }, |
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271 | 283 | #endif |
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272 | 284 | #ifdef CONFIG_SYSC_R8A7745 |
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273 | 285 | { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info }, |
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274 | 286 | #endif |
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275 | 287 | #ifdef CONFIG_SYSC_R8A77470 |
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276 | 288 | { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info }, |
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| 289 | +#endif |
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| 290 | +#ifdef CONFIG_SYSC_R8A774A1 |
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| 291 | + { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info }, |
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| 292 | +#endif |
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| 293 | +#ifdef CONFIG_SYSC_R8A774B1 |
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| 294 | + { .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info }, |
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| 295 | +#endif |
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| 296 | +#ifdef CONFIG_SYSC_R8A774C0 |
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| 297 | + { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info }, |
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| 298 | +#endif |
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| 299 | +#ifdef CONFIG_SYSC_R8A774E1 |
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| 300 | + { .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info }, |
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277 | 301 | #endif |
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278 | 302 | #ifdef CONFIG_SYSC_R8A7779 |
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279 | 303 | { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info }, |
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.. | .. |
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295 | 319 | #ifdef CONFIG_SYSC_R8A7795 |
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296 | 320 | { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info }, |
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297 | 321 | #endif |
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298 | | -#ifdef CONFIG_SYSC_R8A7796 |
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299 | | - { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info }, |
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| 322 | +#ifdef CONFIG_SYSC_R8A77960 |
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| 323 | + { .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info }, |
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| 324 | +#endif |
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| 325 | +#ifdef CONFIG_SYSC_R8A77961 |
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| 326 | + { .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info }, |
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300 | 327 | #endif |
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301 | 328 | #ifdef CONFIG_SYSC_R8A77965 |
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302 | 329 | { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info }, |
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.. | .. |
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329 | 356 | const struct of_device_id *match; |
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330 | 357 | struct rcar_pm_domains *domains; |
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331 | 358 | struct device_node *np; |
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332 | | - u32 syscier, syscimr; |
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333 | 359 | void __iomem *base; |
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334 | 360 | unsigned int i; |
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335 | 361 | int error; |
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.. | .. |
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343 | 369 | if (info->init) { |
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344 | 370 | error = info->init(); |
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345 | 371 | if (error) |
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346 | | - return error; |
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| 372 | + goto out_put; |
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347 | 373 | } |
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348 | 374 | |
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349 | 375 | has_cpg_mstp = of_find_compatible_node(NULL, NULL, |
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.. | .. |
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358 | 384 | |
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359 | 385 | rcar_sysc_base = base; |
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360 | 386 | |
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| 387 | + /* Optional External Request Mask Register */ |
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| 388 | + rcar_sysc_extmask_offs = info->extmask_offs; |
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| 389 | + rcar_sysc_extmask_val = info->extmask_val; |
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| 390 | + |
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361 | 391 | domains = kzalloc(sizeof(*domains), GFP_KERNEL); |
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362 | 392 | if (!domains) { |
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363 | 393 | error = -ENOMEM; |
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.. | .. |
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368 | 398 | domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains); |
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369 | 399 | rcar_sysc_onecell_data = &domains->onecell_data; |
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370 | 400 | |
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371 | | - for (i = 0, syscier = 0; i < info->num_areas; i++) |
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372 | | - syscier |= BIT(info->areas[i].isr_bit); |
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373 | | - |
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374 | | - /* |
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375 | | - * Mask all interrupt sources to prevent the CPU from receiving them. |
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376 | | - * Make sure not to clear reserved bits that were set before. |
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377 | | - */ |
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378 | | - syscimr = ioread32(base + SYSCIMR); |
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379 | | - syscimr |= syscier; |
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380 | | - pr_debug("%pOF: syscimr = 0x%08x\n", np, syscimr); |
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381 | | - iowrite32(syscimr, base + SYSCIMR); |
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382 | | - |
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383 | | - /* |
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384 | | - * SYSC needs all interrupt sources enabled to control power. |
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385 | | - */ |
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386 | | - pr_debug("%pOF: syscier = 0x%08x\n", np, syscier); |
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387 | | - iowrite32(syscier, base + SYSCIER); |
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388 | | - |
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389 | | - /* |
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390 | | - * First, create all PM domains |
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391 | | - */ |
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392 | 401 | for (i = 0; i < info->num_areas; i++) { |
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393 | 402 | const struct rcar_sysc_area *area = &info->areas[i]; |
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394 | 403 | struct rcar_sysc_pd *pd; |
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.. | .. |
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416 | 425 | goto out_put; |
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417 | 426 | |
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418 | 427 | domains->domains[area->isr_bit] = &pd->genpd; |
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419 | | - } |
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420 | 428 | |
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421 | | - /* |
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422 | | - * Second, link all PM domains to their parents |
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423 | | - */ |
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424 | | - for (i = 0; i < info->num_areas; i++) { |
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425 | | - const struct rcar_sysc_area *area = &info->areas[i]; |
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426 | | - |
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427 | | - if (!area->name || area->parent < 0) |
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| 429 | + if (area->parent < 0) |
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428 | 430 | continue; |
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429 | 431 | |
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430 | 432 | error = pm_genpd_add_subdomain(domains->domains[area->parent], |
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431 | | - domains->domains[area->isr_bit]); |
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432 | | - if (error) |
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| 433 | + &pd->genpd); |
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| 434 | + if (error) { |
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433 | 435 | pr_warn("Failed to add PM subdomain %s to parent %u\n", |
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434 | 436 | area->name, area->parent); |
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| 437 | + goto out_put; |
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| 438 | + } |
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435 | 439 | } |
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436 | 440 | |
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437 | 441 | error = of_genpd_add_provider_onecell(np, &domains->onecell_data); |
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.. | .. |
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473 | 477 | if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx) |
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474 | 478 | continue; |
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475 | 479 | |
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476 | | - return on ? rcar_sysc_power_up(&pd->ch) |
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477 | | - : rcar_sysc_power_down(&pd->ch); |
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| 480 | + return rcar_sysc_power(&pd->ch, on); |
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478 | 481 | } |
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479 | 482 | |
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480 | 483 | return -ENOENT; |
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