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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/soc/mediatek/mtk-pmic-wrap.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2014 MediaTek Inc.
34  * Author: Flora Fu, MediaTek
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
135  */
146 #include <linux/clk.h>
157 #include <linux/interrupt.h>
....@@ -76,6 +68,13 @@
7668 #define PWRAP_SLV_CAP_SECURITY	BIT(2)
7769 #define HAS_CAP(_c, _x)	(((_c) & (_x)) == (_x))
7870 
71
+/* Group of bits used for shown pwrap capability */
72
+#define PWRAP_CAP_BRIDGE	BIT(0)
73
+#define PWRAP_CAP_RESET		BIT(1)
74
+#define PWRAP_CAP_DCM		BIT(2)
75
+#define PWRAP_CAP_INT1_EN	BIT(3)
76
+#define PWRAP_CAP_WDT_SRC1	BIT(4)
77
+
7978 /* defines for slave device wrapper registers */
8079 enum dew_regs {
8180 	PWRAP_DEW_BASE,
....@@ -91,6 +90,49 @@
9190 	PWRAP_DEW_CIPHER_MODE,
9291 	PWRAP_DEW_CIPHER_SWRST,
9392 
93
+	/* MT6323 only regs */
94
+	PWRAP_DEW_CIPHER_EN,
95
+	PWRAP_DEW_RDDMY_NO,
96
+
97
+	/* MT6358 only regs */
98
+	PWRAP_SMT_CON1,
99
+	PWRAP_DRV_CON1,
100
+	PWRAP_FILTER_CON0,
101
+	PWRAP_GPIO_PULLEN0_CLR,
102
+	PWRAP_RG_SPI_CON0,
103
+	PWRAP_RG_SPI_RECORD0,
104
+	PWRAP_RG_SPI_CON2,
105
+	PWRAP_RG_SPI_CON3,
106
+	PWRAP_RG_SPI_CON4,
107
+	PWRAP_RG_SPI_CON5,
108
+	PWRAP_RG_SPI_CON6,
109
+	PWRAP_RG_SPI_CON7,
110
+	PWRAP_RG_SPI_CON8,
111
+	PWRAP_RG_SPI_CON13,
112
+	PWRAP_SPISLV_KEY,
113
+
114
+	/* MT6359 only regs */
115
+	PWRAP_DEW_CRC_SWRST,
116
+	PWRAP_DEW_RG_EN_RECORD,
117
+	PWRAP_DEW_RECORD_CMD0,
118
+	PWRAP_DEW_RECORD_CMD1,
119
+	PWRAP_DEW_RECORD_CMD2,
120
+	PWRAP_DEW_RECORD_CMD3,
121
+	PWRAP_DEW_RECORD_CMD4,
122
+	PWRAP_DEW_RECORD_CMD5,
123
+	PWRAP_DEW_RECORD_WDATA0,
124
+	PWRAP_DEW_RECORD_WDATA1,
125
+	PWRAP_DEW_RECORD_WDATA2,
126
+	PWRAP_DEW_RECORD_WDATA3,
127
+	PWRAP_DEW_RECORD_WDATA4,
128
+	PWRAP_DEW_RECORD_WDATA5,
129
+	PWRAP_DEW_RG_ADDR_TARGET,
130
+	PWRAP_DEW_RG_ADDR_MASK,
131
+	PWRAP_DEW_RG_WDATA_TARGET,
132
+	PWRAP_DEW_RG_WDATA_MASK,
133
+	PWRAP_DEW_RG_SPI_RECORD_CLR,
134
+	PWRAP_DEW_RG_CMD_ALERT_CLR,
135
+
94136 	/* MT6397 only regs */
95137 	PWRAP_DEW_EVENT_OUT_EN,
96138 	PWRAP_DEW_EVENT_SRC_EN,
....@@ -100,10 +142,6 @@
100142 	PWRAP_DEW_EVENT_TEST,
101143 	PWRAP_DEW_CIPHER_LOAD,
102144 	PWRAP_DEW_CIPHER_START,
103
-
104
-	/* MT6323 only regs */
105
-	PWRAP_DEW_CIPHER_EN,
106
-	PWRAP_DEW_RDDMY_NO,
107145 };
108146 
109147 static const u32 mt6323_regs[] = {
....@@ -121,6 +159,100 @@
121159 	[PWRAP_DEW_CIPHER_MODE] =	0x01a0,
122160 	[PWRAP_DEW_CIPHER_SWRST] =	0x01a2,
123161 	[PWRAP_DEW_RDDMY_NO] =		0x01a4,
162
+};
163
+
164
+static const u32 mt6351_regs[] = {
165
+	[PWRAP_DEW_DIO_EN] =		0x02F2,
166
+	[PWRAP_DEW_READ_TEST] =		0x02F4,
167
+	[PWRAP_DEW_WRITE_TEST] =	0x02F6,
168
+	[PWRAP_DEW_CRC_EN] =		0x02FA,
169
+	[PWRAP_DEW_CRC_VAL] =		0x02FC,
170
+	[PWRAP_DEW_CIPHER_KEY_SEL] =	0x0300,
171
+	[PWRAP_DEW_CIPHER_IV_SEL] =	0x0302,
172
+	[PWRAP_DEW_CIPHER_EN] =		0x0304,
173
+	[PWRAP_DEW_CIPHER_RDY] =	0x0306,
174
+	[PWRAP_DEW_CIPHER_MODE] =	0x0308,
175
+	[PWRAP_DEW_CIPHER_SWRST] =	0x030A,
176
+	[PWRAP_DEW_RDDMY_NO] =		0x030C,
177
+};
178
+
179
+static const u32 mt6357_regs[] = {
180
+	[PWRAP_DEW_DIO_EN] =            0x040A,
181
+	[PWRAP_DEW_READ_TEST] =         0x040C,
182
+	[PWRAP_DEW_WRITE_TEST] =        0x040E,
183
+	[PWRAP_DEW_CRC_EN] =            0x0412,
184
+	[PWRAP_DEW_CRC_VAL] =           0x0414,
185
+	[PWRAP_DEW_CIPHER_KEY_SEL] =    0x0418,
186
+	[PWRAP_DEW_CIPHER_IV_SEL] =     0x041A,
187
+	[PWRAP_DEW_CIPHER_EN] =         0x041C,
188
+	[PWRAP_DEW_CIPHER_RDY] =        0x041E,
189
+	[PWRAP_DEW_CIPHER_MODE] =       0x0420,
190
+	[PWRAP_DEW_CIPHER_SWRST] =      0x0422,
191
+	[PWRAP_DEW_RDDMY_NO] =          0x0424,
192
+};
193
+
194
+static const u32 mt6358_regs[] = {
195
+	[PWRAP_SMT_CON1] =		0x0030,
196
+	[PWRAP_DRV_CON1] =		0x0038,
197
+	[PWRAP_FILTER_CON0] =		0x0040,
198
+	[PWRAP_GPIO_PULLEN0_CLR] =	0x0098,
199
+	[PWRAP_RG_SPI_CON0] =		0x0408,
200
+	[PWRAP_RG_SPI_RECORD0] =	0x040a,
201
+	[PWRAP_DEW_DIO_EN] =		0x040c,
202
+	[PWRAP_DEW_READ_TEST]	=	0x040e,
203
+	[PWRAP_DEW_WRITE_TEST]	=	0x0410,
204
+	[PWRAP_DEW_CRC_EN] =		0x0414,
205
+	[PWRAP_DEW_CIPHER_KEY_SEL] =	0x041a,
206
+	[PWRAP_DEW_CIPHER_IV_SEL] =	0x041c,
207
+	[PWRAP_DEW_CIPHER_EN]	=	0x041e,
208
+	[PWRAP_DEW_CIPHER_RDY] =	0x0420,
209
+	[PWRAP_DEW_CIPHER_MODE] =	0x0422,
210
+	[PWRAP_DEW_CIPHER_SWRST] =	0x0424,
211
+	[PWRAP_RG_SPI_CON2] =		0x0432,
212
+	[PWRAP_RG_SPI_CON3] =		0x0434,
213
+	[PWRAP_RG_SPI_CON4] =		0x0436,
214
+	[PWRAP_RG_SPI_CON5] =		0x0438,
215
+	[PWRAP_RG_SPI_CON6] =		0x043a,
216
+	[PWRAP_RG_SPI_CON7] =		0x043c,
217
+	[PWRAP_RG_SPI_CON8] =		0x043e,
218
+	[PWRAP_RG_SPI_CON13] =		0x0448,
219
+	[PWRAP_SPISLV_KEY] =		0x044a,
220
+};
221
+
222
+static const u32 mt6359_regs[] = {
223
+	[PWRAP_DEW_RG_EN_RECORD] =	0x040a,
224
+	[PWRAP_DEW_DIO_EN] =		0x040c,
225
+	[PWRAP_DEW_READ_TEST] =		0x040e,
226
+	[PWRAP_DEW_WRITE_TEST] =	0x0410,
227
+	[PWRAP_DEW_CRC_SWRST] =		0x0412,
228
+	[PWRAP_DEW_CRC_EN] =		0x0414,
229
+	[PWRAP_DEW_CRC_VAL] =		0x0416,
230
+	[PWRAP_DEW_CIPHER_KEY_SEL] =	0x0418,
231
+	[PWRAP_DEW_CIPHER_IV_SEL] =	0x041a,
232
+	[PWRAP_DEW_CIPHER_EN] =		0x041c,
233
+	[PWRAP_DEW_CIPHER_RDY] =	0x041e,
234
+	[PWRAP_DEW_CIPHER_MODE] =	0x0420,
235
+	[PWRAP_DEW_CIPHER_SWRST] =	0x0422,
236
+	[PWRAP_DEW_RDDMY_NO] =		0x0424,
237
+	[PWRAP_DEW_RECORD_CMD0] =	0x0428,
238
+	[PWRAP_DEW_RECORD_CMD1] =	0x042a,
239
+	[PWRAP_DEW_RECORD_CMD2] =	0x042c,
240
+	[PWRAP_DEW_RECORD_CMD3] =	0x042e,
241
+	[PWRAP_DEW_RECORD_CMD4] =	0x0430,
242
+	[PWRAP_DEW_RECORD_CMD5] =	0x0432,
243
+	[PWRAP_DEW_RECORD_WDATA0] =	0x0434,
244
+	[PWRAP_DEW_RECORD_WDATA1] =	0x0436,
245
+	[PWRAP_DEW_RECORD_WDATA2] =	0x0438,
246
+	[PWRAP_DEW_RECORD_WDATA3] =	0x043a,
247
+	[PWRAP_DEW_RECORD_WDATA4] =	0x043c,
248
+	[PWRAP_DEW_RECORD_WDATA5] =	0x043e,
249
+	[PWRAP_DEW_RG_ADDR_TARGET] =	0x0440,
250
+	[PWRAP_DEW_RG_ADDR_MASK] =	0x0442,
251
+	[PWRAP_DEW_RG_WDATA_TARGET] =	0x0444,
252
+	[PWRAP_DEW_RG_WDATA_MASK] =	0x0446,
253
+	[PWRAP_DEW_RG_SPI_RECORD_CLR] =	0x0448,
254
+	[PWRAP_DEW_RG_CMD_ALERT_CLR] =	0x0448,
255
+	[PWRAP_SPISLV_KEY] =		0x044a,
124256 };
125257 
126258 static const u32 mt6397_regs[] = {
....@@ -144,21 +276,6 @@
144276 	[PWRAP_DEW_CIPHER_RDY] =	0xbc20,
145277 	[PWRAP_DEW_CIPHER_MODE] =	0xbc22,
146278 	[PWRAP_DEW_CIPHER_SWRST] =	0xbc24,
147
-};
148
-
149
-static const u32 mt6351_regs[] = {
150
-	[PWRAP_DEW_DIO_EN] =		0x02F2,
151
-	[PWRAP_DEW_READ_TEST] =		0x02F4,
152
-	[PWRAP_DEW_WRITE_TEST] =	0x02F6,
153
-	[PWRAP_DEW_CRC_EN] =		0x02FA,
154
-	[PWRAP_DEW_CRC_VAL] =		0x02FC,
155
-	[PWRAP_DEW_CIPHER_KEY_SEL] =	0x0300,
156
-	[PWRAP_DEW_CIPHER_IV_SEL] =	0x0302,
157
-	[PWRAP_DEW_CIPHER_EN] =		0x0304,
158
-	[PWRAP_DEW_CIPHER_RDY] =	0x0306,
159
-	[PWRAP_DEW_CIPHER_MODE] =	0x0308,
160
-	[PWRAP_DEW_CIPHER_SWRST] =	0x030A,
161
-	[PWRAP_DEW_RDDMY_NO] =		0x030C,
162279 };
163280 
164281 enum pwrap_regs {
....@@ -221,6 +338,8 @@
221338 	PWRAP_CIPHER_SWRST,
222339 	PWRAP_DCM_EN,
223340 	PWRAP_DCM_DBC_PRD,
341
+	PWRAP_EINT_STA0_ADR,
342
+	PWRAP_EINT_STA1_ADR,
224343 
225344 	/* MT2701 only regs */
226345 	PWRAP_ADC_CMD_ADDR,
....@@ -230,8 +349,6 @@
230349 	PWRAP_ADC_RDATA_ADDR2,
231350 
232351 	/* MT7622 only regs */
233
-	PWRAP_EINT_STA0_ADR,
234
-	PWRAP_EINT_STA1_ADR,
235352 	PWRAP_STA,
236353 	PWRAP_CLR,
237354 	PWRAP_DVFS_ADR8,
....@@ -293,6 +410,31 @@
293410 	PWRAP_DVFS_WDATA7,
294411 	PWRAP_SPMINF_STA,
295412 	PWRAP_CIPHER_EN,
413
+
414
+	/* MT8183 only regs */
415
+	PWRAP_SI_SAMPLE_CTRL,
416
+	PWRAP_CSLEXT_WRITE,
417
+	PWRAP_CSLEXT_READ,
418
+	PWRAP_EXT_CK_WRITE,
419
+	PWRAP_STAUPD_CTRL,
420
+	PWRAP_WACS_P2P_EN,
421
+	PWRAP_INIT_DONE_P2P,
422
+	PWRAP_WACS_MD32_EN,
423
+	PWRAP_INIT_DONE_MD32,
424
+	PWRAP_INT1_EN,
425
+	PWRAP_INT1_FLG,
426
+	PWRAP_INT1_CLR,
427
+	PWRAP_WDT_SRC_EN_1,
428
+	PWRAP_INT_GPS_AUXADC_CMD_ADDR,
429
+	PWRAP_INT_GPS_AUXADC_CMD,
430
+	PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
431
+	PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
432
+	PWRAP_GPSINF_0_STA,
433
+	PWRAP_GPSINF_1_STA,
434
+
435
+	/* MT8516 only regs */
436
+	PWRAP_OP_TYPE,
437
+	PWRAP_MSB_FIRST,
296438 };
297439 
298440 static int mt2701_regs[] = {
....@@ -379,6 +521,77 @@
379521 	[PWRAP_ADC_RDY_ADDR] =		0x14c,
380522 	[PWRAP_ADC_RDATA_ADDR1] =	0x150,
381523 	[PWRAP_ADC_RDATA_ADDR2] =	0x154,
524
+};
525
+
526
+static int mt6765_regs[] = {
527
+	[PWRAP_MUX_SEL] =		0x0,
528
+	[PWRAP_WRAP_EN] =		0x4,
529
+	[PWRAP_DIO_EN] =		0x8,
530
+	[PWRAP_RDDMY] =			0x20,
531
+	[PWRAP_CSHEXT_WRITE] =		0x24,
532
+	[PWRAP_CSHEXT_READ] =		0x28,
533
+	[PWRAP_CSLEXT_START] =		0x2C,
534
+	[PWRAP_CSLEXT_END] =		0x30,
535
+	[PWRAP_STAUPD_PRD] =		0x3C,
536
+	[PWRAP_HARB_HPRIO] =		0x68,
537
+	[PWRAP_HIPRIO_ARB_EN] =		0x6C,
538
+	[PWRAP_MAN_EN] =		0x7C,
539
+	[PWRAP_MAN_CMD] =		0x80,
540
+	[PWRAP_WACS0_EN] =		0x8C,
541
+	[PWRAP_WACS1_EN] =		0x94,
542
+	[PWRAP_WACS2_EN] =		0x9C,
543
+	[PWRAP_INIT_DONE2] =		0xA0,
544
+	[PWRAP_WACS2_CMD] =		0xC20,
545
+	[PWRAP_WACS2_RDATA] =		0xC24,
546
+	[PWRAP_WACS2_VLDCLR] =		0xC28,
547
+	[PWRAP_INT_EN] =		0xB4,
548
+	[PWRAP_INT_FLG_RAW] =		0xB8,
549
+	[PWRAP_INT_FLG] =		0xBC,
550
+	[PWRAP_INT_CLR] =		0xC0,
551
+	[PWRAP_TIMER_EN] =		0xE8,
552
+	[PWRAP_WDT_UNIT] =		0xF0,
553
+	[PWRAP_WDT_SRC_EN] =		0xF4,
554
+	[PWRAP_DCM_EN] =		0x1DC,
555
+	[PWRAP_DCM_DBC_PRD] =		0x1E0,
556
+};
557
+
558
+static int mt6779_regs[] = {
559
+	[PWRAP_MUX_SEL] =		0x0,
560
+	[PWRAP_WRAP_EN] =		0x4,
561
+	[PWRAP_DIO_EN] =		0x8,
562
+	[PWRAP_RDDMY] =			0x20,
563
+	[PWRAP_CSHEXT_WRITE] =		0x24,
564
+	[PWRAP_CSHEXT_READ] =		0x28,
565
+	[PWRAP_CSLEXT_WRITE] =		0x2C,
566
+	[PWRAP_CSLEXT_READ] =		0x30,
567
+	[PWRAP_EXT_CK_WRITE] =		0x34,
568
+	[PWRAP_STAUPD_CTRL] =		0x3C,
569
+	[PWRAP_STAUPD_GRPEN] =		0x40,
570
+	[PWRAP_EINT_STA0_ADR] =		0x44,
571
+	[PWRAP_HARB_HPRIO] =		0x68,
572
+	[PWRAP_HIPRIO_ARB_EN] =		0x6C,
573
+	[PWRAP_MAN_EN] =		0x7C,
574
+	[PWRAP_MAN_CMD] =		0x80,
575
+	[PWRAP_WACS0_EN] =		0x8C,
576
+	[PWRAP_INIT_DONE0] =		0x90,
577
+	[PWRAP_WACS1_EN] =		0x94,
578
+	[PWRAP_WACS2_EN] =		0x9C,
579
+	[PWRAP_INIT_DONE1] =		0x98,
580
+	[PWRAP_INIT_DONE2] =		0xA0,
581
+	[PWRAP_INT_EN] =		0xBC,
582
+	[PWRAP_INT_FLG_RAW] =		0xC0,
583
+	[PWRAP_INT_FLG] =		0xC4,
584
+	[PWRAP_INT_CLR] =		0xC8,
585
+	[PWRAP_INT1_EN] =		0xCC,
586
+	[PWRAP_INT1_FLG] =		0xD4,
587
+	[PWRAP_INT1_CLR] =		0xD8,
588
+	[PWRAP_TIMER_EN] =		0xF0,
589
+	[PWRAP_WDT_UNIT] =		0xF8,
590
+	[PWRAP_WDT_SRC_EN] =		0xFC,
591
+	[PWRAP_WDT_SRC_EN_1] =		0x100,
592
+	[PWRAP_WACS2_CMD] =		0xC20,
593
+	[PWRAP_WACS2_RDATA] =		0xC24,
594
+	[PWRAP_WACS2_VLDCLR] =		0xC28,
382595 };
383596 
384597 static int mt6797_regs[] = {
....@@ -526,6 +739,79 @@
526739 	[PWRAP_SPI2_CTRL] =		0x244,
527740 };
528741 
742
+static int mt8135_regs[] = {
743
+	[PWRAP_MUX_SEL] =		0x0,
744
+	[PWRAP_WRAP_EN] =		0x4,
745
+	[PWRAP_DIO_EN] =		0x8,
746
+	[PWRAP_SIDLY] =			0xc,
747
+	[PWRAP_CSHEXT] =		0x10,
748
+	[PWRAP_CSHEXT_WRITE] =		0x14,
749
+	[PWRAP_CSHEXT_READ] =		0x18,
750
+	[PWRAP_CSLEXT_START] =		0x1c,
751
+	[PWRAP_CSLEXT_END] =		0x20,
752
+	[PWRAP_STAUPD_PRD] =		0x24,
753
+	[PWRAP_STAUPD_GRPEN] =		0x28,
754
+	[PWRAP_STAUPD_MAN_TRIG] =	0x2c,
755
+	[PWRAP_STAUPD_STA] =		0x30,
756
+	[PWRAP_EVENT_IN_EN] =		0x34,
757
+	[PWRAP_EVENT_DST_EN] =		0x38,
758
+	[PWRAP_WRAP_STA] =		0x3c,
759
+	[PWRAP_RRARB_INIT] =		0x40,
760
+	[PWRAP_RRARB_EN] =		0x44,
761
+	[PWRAP_RRARB_STA0] =		0x48,
762
+	[PWRAP_RRARB_STA1] =		0x4c,
763
+	[PWRAP_HARB_INIT] =		0x50,
764
+	[PWRAP_HARB_HPRIO] =		0x54,
765
+	[PWRAP_HIPRIO_ARB_EN] =		0x58,
766
+	[PWRAP_HARB_STA0] =		0x5c,
767
+	[PWRAP_HARB_STA1] =		0x60,
768
+	[PWRAP_MAN_EN] =		0x64,
769
+	[PWRAP_MAN_CMD] =		0x68,
770
+	[PWRAP_MAN_RDATA] =		0x6c,
771
+	[PWRAP_MAN_VLDCLR] =		0x70,
772
+	[PWRAP_WACS0_EN] =		0x74,
773
+	[PWRAP_INIT_DONE0] =		0x78,
774
+	[PWRAP_WACS0_CMD] =		0x7c,
775
+	[PWRAP_WACS0_RDATA] =		0x80,
776
+	[PWRAP_WACS0_VLDCLR] =		0x84,
777
+	[PWRAP_WACS1_EN] =		0x88,
778
+	[PWRAP_INIT_DONE1] =		0x8c,
779
+	[PWRAP_WACS1_CMD] =		0x90,
780
+	[PWRAP_WACS1_RDATA] =		0x94,
781
+	[PWRAP_WACS1_VLDCLR] =		0x98,
782
+	[PWRAP_WACS2_EN] =		0x9c,
783
+	[PWRAP_INIT_DONE2] =		0xa0,
784
+	[PWRAP_WACS2_CMD] =		0xa4,
785
+	[PWRAP_WACS2_RDATA] =		0xa8,
786
+	[PWRAP_WACS2_VLDCLR] =		0xac,
787
+	[PWRAP_INT_EN] =		0xb0,
788
+	[PWRAP_INT_FLG_RAW] =		0xb4,
789
+	[PWRAP_INT_FLG] =		0xb8,
790
+	[PWRAP_INT_CLR] =		0xbc,
791
+	[PWRAP_SIG_ADR] =		0xc0,
792
+	[PWRAP_SIG_MODE] =		0xc4,
793
+	[PWRAP_SIG_VALUE] =		0xc8,
794
+	[PWRAP_SIG_ERRVAL] =		0xcc,
795
+	[PWRAP_CRC_EN] =		0xd0,
796
+	[PWRAP_EVENT_STA] =		0xd4,
797
+	[PWRAP_EVENT_STACLR] =		0xd8,
798
+	[PWRAP_TIMER_EN] =		0xdc,
799
+	[PWRAP_TIMER_STA] =		0xe0,
800
+	[PWRAP_WDT_UNIT] =		0xe4,
801
+	[PWRAP_WDT_SRC_EN] =		0xe8,
802
+	[PWRAP_WDT_FLG] =		0xec,
803
+	[PWRAP_DEBUG_INT_SEL] =		0xf0,
804
+	[PWRAP_CIPHER_KEY_SEL] =	0x134,
805
+	[PWRAP_CIPHER_IV_SEL] =		0x138,
806
+	[PWRAP_CIPHER_LOAD] =		0x13c,
807
+	[PWRAP_CIPHER_START] =		0x140,
808
+	[PWRAP_CIPHER_RDY] =		0x144,
809
+	[PWRAP_CIPHER_MODE] =		0x148,
810
+	[PWRAP_CIPHER_SWRST] =		0x14c,
811
+	[PWRAP_DCM_EN] =		0x15c,
812
+	[PWRAP_DCM_DBC_PRD] =		0x160,
813
+};
814
+
529815 static int mt8173_regs[] = {
530816 	[PWRAP_MUX_SEL] =		0x0,
531817 	[PWRAP_WRAP_EN] =		0x4,
....@@ -608,92 +894,162 @@
608894 	[PWRAP_DCM_DBC_PRD] =		0x148,
609895 };
610896 
611
-static int mt8135_regs[] = {
897
+static int mt8183_regs[] = {
898
+	[PWRAP_MUX_SEL] =			0x0,
899
+	[PWRAP_WRAP_EN] =			0x4,
900
+	[PWRAP_DIO_EN] =			0x8,
901
+	[PWRAP_SI_SAMPLE_CTRL] =		0xC,
902
+	[PWRAP_RDDMY] =				0x14,
903
+	[PWRAP_CSHEXT_WRITE] =			0x18,
904
+	[PWRAP_CSHEXT_READ] =			0x1C,
905
+	[PWRAP_CSLEXT_WRITE] =			0x20,
906
+	[PWRAP_CSLEXT_READ] =			0x24,
907
+	[PWRAP_EXT_CK_WRITE] =			0x28,
908
+	[PWRAP_STAUPD_CTRL] =			0x30,
909
+	[PWRAP_STAUPD_GRPEN] =			0x34,
910
+	[PWRAP_EINT_STA0_ADR] =			0x38,
911
+	[PWRAP_HARB_HPRIO] =			0x5C,
912
+	[PWRAP_HIPRIO_ARB_EN] =			0x60,
913
+	[PWRAP_MAN_EN] =			0x70,
914
+	[PWRAP_MAN_CMD] =			0x74,
915
+	[PWRAP_WACS0_EN] =			0x80,
916
+	[PWRAP_INIT_DONE0] =			0x84,
917
+	[PWRAP_WACS1_EN] =			0x88,
918
+	[PWRAP_INIT_DONE1] =			0x8C,
919
+	[PWRAP_WACS2_EN] =			0x90,
920
+	[PWRAP_INIT_DONE2] =			0x94,
921
+	[PWRAP_WACS_P2P_EN] =			0xA0,
922
+	[PWRAP_INIT_DONE_P2P] =			0xA4,
923
+	[PWRAP_WACS_MD32_EN] =			0xA8,
924
+	[PWRAP_INIT_DONE_MD32] =		0xAC,
925
+	[PWRAP_INT_EN] =			0xB0,
926
+	[PWRAP_INT_FLG] =			0xB8,
927
+	[PWRAP_INT_CLR] =			0xBC,
928
+	[PWRAP_INT1_EN] =			0xC0,
929
+	[PWRAP_INT1_FLG] =			0xC8,
930
+	[PWRAP_INT1_CLR] =			0xCC,
931
+	[PWRAP_SIG_ADR] =			0xD0,
932
+	[PWRAP_CRC_EN] =			0xE0,
933
+	[PWRAP_TIMER_EN] =			0xE4,
934
+	[PWRAP_WDT_UNIT] =			0xEC,
935
+	[PWRAP_WDT_SRC_EN] =			0xF0,
936
+	[PWRAP_WDT_SRC_EN_1] =			0xF4,
937
+	[PWRAP_INT_GPS_AUXADC_CMD_ADDR] =	0x1DC,
938
+	[PWRAP_INT_GPS_AUXADC_CMD] =		0x1E0,
939
+	[PWRAP_INT_GPS_AUXADC_RDATA_ADDR] =	0x1E4,
940
+	[PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] =	0x1E8,
941
+	[PWRAP_GPSINF_0_STA] =			0x1EC,
942
+	[PWRAP_GPSINF_1_STA] =			0x1F0,
943
+	[PWRAP_WACS2_CMD] =			0xC20,
944
+	[PWRAP_WACS2_RDATA] =			0xC24,
945
+	[PWRAP_WACS2_VLDCLR] =			0xC28,
946
+};
947
+
948
+static int mt8516_regs[] = {
612949 	[PWRAP_MUX_SEL] =		0x0,
613950 	[PWRAP_WRAP_EN] =		0x4,
614951 	[PWRAP_DIO_EN] =		0x8,
615952 	[PWRAP_SIDLY] =			0xc,
616
-	[PWRAP_CSHEXT] =		0x10,
617
-	[PWRAP_CSHEXT_WRITE] =		0x14,
618
-	[PWRAP_CSHEXT_READ] =		0x18,
619
-	[PWRAP_CSLEXT_START] =		0x1c,
620
-	[PWRAP_CSLEXT_END] =		0x20,
621
-	[PWRAP_STAUPD_PRD] =		0x24,
622
-	[PWRAP_STAUPD_GRPEN] =		0x28,
623
-	[PWRAP_STAUPD_MAN_TRIG] =	0x2c,
624
-	[PWRAP_STAUPD_STA] =		0x30,
625
-	[PWRAP_EVENT_IN_EN] =		0x34,
626
-	[PWRAP_EVENT_DST_EN] =		0x38,
627
-	[PWRAP_WRAP_STA] =		0x3c,
628
-	[PWRAP_RRARB_INIT] =		0x40,
629
-	[PWRAP_RRARB_EN] =		0x44,
630
-	[PWRAP_RRARB_STA0] =		0x48,
631
-	[PWRAP_RRARB_STA1] =		0x4c,
632
-	[PWRAP_HARB_INIT] =		0x50,
633
-	[PWRAP_HARB_HPRIO] =		0x54,
634
-	[PWRAP_HIPRIO_ARB_EN] =		0x58,
635
-	[PWRAP_HARB_STA0] =		0x5c,
636
-	[PWRAP_HARB_STA1] =		0x60,
637
-	[PWRAP_MAN_EN] =		0x64,
638
-	[PWRAP_MAN_CMD] =		0x68,
639
-	[PWRAP_MAN_RDATA] =		0x6c,
640
-	[PWRAP_MAN_VLDCLR] =		0x70,
641
-	[PWRAP_WACS0_EN] =		0x74,
642
-	[PWRAP_INIT_DONE0] =		0x78,
643
-	[PWRAP_WACS0_CMD] =		0x7c,
644
-	[PWRAP_WACS0_RDATA] =		0x80,
645
-	[PWRAP_WACS0_VLDCLR] =		0x84,
646
-	[PWRAP_WACS1_EN] =		0x88,
647
-	[PWRAP_INIT_DONE1] =		0x8c,
648
-	[PWRAP_WACS1_CMD] =		0x90,
649
-	[PWRAP_WACS1_RDATA] =		0x94,
650
-	[PWRAP_WACS1_VLDCLR] =		0x98,
651
-	[PWRAP_WACS2_EN] =		0x9c,
652
-	[PWRAP_INIT_DONE2] =		0xa0,
653
-	[PWRAP_WACS2_CMD] =		0xa4,
654
-	[PWRAP_WACS2_RDATA] =		0xa8,
655
-	[PWRAP_WACS2_VLDCLR] =		0xac,
656
-	[PWRAP_INT_EN] =		0xb0,
657
-	[PWRAP_INT_FLG_RAW] =		0xb4,
658
-	[PWRAP_INT_FLG] =		0xb8,
659
-	[PWRAP_INT_CLR] =		0xbc,
660
-	[PWRAP_SIG_ADR] =		0xc0,
661
-	[PWRAP_SIG_MODE] =		0xc4,
662
-	[PWRAP_SIG_VALUE] =		0xc8,
663
-	[PWRAP_SIG_ERRVAL] =		0xcc,
664
-	[PWRAP_CRC_EN] =		0xd0,
665
-	[PWRAP_EVENT_STA] =		0xd4,
666
-	[PWRAP_EVENT_STACLR] =		0xd8,
667
-	[PWRAP_TIMER_EN] =		0xdc,
668
-	[PWRAP_TIMER_STA] =		0xe0,
669
-	[PWRAP_WDT_UNIT] =		0xe4,
670
-	[PWRAP_WDT_SRC_EN] =		0xe8,
671
-	[PWRAP_WDT_FLG] =		0xec,
672
-	[PWRAP_DEBUG_INT_SEL] =		0xf0,
673
-	[PWRAP_CIPHER_KEY_SEL] =	0x134,
674
-	[PWRAP_CIPHER_IV_SEL] =		0x138,
675
-	[PWRAP_CIPHER_LOAD] =		0x13c,
676
-	[PWRAP_CIPHER_START] =		0x140,
677
-	[PWRAP_CIPHER_RDY] =		0x144,
678
-	[PWRAP_CIPHER_MODE] =		0x148,
679
-	[PWRAP_CIPHER_SWRST] =		0x14c,
680
-	[PWRAP_DCM_EN] =		0x15c,
681
-	[PWRAP_DCM_DBC_PRD] =		0x160,
953
+	[PWRAP_RDDMY] =			0x10,
954
+	[PWRAP_SI_CK_CON] =		0x14,
955
+	[PWRAP_CSHEXT_WRITE] =		0x18,
956
+	[PWRAP_CSHEXT_READ] =		0x1c,
957
+	[PWRAP_CSLEXT_START] =		0x20,
958
+	[PWRAP_CSLEXT_END] =		0x24,
959
+	[PWRAP_STAUPD_PRD] =		0x28,
960
+	[PWRAP_STAUPD_GRPEN] =		0x2c,
961
+	[PWRAP_STAUPD_MAN_TRIG] =	0x40,
962
+	[PWRAP_STAUPD_STA] =		0x44,
963
+	[PWRAP_WRAP_STA] =		0x48,
964
+	[PWRAP_HARB_INIT] =		0x4c,
965
+	[PWRAP_HARB_HPRIO] =		0x50,
966
+	[PWRAP_HIPRIO_ARB_EN] =		0x54,
967
+	[PWRAP_HARB_STA0] =		0x58,
968
+	[PWRAP_HARB_STA1] =		0x5c,
969
+	[PWRAP_MAN_EN] =		0x60,
970
+	[PWRAP_MAN_CMD] =		0x64,
971
+	[PWRAP_MAN_RDATA] =		0x68,
972
+	[PWRAP_MAN_VLDCLR] =		0x6c,
973
+	[PWRAP_WACS0_EN] =		0x70,
974
+	[PWRAP_INIT_DONE0] =		0x74,
975
+	[PWRAP_WACS0_CMD] =		0x78,
976
+	[PWRAP_WACS0_RDATA] =		0x7c,
977
+	[PWRAP_WACS0_VLDCLR] =		0x80,
978
+	[PWRAP_WACS1_EN] =		0x84,
979
+	[PWRAP_INIT_DONE1] =		0x88,
980
+	[PWRAP_WACS1_CMD] =		0x8c,
981
+	[PWRAP_WACS1_RDATA] =		0x90,
982
+	[PWRAP_WACS1_VLDCLR] =		0x94,
983
+	[PWRAP_WACS2_EN] =		0x98,
984
+	[PWRAP_INIT_DONE2] =		0x9c,
985
+	[PWRAP_WACS2_CMD] =		0xa0,
986
+	[PWRAP_WACS2_RDATA] =		0xa4,
987
+	[PWRAP_WACS2_VLDCLR] =		0xa8,
988
+	[PWRAP_INT_EN] =		0xac,
989
+	[PWRAP_INT_FLG_RAW] =		0xb0,
990
+	[PWRAP_INT_FLG] =		0xb4,
991
+	[PWRAP_INT_CLR] =		0xb8,
992
+	[PWRAP_SIG_ADR] =		0xbc,
993
+	[PWRAP_SIG_MODE] =		0xc0,
994
+	[PWRAP_SIG_VALUE] =		0xc4,
995
+	[PWRAP_SIG_ERRVAL] =		0xc8,
996
+	[PWRAP_CRC_EN] =		0xcc,
997
+	[PWRAP_TIMER_EN] =		0xd0,
998
+	[PWRAP_TIMER_STA] =		0xd4,
999
+	[PWRAP_WDT_UNIT] =		0xd8,
1000
+	[PWRAP_WDT_SRC_EN] =		0xdc,
1001
+	[PWRAP_WDT_FLG] =		0xe0,
1002
+	[PWRAP_DEBUG_INT_SEL] =		0xe4,
1003
+	[PWRAP_DVFS_ADR0] =		0xe8,
1004
+	[PWRAP_DVFS_WDATA0] =		0xec,
1005
+	[PWRAP_DVFS_ADR1] =		0xf0,
1006
+	[PWRAP_DVFS_WDATA1] =		0xf4,
1007
+	[PWRAP_DVFS_ADR2] =		0xf8,
1008
+	[PWRAP_DVFS_WDATA2] =		0xfc,
1009
+	[PWRAP_DVFS_ADR3] =		0x100,
1010
+	[PWRAP_DVFS_WDATA3] =		0x104,
1011
+	[PWRAP_DVFS_ADR4] =		0x108,
1012
+	[PWRAP_DVFS_WDATA4] =		0x10c,
1013
+	[PWRAP_DVFS_ADR5] =		0x110,
1014
+	[PWRAP_DVFS_WDATA5] =		0x114,
1015
+	[PWRAP_DVFS_ADR6] =		0x118,
1016
+	[PWRAP_DVFS_WDATA6] =		0x11c,
1017
+	[PWRAP_DVFS_ADR7] =		0x120,
1018
+	[PWRAP_DVFS_WDATA7] =		0x124,
1019
+	[PWRAP_SPMINF_STA] =		0x128,
1020
+	[PWRAP_CIPHER_KEY_SEL] =	0x12c,
1021
+	[PWRAP_CIPHER_IV_SEL] =		0x130,
1022
+	[PWRAP_CIPHER_EN] =		0x134,
1023
+	[PWRAP_CIPHER_RDY] =		0x138,
1024
+	[PWRAP_CIPHER_MODE] =		0x13c,
1025
+	[PWRAP_CIPHER_SWRST] =		0x140,
1026
+	[PWRAP_DCM_EN] =		0x144,
1027
+	[PWRAP_DCM_DBC_PRD] =		0x148,
1028
+	[PWRAP_SW_RST] =		0x168,
1029
+	[PWRAP_OP_TYPE] =		0x16c,
1030
+	[PWRAP_MSB_FIRST] =		0x170,
6821031 };
6831032 
6841033 enum pmic_type {
6851034 	PMIC_MT6323,
6861035 	PMIC_MT6351,
1036
+	PMIC_MT6357,
1037
+	PMIC_MT6358,
1038
+	PMIC_MT6359,
6871039 	PMIC_MT6380,
6881040 	PMIC_MT6397,
6891041 };
6901042 
6911043 enum pwrap_type {
6921044 	PWRAP_MT2701,
1045
+	PWRAP_MT6765,
1046
+	PWRAP_MT6779,
6931047 	PWRAP_MT6797,
6941048 	PWRAP_MT7622,
6951049 	PWRAP_MT8135,
6961050 	PWRAP_MT8173,
1051
+	PWRAP_MT8183,
1052
+	PWRAP_MT8516,
6971053 };
6981054 
6991055 struct pmic_wrapper;
....@@ -731,9 +1087,11 @@
7311087 	enum pwrap_type type;
7321088 	u32 arb_en_all;
7331089 	u32 int_en_all;
1090
+	u32 int1_en_all;
7341091 	u32 spi_w;
7351092 	u32 wdt_src;
736
-	unsigned int has_bridge:1;
1093
+	/* Flags indicating the capability for the target pwrap */
1094
+	u32 caps;
7371095 	int (*init_reg_clock)(struct pmic_wrapper *wrp);
7381096 	int (*init_soc_specific)(struct pmic_wrapper *wrp);
7391097 };
....@@ -1096,7 +1454,7 @@
10961454 	ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
10971455 			 &rdata);
10981456 	if (ret)
1099
-		return 0;
1457
+		return false;
11001458 
11011459 	return rdata == 1;
11021460 }
....@@ -1117,12 +1475,17 @@
11171475 		pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
11181476 		break;
11191477 	case PWRAP_MT2701:
1478
+	case PWRAP_MT6765:
1479
+	case PWRAP_MT6779:
11201480 	case PWRAP_MT6797:
11211481 	case PWRAP_MT8173:
1482
+	case PWRAP_MT8516:
11221483 		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
11231484 		break;
11241485 	case PWRAP_MT7622:
11251486 		pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1487
+		break;
1488
+	case PWRAP_MT8183:
11261489 		break;
11271490 	}
11281491 
....@@ -1141,6 +1504,7 @@
11411504 		break;
11421505 	case PMIC_MT6323:
11431506 	case PMIC_MT6351:
1507
+	case PMIC_MT6357:
11441508 		pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
11451509 			    0x1);
11461510 		break;
....@@ -1276,11 +1640,29 @@
12761640 	return 0;
12771641 }
12781642 
1643
+static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
1644
+{
1645
+	pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
1646
+
1647
+	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1648
+	pwrap_writel(wrp, 1, PWRAP_CRC_EN);
1649
+	pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
1650
+	pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
1651
+
1652
+	pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
1653
+	pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
1654
+	pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
1655
+	pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
1656
+
1657
+	return 0;
1658
+}
1659
+
12791660 static int pwrap_init(struct pmic_wrapper *wrp)
12801661 {
12811662 	int ret;
12821663 
1283
-	reset_control_reset(wrp->rstc);
1664
+	if (wrp->rstc)
1665
+		reset_control_reset(wrp->rstc);
12841666 	if (wrp->rstc_bridge)
12851667 		reset_control_reset(wrp->rstc_bridge);
12861668 
....@@ -1348,7 +1730,7 @@
13481730 	pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
13491731 	pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
13501732 
1351
-	if (wrp->master->has_bridge) {
1733
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
13521734 		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
13531735 		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
13541736 	}
....@@ -1362,10 +1744,14 @@
13621744 	struct pmic_wrapper *wrp = dev_id;
13631745 
13641746 	rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1365
-
13661747 	dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1367
-
13681748 	pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1749
+
1750
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1751
+		rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
1752
+		dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
1753
+		pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
1754
+	}
13691755 
13701756 	return IRQ_HANDLED;
13711757 }
....@@ -1398,6 +1784,42 @@
13981784 	.pwrap_write = pwrap_write16,
13991785 };
14001786 
1787
+static const struct pwrap_slv_type pmic_mt6351 = {
1788
+	.dew_regs = mt6351_regs,
1789
+	.type = PMIC_MT6351,
1790
+	.regmap = &pwrap_regmap_config16,
1791
+	.caps = 0,
1792
+	.pwrap_read = pwrap_read16,
1793
+	.pwrap_write = pwrap_write16,
1794
+};
1795
+
1796
+static const struct pwrap_slv_type pmic_mt6357 = {
1797
+	.dew_regs = mt6357_regs,
1798
+	.type = PMIC_MT6357,
1799
+	.regmap = &pwrap_regmap_config16,
1800
+	.caps = 0,
1801
+	.pwrap_read = pwrap_read16,
1802
+	.pwrap_write = pwrap_write16,
1803
+};
1804
+
1805
+static const struct pwrap_slv_type pmic_mt6358 = {
1806
+	.dew_regs = mt6358_regs,
1807
+	.type = PMIC_MT6358,
1808
+	.regmap = &pwrap_regmap_config16,
1809
+	.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
1810
+	.pwrap_read = pwrap_read16,
1811
+	.pwrap_write = pwrap_write16,
1812
+};
1813
+
1814
+static const struct pwrap_slv_type pmic_mt6359 = {
1815
+	.dew_regs = mt6359_regs,
1816
+	.type = PMIC_MT6359,
1817
+	.regmap = &pwrap_regmap_config16,
1818
+	.caps = PWRAP_SLV_CAP_DUALIO,
1819
+	.pwrap_read = pwrap_read16,
1820
+	.pwrap_write = pwrap_write16,
1821
+};
1822
+
14011823 static const struct pwrap_slv_type pmic_mt6380 = {
14021824 	.dew_regs = NULL,
14031825 	.type = PMIC_MT6380,
....@@ -1417,19 +1839,22 @@
14171839 	.pwrap_write = pwrap_write16,
14181840 };
14191841 
1420
-static const struct pwrap_slv_type pmic_mt6351 = {
1421
-	.dew_regs = mt6351_regs,
1422
-	.type = PMIC_MT6351,
1423
-	.regmap = &pwrap_regmap_config16,
1424
-	.caps = 0,
1425
-	.pwrap_read = pwrap_read16,
1426
-	.pwrap_write = pwrap_write16,
1427
-};
1428
-
14291842 static const struct of_device_id of_slave_match_tbl[] = {
14301843 	{
14311844 		.compatible = "mediatek,mt6323",
14321845 		.data = &pmic_mt6323,
1846
+	}, {
1847
+		.compatible = "mediatek,mt6351",
1848
+		.data = &pmic_mt6351,
1849
+	}, {
1850
+		.compatible = "mediatek,mt6357",
1851
+		.data = &pmic_mt6357,
1852
+	}, {
1853
+		.compatible = "mediatek,mt6358",
1854
+		.data = &pmic_mt6358,
1855
+	}, {
1856
+		.compatible = "mediatek,mt6359",
1857
+		.data = &pmic_mt6359,
14331858 	}, {
14341859 		/* The MT6380 PMIC only implements a regulator, so we bind it
14351860 		 * directly instead of using a MFD.
....@@ -1439,9 +1864,6 @@
14391864 	}, {
14401865 		.compatible = "mediatek,mt6397",
14411866 		.data = &pmic_mt6397,
1442
-	}, {
1443
-		.compatible = "mediatek,mt6351",
1444
-		.data = &pmic_mt6351,
14451867 	}, {
14461868 		/* sentinel */
14471869 	}
....@@ -1453,11 +1875,37 @@
14531875 	.type = PWRAP_MT2701,
14541876 	.arb_en_all = 0x3f,
14551877 	.int_en_all = ~(u32)(BIT(31) | BIT(2)),
1878
+	.int1_en_all = 0,
14561879 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
14571880 	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1458
-	.has_bridge = 0,
1881
+	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
14591882 	.init_reg_clock = pwrap_mt2701_init_reg_clock,
14601883 	.init_soc_specific = pwrap_mt2701_init_soc_specific,
1884
+};
1885
+
1886
+static const struct pmic_wrapper_type pwrap_mt6765 = {
1887
+	.regs = mt6765_regs,
1888
+	.type = PWRAP_MT6765,
1889
+	.arb_en_all = 0x3fd35,
1890
+	.int_en_all = 0xffffffff,
1891
+	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1892
+	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1893
+	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1894
+	.init_reg_clock = pwrap_common_init_reg_clock,
1895
+	.init_soc_specific = NULL,
1896
+};
1897
+
1898
+static const struct pmic_wrapper_type pwrap_mt6779 = {
1899
+	.regs = mt6779_regs,
1900
+	.type = PWRAP_MT6779,
1901
+	.arb_en_all = 0xfbb7f,
1902
+	.int_en_all = 0xfffffffe,
1903
+	.int1_en_all = 0,
1904
+	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1905
+	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1906
+	.caps = 0,
1907
+	.init_reg_clock = pwrap_common_init_reg_clock,
1908
+	.init_soc_specific = NULL,
14611909 };
14621910 
14631911 static const struct pmic_wrapper_type pwrap_mt6797 = {
....@@ -1465,9 +1913,10 @@
14651913 	.type = PWRAP_MT6797,
14661914 	.arb_en_all = 0x01fff,
14671915 	.int_en_all = 0xffffffc6,
1916
+	.int1_en_all = 0,
14681917 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
14691918 	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1470
-	.has_bridge = 0,
1919
+	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
14711920 	.init_reg_clock = pwrap_common_init_reg_clock,
14721921 	.init_soc_specific = NULL,
14731922 };
....@@ -1477,9 +1926,10 @@
14771926 	.type = PWRAP_MT7622,
14781927 	.arb_en_all = 0xff,
14791928 	.int_en_all = ~(u32)BIT(31),
1929
+	.int1_en_all = 0,
14801930 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
14811931 	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1482
-	.has_bridge = 0,
1932
+	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
14831933 	.init_reg_clock = pwrap_common_init_reg_clock,
14841934 	.init_soc_specific = pwrap_mt7622_init_soc_specific,
14851935 };
....@@ -1489,9 +1939,10 @@
14891939 	.type = PWRAP_MT8135,
14901940 	.arb_en_all = 0x1ff,
14911941 	.int_en_all = ~(u32)(BIT(31) | BIT(1)),
1942
+	.int1_en_all = 0,
14921943 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
14931944 	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1494
-	.has_bridge = 1,
1945
+	.caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
14951946 	.init_reg_clock = pwrap_common_init_reg_clock,
14961947 	.init_soc_specific = pwrap_mt8135_init_soc_specific,
14971948 };
....@@ -1501,17 +1952,49 @@
15011952 	.type = PWRAP_MT8173,
15021953 	.arb_en_all = 0x3f,
15031954 	.int_en_all = ~(u32)(BIT(31) | BIT(1)),
1955
+	.int1_en_all = 0,
15041956 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
15051957 	.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
1506
-	.has_bridge = 0,
1958
+	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
15071959 	.init_reg_clock = pwrap_common_init_reg_clock,
15081960 	.init_soc_specific = pwrap_mt8173_init_soc_specific,
1961
+};
1962
+
1963
+static const struct pmic_wrapper_type pwrap_mt8183 = {
1964
+	.regs = mt8183_regs,
1965
+	.type = PWRAP_MT8183,
1966
+	.arb_en_all = 0x3fa75,
1967
+	.int_en_all = 0xffffffff,
1968
+	.int1_en_all = 0xeef7ffff,
1969
+	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1970
+	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1971
+	.caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
1972
+	.init_reg_clock = pwrap_common_init_reg_clock,
1973
+	.init_soc_specific = pwrap_mt8183_init_soc_specific,
1974
+};
1975
+
1976
+static struct pmic_wrapper_type pwrap_mt8516 = {
1977
+	.regs = mt8516_regs,
1978
+	.type = PWRAP_MT8516,
1979
+	.arb_en_all = 0xff,
1980
+	.int_en_all = ~(u32)(BIT(31) | BIT(2)),
1981
+	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1982
+	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1983
+	.caps = PWRAP_CAP_DCM,
1984
+	.init_reg_clock = pwrap_mt2701_init_reg_clock,
1985
+	.init_soc_specific = NULL,
15091986 };
15101987 
15111988 static const struct of_device_id of_pwrap_match_tbl[] = {
15121989 	{
15131990 		.compatible = "mediatek,mt2701-pwrap",
15141991 		.data = &pwrap_mt2701,
1992
+	}, {
1993
+		.compatible = "mediatek,mt6765-pwrap",
1994
+		.data = &pwrap_mt6765,
1995
+	}, {
1996
+		.compatible = "mediatek,mt6779-pwrap",
1997
+		.data = &pwrap_mt6779,
15151998 	}, {
15161999 		.compatible = "mediatek,mt6797-pwrap",
15172000 		.data = &pwrap_mt6797,
....@@ -1524,6 +2007,12 @@
15242007 	}, {
15252008 		.compatible = "mediatek,mt8173-pwrap",
15262009 		.data = &pwrap_mt8173,
2010
+	}, {
2011
+		.compatible = "mediatek,mt8183-pwrap",
2012
+		.data = &pwrap_mt8183,
2013
+	}, {
2014
+		.compatible = "mediatek,mt8516-pwrap",
2015
+		.data = &pwrap_mt8516,
15272016 	}, {
15282017 		/* sentinel */
15292018 	}
....@@ -1561,14 +2050,16 @@
15612050 	if (IS_ERR(wrp->base))
15622051 		return PTR_ERR(wrp->base);
15632052 
1564
-	wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
1565
-	if (IS_ERR(wrp->rstc)) {
1566
-		ret = PTR_ERR(wrp->rstc);
1567
-		dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
1568
-		return ret;
2053
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2054
+		wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2055
+		if (IS_ERR(wrp->rstc)) {
2056
+			ret = PTR_ERR(wrp->rstc);
2057
+			dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2058
+			return ret;
2059
+		}
15692060 	}
15702061 
1571
-	if (wrp->master->has_bridge) {
2062
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
15722063 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
15732064 				"pwrap-bridge");
15742065 		wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
....@@ -1608,8 +2099,10 @@
16082099 		goto err_out1;
16092100 
16102101 	/* Enable internal dynamic clock */
1611
-	pwrap_writel(wrp, 1, PWRAP_DCM_EN);
1612
-	pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2102
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2103
+		pwrap_writel(wrp, 1, PWRAP_DCM_EN);
2104
+		pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2105
+	}
16132106 
16142107 	/*
16152108 	 * The PMIC could already be initialized by the bootloader.
....@@ -1636,8 +2129,17 @@
16362129 	 * so STAUPD of WDT_SRC which should be turned off
16372130 	 */
16382131 	pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2132
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2133
+		pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2134
+
16392135 	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
16402136 	pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2137
+	/*
2138
+	 * We add INT1 interrupt to handle starvation and request exception
2139
+	 * If we support it, we should enable it here.
2140
+	 */
2141
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2142
+		pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
16412143 
16422144 	irq = platform_get_irq(pdev, 0);
16432145 	ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,