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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/soc/fsl/qe/qe_ic.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * arch/powerpc/sysdev/qe_lib/qe_ic.c
34  *
....@@ -7,11 +8,6 @@
78  * Based on code from Shlomi Gridish <gridish@freescale.com>
89  *
910  * QUICC ENGINE Interrupt Controller
10
- *
11
- * This program is free software; you can redistribute  it and/or modify it
12
- * under  the terms of  the GNU General  Public License as published by the
13
- * Free Software Foundation;  either version 2 of the  License, or (at your
14
- * option) any later version.
1511  */
1612 
1713 #include <linux/of_irq.h>
....@@ -19,6 +15,7 @@
1915 #include <linux/kernel.h>
2016 #include <linux/init.h>
2117 #include <linux/errno.h>
18
+#include <linux/irq.h>
2219 #include <linux/reboot.h>
2320 #include <linux/slab.h>
2421 #include <linux/stddef.h>
....@@ -28,9 +25,57 @@
2825 #include <linux/spinlock.h>
2926 #include <asm/irq.h>
3027 #include <asm/io.h>
31
-#include <soc/fsl/qe/qe_ic.h>
28
+#include <soc/fsl/qe/qe.h>
3229 
33
-#include "qe_ic.h"
30
+#define NR_QE_IC_INTS		64
31
+
32
+/* QE IC registers offset */
33
+#define QEIC_CICR		0x00
34
+#define QEIC_CIVEC		0x04
35
+#define QEIC_CIPXCC		0x10
36
+#define QEIC_CIPYCC		0x14
37
+#define QEIC_CIPWCC		0x18
38
+#define QEIC_CIPZCC		0x1c
39
+#define QEIC_CIMR		0x20
40
+#define QEIC_CRIMR		0x24
41
+#define QEIC_CIPRTA		0x30
42
+#define QEIC_CIPRTB		0x34
43
+#define QEIC_CHIVEC		0x60
44
+
45
+struct qe_ic {
46
+	/* Control registers offset */
47
+	__be32 __iomem *regs;
48
+
49
+	/* The remapper for this QEIC */
50
+	struct irq_domain *irqhost;
51
+
52
+	/* The "linux" controller struct */
53
+	struct irq_chip hc_irq;
54
+
55
+	/* VIRQ numbers of QE high/low irqs */
56
+	unsigned int virq_high;
57
+	unsigned int virq_low;
58
+};
59
+
60
+/*
61
+ * QE interrupt controller internal structure
62
+ */
63
+struct qe_ic_info {
64
+	/* Location of this source at the QIMR register */
65
+	u32	mask;
66
+
67
+	/* Mask register offset */
68
+	u32	mask_reg;
69
+
70
+	/*
71
+	 * For grouped interrupts sources - the interrupt code as
72
+	 * appears at the group priority register
73
+	 */
74
+	u8	pri_code;
75
+
76
+	/* Group priority register offset */
77
+	u32	pri_reg;
78
+};
3479 
3580 static DEFINE_RAW_SPINLOCK(qe_ic_lock);
3681 
....@@ -175,15 +220,15 @@
175220 		},
176221 };
177222 
178
-static inline u32 qe_ic_read(volatile __be32  __iomem * base, unsigned int reg)
223
+static inline u32 qe_ic_read(__be32  __iomem *base, unsigned int reg)
179224 {
180
-	return in_be32(base + (reg >> 2));
225
+	return qe_ioread32be(base + (reg >> 2));
181226 }
182227 
183
-static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg,
228
+static inline void qe_ic_write(__be32  __iomem *base, unsigned int reg,
184229 			       u32 value)
185230 {
186
-	out_be32(base + (reg >> 2), value);
231
+	qe_iowrite32be(value, base + (reg >> 2));
187232 }
188233 
189234 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
....@@ -285,8 +330,8 @@
285330 	.xlate = irq_domain_xlate_onetwocell,
286331 };
287332 
288
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
289
-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
333
+/* Return an interrupt vector or 0 if no interrupt is pending. */
334
+static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
290335 {
291336 	int irq;
292337 
....@@ -296,13 +341,13 @@
296341 	irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
297342 
298343 	if (irq == 0)
299
-		return NO_IRQ;
344
+		return 0;
300345 
301346 	return irq_linear_revmap(qe_ic->irqhost, irq);
302347 }
303348 
304
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
305
-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
349
+/* Return an interrupt vector or 0 if no interrupt is pending. */
350
+static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
306351 {
307352 	int irq;
308353 
....@@ -312,18 +357,60 @@
312357 	irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
313358 
314359 	if (irq == 0)
315
-		return NO_IRQ;
360
+		return 0;
316361 
317362 	return irq_linear_revmap(qe_ic->irqhost, irq);
318363 }
319364 
320
-void __init qe_ic_init(struct device_node *node, unsigned int flags,
321
-		       void (*low_handler)(struct irq_desc *desc),
322
-		       void (*high_handler)(struct irq_desc *desc))
365
+static void qe_ic_cascade_low(struct irq_desc *desc)
323366 {
367
+	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
368
+	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
369
+	struct irq_chip *chip = irq_desc_get_chip(desc);
370
+
371
+	if (cascade_irq != 0)
372
+		generic_handle_irq(cascade_irq);
373
+
374
+	if (chip->irq_eoi)
375
+		chip->irq_eoi(&desc->irq_data);
376
+}
377
+
378
+static void qe_ic_cascade_high(struct irq_desc *desc)
379
+{
380
+	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
381
+	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
382
+	struct irq_chip *chip = irq_desc_get_chip(desc);
383
+
384
+	if (cascade_irq != 0)
385
+		generic_handle_irq(cascade_irq);
386
+
387
+	if (chip->irq_eoi)
388
+		chip->irq_eoi(&desc->irq_data);
389
+}
390
+
391
+static void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
392
+{
393
+	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
394
+	unsigned int cascade_irq;
395
+	struct irq_chip *chip = irq_desc_get_chip(desc);
396
+
397
+	cascade_irq = qe_ic_get_high_irq(qe_ic);
398
+	if (cascade_irq == 0)
399
+		cascade_irq = qe_ic_get_low_irq(qe_ic);
400
+
401
+	if (cascade_irq != 0)
402
+		generic_handle_irq(cascade_irq);
403
+
404
+	chip->irq_eoi(&desc->irq_data);
405
+}
406
+
407
+static void __init qe_ic_init(struct device_node *node)
408
+{
409
+	void (*low_handler)(struct irq_desc *desc);
410
+	void (*high_handler)(struct irq_desc *desc);
324411 	struct qe_ic *qe_ic;
325412 	struct resource res;
326
-	u32 temp = 0, ret, high_active = 0;
413
+	u32 ret;
327414 
328415 	ret = of_address_to_resource(node, 0, &res);
329416 	if (ret)
....@@ -347,166 +434,42 @@
347434 	qe_ic->virq_high = irq_of_parse_and_map(node, 0);
348435 	qe_ic->virq_low = irq_of_parse_and_map(node, 1);
349436 
350
-	if (qe_ic->virq_low == NO_IRQ) {
437
+	if (!qe_ic->virq_low) {
351438 		printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
352439 		kfree(qe_ic);
353440 		return;
354441 	}
355
-
356
-	/* default priority scheme is grouped. If spread mode is    */
357
-	/* required, configure cicr accordingly.                    */
358
-	if (flags & QE_IC_SPREADMODE_GRP_W)
359
-		temp |= CICR_GWCC;
360
-	if (flags & QE_IC_SPREADMODE_GRP_X)
361
-		temp |= CICR_GXCC;
362
-	if (flags & QE_IC_SPREADMODE_GRP_Y)
363
-		temp |= CICR_GYCC;
364
-	if (flags & QE_IC_SPREADMODE_GRP_Z)
365
-		temp |= CICR_GZCC;
366
-	if (flags & QE_IC_SPREADMODE_GRP_RISCA)
367
-		temp |= CICR_GRTA;
368
-	if (flags & QE_IC_SPREADMODE_GRP_RISCB)
369
-		temp |= CICR_GRTB;
370
-
371
-	/* choose destination signal for highest priority interrupt */
372
-	if (flags & QE_IC_HIGH_SIGNAL) {
373
-		temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
374
-		high_active = 1;
442
+	if (qe_ic->virq_high != qe_ic->virq_low) {
443
+		low_handler = qe_ic_cascade_low;
444
+		high_handler = qe_ic_cascade_high;
445
+	} else {
446
+		low_handler = qe_ic_cascade_muxed_mpic;
447
+		high_handler = NULL;
375448 	}
376449 
377
-	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
450
+	qe_ic_write(qe_ic->regs, QEIC_CICR, 0);
378451 
379452 	irq_set_handler_data(qe_ic->virq_low, qe_ic);
380453 	irq_set_chained_handler(qe_ic->virq_low, low_handler);
381454 
382
-	if (qe_ic->virq_high != NO_IRQ &&
383
-			qe_ic->virq_high != qe_ic->virq_low) {
455
+	if (qe_ic->virq_high && qe_ic->virq_high != qe_ic->virq_low) {
384456 		irq_set_handler_data(qe_ic->virq_high, qe_ic);
385457 		irq_set_chained_handler(qe_ic->virq_high, high_handler);
386458 	}
387459 }
388460 
389
-void qe_ic_set_highest_priority(unsigned int virq, int high)
461
+static int __init qe_ic_of_init(void)
390462 {
391
-	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
392
-	unsigned int src = virq_to_hw(virq);
393
-	u32 temp = 0;
463
+	struct device_node *np;
394464 
395
-	temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
396
-
397
-	temp &= ~CICR_HP_MASK;
398
-	temp |= src << CICR_HP_SHIFT;
399
-
400
-	temp &= ~CICR_HPIT_MASK;
401
-	temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
402
-
403
-	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
404
-}
405
-
406
-/* Set Priority level within its group, from 1 to 8 */
407
-int qe_ic_set_priority(unsigned int virq, unsigned int priority)
408
-{
409
-	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
410
-	unsigned int src = virq_to_hw(virq);
411
-	u32 temp;
412
-
413
-	if (priority > 8 || priority == 0)
414
-		return -EINVAL;
415
-	if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
416
-		      "%s: Invalid hw irq number for QEIC\n", __func__))
417
-		return -EINVAL;
418
-	if (qe_ic_info[src].pri_reg == 0)
419
-		return -EINVAL;
420
-
421
-	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
422
-
423
-	if (priority < 4) {
424
-		temp &= ~(0x7 << (32 - priority * 3));
425
-		temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
426
-	} else {
427
-		temp &= ~(0x7 << (24 - priority * 3));
428
-		temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
465
+	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
466
+	if (!np) {
467
+		np = of_find_node_by_type(NULL, "qeic");
468
+		if (!np)
469
+			return -ENODEV;
429470 	}
430
-
431
-	qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
432
-
471
+	qe_ic_init(np);
472
+	of_node_put(np);
433473 	return 0;
434474 }
435
-
436
-/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
437
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
438
-{
439
-	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
440
-	unsigned int src = virq_to_hw(virq);
441
-	u32 temp, control_reg = QEIC_CICNR, shift = 0;
442
-
443
-	if (priority > 2 || priority == 0)
444
-		return -EINVAL;
445
-	if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
446
-		      "%s: Invalid hw irq number for QEIC\n", __func__))
447
-		return -EINVAL;
448
-
449
-	switch (qe_ic_info[src].pri_reg) {
450
-	case QEIC_CIPZCC:
451
-		shift = CICNR_ZCC1T_SHIFT;
452
-		break;
453
-	case QEIC_CIPWCC:
454
-		shift = CICNR_WCC1T_SHIFT;
455
-		break;
456
-	case QEIC_CIPYCC:
457
-		shift = CICNR_YCC1T_SHIFT;
458
-		break;
459
-	case QEIC_CIPXCC:
460
-		shift = CICNR_XCC1T_SHIFT;
461
-		break;
462
-	case QEIC_CIPRTA:
463
-		shift = CRICR_RTA1T_SHIFT;
464
-		control_reg = QEIC_CRICR;
465
-		break;
466
-	case QEIC_CIPRTB:
467
-		shift = CRICR_RTB1T_SHIFT;
468
-		control_reg = QEIC_CRICR;
469
-		break;
470
-	default:
471
-		return -EINVAL;
472
-	}
473
-
474
-	shift += (2 - priority) * 2;
475
-	temp = qe_ic_read(qe_ic->regs, control_reg);
476
-	temp &= ~(SIGNAL_MASK << shift);
477
-	temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
478
-	qe_ic_write(qe_ic->regs, control_reg, temp);
479
-
480
-	return 0;
481
-}
482
-
483
-static struct bus_type qe_ic_subsys = {
484
-	.name = "qe_ic",
485
-	.dev_name = "qe_ic",
486
-};
487
-
488
-static struct device device_qe_ic = {
489
-	.id = 0,
490
-	.bus = &qe_ic_subsys,
491
-};
492
-
493
-static int __init init_qe_ic_sysfs(void)
494
-{
495
-	int rc;
496
-
497
-	printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
498
-
499
-	rc = subsys_system_register(&qe_ic_subsys, NULL);
500
-	if (rc) {
501
-		printk(KERN_ERR "Failed registering qe_ic sys class\n");
502
-		return -ENODEV;
503
-	}
504
-	rc = device_register(&device_qe_ic);
505
-	if (rc) {
506
-		printk(KERN_ERR "Failed registering qe_ic sys device\n");
507
-		return -ENODEV;
508
-	}
509
-	return 0;
510
-}
511
-
512
-subsys_initcall(init_qe_ic_sysfs);
475
+subsys_initcall(qe_ic_of_init);