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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/scsi/qla1280.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /******************************************************************************
23 *                  QLOGIC LINUX SOFTWARE
34 *
....@@ -5,16 +6,6 @@
56 * Copyright (C) 2000 Qlogic Corporation (www.qlogic.com)
67 * Copyright (C) 2001-2004 Jes Sorensen, Wild Open Source Inc.
78 * Copyright (C) 2003-2004 Christoph Hellwig
8
-*
9
-* This program is free software; you can redistribute it and/or modify it
10
-* under the terms of the GNU General Public License as published by the
11
-* Free Software Foundation; either version 2, or (at your option) any
12
-* later version.
13
-*
14
-* This program is distributed in the hope that it will be useful, but
15
-* WITHOUT ANY WARRANTY; without even the implied warranty of
16
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17
-* General Public License for more details.
189 *
1910 ******************************************************************************/
2011 #define QLA1280_VERSION      "3.27.1"
....@@ -366,10 +357,6 @@
366357 #include <scsi/scsi_host.h>
367358 #include <scsi/scsi_tcq.h>
368359 
369
-#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
370
-#include <asm/sn/io.h>
371
-#endif
372
-
373360 
374361 /*
375362  * Compile time Options:
....@@ -383,26 +370,11 @@
383370 
384371 #include "qla1280.h"
385372 
386
-#ifndef BITS_PER_LONG
387
-#error "BITS_PER_LONG not defined!"
388
-#endif
389
-#if (BITS_PER_LONG == 64) || defined CONFIG_HIGHMEM
373
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
390374 #define QLA_64BIT_PTR	1
391375 #endif
392376 
393
-#ifdef QLA_64BIT_PTR
394
-#define pci_dma_hi32(a)			((a >> 16) >> 16)
395
-#else
396
-#define pci_dma_hi32(a)			0
397
-#endif
398
-#define pci_dma_lo32(a)			(a & 0xffffffff)
399
-
400377 #define NVRAM_DELAY()			udelay(500)	/* 2 microseconds */
401
-
402
-#if defined(__ia64__) && !defined(ia64_platform_is)
403
-#define ia64_platform_is(foo)		(!strcmp(x, platform_name))
404
-#endif
405
-
406378 
407379 #define IS_ISP1040(ha) (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP1020)
408380 #define IS_ISP1x40(ha) (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP1020 || \
....@@ -554,7 +526,7 @@
554526 };
555527 MODULE_DEVICE_TABLE(pci, qla1280_pci_tbl);
556528 
557
-DEFINE_MUTEX(qla1280_firmware_mutex);
529
+static DEFINE_MUTEX(qla1280_firmware_mutex);
558530 
559531 struct qla_fw {
560532 	char *fwname;
....@@ -563,7 +535,7 @@
563535 
564536 #define QL_NUM_FW_IMAGES 3
565537 
566
-struct qla_fw qla1280_fw_tbl[QL_NUM_FW_IMAGES] = {
538
+static struct qla_fw qla1280_fw_tbl[QL_NUM_FW_IMAGES] = {
567539 	{"qlogic/1040.bin",  NULL},	/* image 0 */
568540 	{"qlogic/1280.bin",  NULL},	/* image 1 */
569541 	{"qlogic/12160.bin", NULL},	/* image 2 */
....@@ -1269,7 +1241,7 @@
12691241 {
12701242 	struct srb *sp;
12711243 	struct list_head *done_q;
1272
-	int bus, target, lun;
1244
+	int bus, target;
12731245 	struct scsi_cmnd *cmd;
12741246 
12751247 	ENTER("qla1280_done");
....@@ -1284,7 +1256,6 @@
12841256 		cmd = sp->cmd;
12851257 		bus = SCSI_BUS_32(cmd);
12861258 		target = SCSI_TCN_32(cmd);
1287
-		lun = SCSI_LUN_32(cmd);
12881259 
12891260 		switch ((CMD_RESULT(cmd) >> 16)) {
12901261 		case DID_RESET:
....@@ -1445,15 +1416,6 @@
14451416 	ha->flags.disable_host_adapter = 0;
14461417 	ha->flags.reset_active = 0;
14471418 	ha->flags.abort_isp_active = 0;
1448
-
1449
-#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
1450
-	if (ia64_platform_is("sn2")) {
1451
-		printk(KERN_INFO "scsi(%li): Enabling SN2 PCI DMA "
1452
-		       "dual channel lockup workaround\n", ha->host_no);
1453
-		ha->flags.use_pci_vchannel = 1;
1454
-		driver_setup.no_nvram = 1;
1455
-	}
1456
-#endif
14571419 
14581420 	/* TODO: implement support for the 1040 nvram format */
14591421 	if (IS_ISP1040(ha))
....@@ -1736,6 +1698,16 @@
17361698 	return err;
17371699 }
17381700 
1701
+#ifdef QLA_64BIT_PTR
1702
+#define LOAD_CMD	MBC_LOAD_RAM_A64_ROM
1703
+#define DUMP_CMD	MBC_DUMP_RAM_A64_ROM
1704
+#define CMD_ARGS	(BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1705
+#else
1706
+#define LOAD_CMD	MBC_LOAD_RAM
1707
+#define DUMP_CMD	MBC_DUMP_RAM
1708
+#define CMD_ARGS	(BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1709
+#endif
1710
+
17391711 #define DUMP_IT_BACK 0		/* for debug of RISC loading */
17401712 static int
17411713 qla1280_load_firmware_dma(struct scsi_qla_host *ha)
....@@ -1750,7 +1722,7 @@
17501722 	uint8_t *sp, *tbuf;
17511723 	dma_addr_t p_tbuf;
17521724 
1753
-	tbuf = pci_alloc_consistent(ha->pdev, 8000, &p_tbuf);
1725
+	tbuf = dma_alloc_coherent(&ha->pdev->dev, 8000, &p_tbuf, GFP_KERNEL);
17541726 	if (!tbuf)
17551727 		return -ENOMEM;
17561728 #endif
....@@ -1785,19 +1757,18 @@
17851757 		for(i = 0; i < cnt; i++)
17861758 			((__le16 *)ha->request_ring)[i] = fw_data[i];
17871759 
1788
-		mb[0] = MBC_LOAD_RAM;
1760
+		mb[0] = LOAD_CMD;
17891761 		mb[1] = risc_address;
17901762 		mb[4] = cnt;
17911763 		mb[3] = ha->request_dma & 0xffff;
17921764 		mb[2] = (ha->request_dma >> 16) & 0xffff;
1793
-		mb[7] = pci_dma_hi32(ha->request_dma) & 0xffff;
1794
-		mb[6] = pci_dma_hi32(ha->request_dma) >> 16;
1765
+		mb[7] = upper_32_bits(ha->request_dma) & 0xffff;
1766
+		mb[6] = upper_32_bits(ha->request_dma) >> 16;
17951767 		dprintk(2, "%s: op=%d  0x%p = 0x%4x,0x%4x,0x%4x,0x%4x\n",
17961768 				__func__, mb[0],
17971769 				(void *)(long)ha->request_dma,
17981770 				mb[6], mb[7], mb[2], mb[3]);
1799
-		err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 |
1800
-				BIT_1 | BIT_0, mb);
1771
+		err = qla1280_mailbox_command(ha, CMD_ARGS, mb);
18011772 		if (err) {
18021773 			printk(KERN_ERR "scsi(%li): Failed to load partial "
18031774 			       "segment of f\n", ha->host_no);
....@@ -1805,16 +1776,15 @@
18051776 		}
18061777 
18071778 #if DUMP_IT_BACK
1808
-		mb[0] = MBC_DUMP_RAM;
1779
+		mb[0] = DUMP_CMD;
18091780 		mb[1] = risc_address;
18101781 		mb[4] = cnt;
18111782 		mb[3] = p_tbuf & 0xffff;
18121783 		mb[2] = (p_tbuf >> 16) & 0xffff;
1813
-		mb[7] = pci_dma_hi32(p_tbuf) & 0xffff;
1814
-		mb[6] = pci_dma_hi32(p_tbuf) >> 16;
1784
+		mb[7] = upper_32_bits(p_tbuf) & 0xffff;
1785
+		mb[6] = upper_32_bits(p_tbuf) >> 16;
18151786 
1816
-		err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 |
1817
-				BIT_1 | BIT_0, mb);
1787
+		err = qla1280_mailbox_command(ha, CMD_ARGS, mb);
18181788 		if (err) {
18191789 			printk(KERN_ERR
18201790 			       "Failed to dump partial segment of f/w\n");
....@@ -1841,7 +1811,7 @@
18411811 
18421812  out:
18431813 #if DUMP_IT_BACK
1844
-	pci_free_consistent(ha->pdev, 8000, tbuf, p_tbuf);
1814
+	dma_free_coherent(&ha->pdev->dev, 8000, tbuf, p_tbuf);
18451815 #endif
18461816 	return err;
18471817 }
....@@ -1933,8 +1903,8 @@
19331903 	mb[3] = ha->request_dma & 0xffff;
19341904 	mb[2] = (ha->request_dma >> 16) & 0xffff;
19351905 	mb[4] = 0;
1936
-	mb[7] = pci_dma_hi32(ha->request_dma) & 0xffff;
1937
-	mb[6] = pci_dma_hi32(ha->request_dma) >> 16;
1906
+	mb[7] = upper_32_bits(ha->request_dma) & 0xffff;
1907
+	mb[6] = upper_32_bits(ha->request_dma) >> 16;
19381908 	if (!(status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_4 |
19391909 					       BIT_3 | BIT_2 | BIT_1 | BIT_0,
19401910 					       &mb[0]))) {
....@@ -1947,8 +1917,8 @@
19471917 		mb[3] = ha->response_dma & 0xffff;
19481918 		mb[2] = (ha->response_dma >> 16) & 0xffff;
19491919 		mb[5] = 0;
1950
-		mb[7] = pci_dma_hi32(ha->response_dma) & 0xffff;
1951
-		mb[6] = pci_dma_hi32(ha->response_dma) >> 16;
1920
+		mb[7] = upper_32_bits(ha->response_dma) & 0xffff;
1921
+		mb[6] = upper_32_bits(ha->response_dma) >> 16;
19521922 		status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_5 |
19531923 						 BIT_3 | BIT_2 | BIT_1 | BIT_0,
19541924 						 &mb[0]);
....@@ -2214,13 +2184,12 @@
22142184 		nv->cntr_flags_1.disable_loading_risc_code;
22152185 
22162186 	if (IS_ISP1040(ha)) {
2217
-		uint16_t hwrev, cfg1, cdma_conf, ddma_conf;
2187
+		uint16_t hwrev, cfg1, cdma_conf;
22182188 
22192189 		hwrev = RD_REG_WORD(&reg->cfg_0) & ISP_CFG0_HWMSK;
22202190 
22212191 		cfg1 = RD_REG_WORD(&reg->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6);
22222192 		cdma_conf = RD_REG_WORD(&reg->cdma_cfg);
2223
-		ddma_conf = RD_REG_WORD(&reg->ddma_cfg);
22242193 
22252194 		/* Busted fifo, says mjacob. */
22262195 		if (hwrev != ISP_CFG0_1040A)
....@@ -2270,13 +2239,6 @@
22702239 	mb[1] = nv->firmware_feature.f.enable_fast_posting;
22712240 	mb[1] |= nv->firmware_feature.f.report_lvd_bus_transition << 1;
22722241 	mb[1] |= nv->firmware_feature.f.disable_synchronous_backoff << 5;
2273
-#if defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_SGI_SN2)
2274
-	if (ia64_platform_is("sn2")) {
2275
-		printk(KERN_INFO "scsi(%li): Enabling SN2 PCI DMA "
2276
-		       "workaround\n", ha->host_no);
2277
-		mb[1] |= nv->firmware_feature.f.unused_9 << 9; /* XXX */
2278
-	}
2279
-#endif
22802242 	status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
22812243 
22822244 	/* Retry count and delay. */
....@@ -2463,7 +2425,6 @@
24632425 	int cnt;
24642426 	uint16_t *optr, *iptr;
24652427 	uint16_t __iomem *mptr;
2466
-	uint16_t data;
24672428 	DECLARE_COMPLETION_ONSTACK(wait);
24682429 
24692430 	ENTER("qla1280_mailbox_command");
....@@ -2498,7 +2459,7 @@
24982459 
24992460 	spin_unlock_irq(ha->host->host_lock);
25002461 	WRT_REG_WORD(&reg->host_cmd, HC_SET_HOST_INT);
2501
-	data = qla1280_debounce_register(&reg->istatus);
2462
+	qla1280_debounce_register(&reg->istatus);
25022463 
25032464 	wait_for_completion(&wait);
25042465 	del_timer_sync(&ha->mailbox_timer);
....@@ -2907,20 +2868,14 @@
29072868 				break;
29082869 
29092870 			dma_handle = sg_dma_address(s);
2910
-#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2911
-			if (ha->flags.use_pci_vchannel)
2912
-				sn_pci_set_vchan(ha->pdev,
2913
-						 (unsigned long *)&dma_handle,
2914
-						 SCSI_BUS_32(cmd));
2915
-#endif
29162871 			*dword_ptr++ =
2917
-				cpu_to_le32(pci_dma_lo32(dma_handle));
2872
+				cpu_to_le32(lower_32_bits(dma_handle));
29182873 			*dword_ptr++ =
2919
-				cpu_to_le32(pci_dma_hi32(dma_handle));
2874
+				cpu_to_le32(upper_32_bits(dma_handle));
29202875 			*dword_ptr++ = cpu_to_le32(sg_dma_len(s));
29212876 			dprintk(3, "S/G Segment phys_addr=%x %x, len=0x%x\n",
2922
-				cpu_to_le32(pci_dma_hi32(dma_handle)),
2923
-				cpu_to_le32(pci_dma_lo32(dma_handle)),
2877
+				cpu_to_le32(upper_32_bits(dma_handle)),
2878
+				cpu_to_le32(lower_32_bits(dma_handle)),
29242879 				cpu_to_le32(sg_dma_len(sg_next(s))));
29252880 			remseg--;
29262881 		}
....@@ -2969,21 +2924,15 @@
29692924 				if (cnt == 5)
29702925 					break;
29712926 				dma_handle = sg_dma_address(s);
2972
-#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2973
-				if (ha->flags.use_pci_vchannel)
2974
-					sn_pci_set_vchan(ha->pdev,
2975
-							 (unsigned long *)&dma_handle,
2976
-							 SCSI_BUS_32(cmd));
2977
-#endif
29782927 				*dword_ptr++ =
2979
-					cpu_to_le32(pci_dma_lo32(dma_handle));
2928
+					cpu_to_le32(lower_32_bits(dma_handle));
29802929 				*dword_ptr++ =
2981
-					cpu_to_le32(pci_dma_hi32(dma_handle));
2930
+					cpu_to_le32(upper_32_bits(dma_handle));
29822931 				*dword_ptr++ =
29832932 					cpu_to_le32(sg_dma_len(s));
29842933 				dprintk(3, "S/G Segment Cont. phys_addr=%x %x, len=0x%x\n",
2985
-					cpu_to_le32(pci_dma_hi32(dma_handle)),
2986
-					cpu_to_le32(pci_dma_lo32(dma_handle)),
2934
+					cpu_to_le32(upper_32_bits(dma_handle)),
2935
+					cpu_to_le32(lower_32_bits(dma_handle)),
29872936 					cpu_to_le32(sg_dma_len(s)));
29882937 			}
29892938 			remseg -= cnt;
....@@ -3014,8 +2963,6 @@
30142963 	sp->flags |= SRB_SENT;
30152964 	ha->actthreads++;
30162965 	WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
3017
-	/* Enforce mmio write ordering; see comment in qla1280_isp_cmd(). */
3018
-	mmiowb();
30192966 
30202967  out:
30212968 	if (status)
....@@ -3178,10 +3125,10 @@
31783125 			if (cnt == 4)
31793126 				break;
31803127 			*dword_ptr++ =
3181
-				cpu_to_le32(pci_dma_lo32(sg_dma_address(s)));
3128
+				cpu_to_le32(lower_32_bits(sg_dma_address(s)));
31823129 			*dword_ptr++ = cpu_to_le32(sg_dma_len(s));
31833130 			dprintk(3, "S/G Segment phys_addr=0x%lx, len=0x%x\n",
3184
-				(pci_dma_lo32(sg_dma_address(s))),
3131
+				(lower_32_bits(sg_dma_address(s))),
31853132 				(sg_dma_len(s)));
31863133 			remseg--;
31873134 		}
....@@ -3224,13 +3171,13 @@
32243171 				if (cnt == 7)
32253172 					break;
32263173 				*dword_ptr++ =
3227
-					cpu_to_le32(pci_dma_lo32(sg_dma_address(s)));
3174
+					cpu_to_le32(lower_32_bits(sg_dma_address(s)));
32283175 				*dword_ptr++ =
32293176 					cpu_to_le32(sg_dma_len(s));
32303177 				dprintk(1,
32313178 					"S/G Segment Cont. phys_addr=0x%x, "
32323179 					"len=0x%x\n",
3233
-					cpu_to_le32(pci_dma_lo32(sg_dma_address(s))),
3180
+					cpu_to_le32(lower_32_bits(sg_dma_address(s))),
32343181 					cpu_to_le32(sg_dma_len(s)));
32353182 			}
32363183 			remseg -= cnt;
....@@ -3264,8 +3211,6 @@
32643211 	sp->flags |= SRB_SENT;
32653212 	ha->actthreads++;
32663213 	WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
3267
-	/* Enforce mmio write ordering; see comment in qla1280_isp_cmd(). */
3268
-	mmiowb();
32693214 
32703215 out:
32713216 	if (status)
....@@ -3377,19 +3322,8 @@
33773322 
33783323 	/*
33793324 	 * Update request index to mailbox4 (Request Queue In).
3380
-	 * The mmiowb() ensures that this write is ordered with writes by other
3381
-	 * CPUs.  Without the mmiowb(), it is possible for the following:
3382
-	 *    CPUA posts write of index 5 to mailbox4
3383
-	 *    CPUA releases host lock
3384
-	 *    CPUB acquires host lock
3385
-	 *    CPUB posts write of index 6 to mailbox4
3386
-	 *    On PCI bus, order reverses and write of 6 posts, then index 5,
3387
-	 *       causing chip to issue full queue of stale commands
3388
-	 * The mmiowb() prevents future writes from crossing the barrier.
3389
-	 * See Documentation/driver-api/device-io.rst for more information.
33903325 	 */
33913326 	WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
3392
-	mmiowb();
33933327 
33943328 	LEAVE("qla1280_isp_cmd");
33953329 }
....@@ -3667,7 +3601,6 @@
36673601 qla1280_status_entry(struct scsi_qla_host *ha, struct response *pkt,
36683602 		     struct list_head *done_q)
36693603 {
3670
-	unsigned int bus, target, lun;
36713604 	int sense_sz;
36723605 	struct srb *sp;
36733606 	struct scsi_cmnd *cmd;
....@@ -3692,11 +3625,6 @@
36923625 	ha->outstanding_cmds[handle] = NULL;
36933626 
36943627 	cmd = sp->cmd;
3695
-
3696
-	/* Generate LU queue on cntrl, target, LUN */
3697
-	bus = SCSI_BUS_32(cmd);
3698
-	target = SCSI_TCN_32(cmd);
3699
-	lun = SCSI_LUN_32(cmd);
37003628 
37013629 	if (comp_status || scsi_status) {
37023630 		dprintk(3, "scsi: comp_status = 0x%x, scsi_status = "
....@@ -3736,7 +3664,8 @@
37363664 
37373665 			dprintk(2, "qla1280_status_entry: Check "
37383666 				"condition Sense data, b %i, t %i, "
3739
-				"l %i\n", bus, target, lun);
3667
+				"l %i\n", SCSI_BUS_32(cmd), SCSI_TCN_32(cmd),
3668
+				SCSI_LUN_32(cmd));
37403669 			if (sense_sz)
37413670 				qla1280_dump_buffer(2,
37423671 						    (char *)cmd->sense_buffer,
....@@ -4213,7 +4142,6 @@
42134142 	.can_queue		= MAX_OUTSTANDING_COMMANDS,
42144143 	.this_id		= -1,
42154144 	.sg_tablesize		= SG_ALL,
4216
-	.use_clustering		= ENABLE_CLUSTERING,
42174145 };
42184146 
42194147 
....@@ -4259,8 +4187,8 @@
42594187 	ha->devnum = devnum;	/* specifies microcode load address */
42604188 
42614189 #ifdef QLA_64BIT_PTR
4262
-	if (pci_set_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
4263
-		if (pci_set_dma_mask(ha->pdev, DMA_BIT_MASK(32))) {
4190
+	if (dma_set_mask_and_coherent(&ha->pdev->dev, DMA_BIT_MASK(64))) {
4191
+		if (dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32))) {
42644192 			printk(KERN_WARNING "scsi(%li): Unable to set a "
42654193 			       "suitable DMA mask - aborting\n", ha->host_no);
42664194 			error = -ENODEV;
....@@ -4270,7 +4198,7 @@
42704198 		dprintk(2, "scsi(%li): 64 Bit PCI Addressing Enabled\n",
42714199 			ha->host_no);
42724200 #else
4273
-	if (pci_set_dma_mask(ha->pdev, DMA_BIT_MASK(32))) {
4201
+	if (dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32))) {
42744202 		printk(KERN_WARNING "scsi(%li): Unable to set a "
42754203 		       "suitable DMA mask - aborting\n", ha->host_no);
42764204 		error = -ENODEV;
....@@ -4278,17 +4206,17 @@
42784206 	}
42794207 #endif
42804208 
4281
-	ha->request_ring = pci_alloc_consistent(ha->pdev,
4209
+	ha->request_ring = dma_alloc_coherent(&ha->pdev->dev,
42824210 			((REQUEST_ENTRY_CNT + 1) * sizeof(request_t)),
4283
-			&ha->request_dma);
4211
+			&ha->request_dma, GFP_KERNEL);
42844212 	if (!ha->request_ring) {
42854213 		printk(KERN_INFO "qla1280: Failed to get request memory\n");
42864214 		goto error_put_host;
42874215 	}
42884216 
4289
-	ha->response_ring = pci_alloc_consistent(ha->pdev,
4217
+	ha->response_ring = dma_alloc_coherent(&ha->pdev->dev,
42904218 			((RESPONSE_ENTRY_CNT + 1) * sizeof(struct response)),
4291
-			&ha->response_dma);
4219
+			&ha->response_dma, GFP_KERNEL);
42924220 	if (!ha->response_ring) {
42934221 		printk(KERN_INFO "qla1280: Failed to get response memory\n");
42944222 		goto error_free_request_ring;
....@@ -4370,11 +4298,11 @@
43704298 	release_region(host->io_port, 0xff);
43714299 #endif
43724300  error_free_response_ring:
4373
-	pci_free_consistent(ha->pdev,
4301
+	dma_free_coherent(&ha->pdev->dev,
43744302 			((RESPONSE_ENTRY_CNT + 1) * sizeof(struct response)),
43754303 			ha->response_ring, ha->response_dma);
43764304  error_free_request_ring:
4377
-	pci_free_consistent(ha->pdev,
4305
+	dma_free_coherent(&ha->pdev->dev,
43784306 			((REQUEST_ENTRY_CNT + 1) * sizeof(request_t)),
43794307 			ha->request_ring, ha->request_dma);
43804308  error_put_host:
....@@ -4404,10 +4332,10 @@
44044332 	release_region(host->io_port, 0xff);
44054333 #endif
44064334 
4407
-	pci_free_consistent(ha->pdev,
4335
+	dma_free_coherent(&ha->pdev->dev,
44084336 			((REQUEST_ENTRY_CNT + 1) * (sizeof(request_t))),
44094337 			ha->request_ring, ha->request_dma);
4410
-	pci_free_consistent(ha->pdev,
4338
+	dma_free_coherent(&ha->pdev->dev,
44114339 			((RESPONSE_ENTRY_CNT + 1) * (sizeof(struct response))),
44124340 			ha->response_ring, ha->response_dma);
44134341