add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/scsi/arcmsr/arcmsr.h
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@@ -49,7 +49,7 @@
49
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 #define ARCMSR_MAX_OUTSTANDING_CMD	1024
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 #define ARCMSR_DEFAULT_OUTSTANDING_CMD	128
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 #define ARCMSR_MIN_OUTSTANDING_CMD	32
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-#define ARCMSR_DRIVER_VERSION		"v1.40.00.09-20180709"
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+#define ARCMSR_DRIVER_VERSION		"v1.50.00.02-20200819"
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 #define ARCMSR_SCSI_INITIATOR_ID	255
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 #define ARCMSR_MAX_XFER_SECTORS		512
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 #define ARCMSR_MAX_XFER_SECTORS_B	4096
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@@ -80,6 +80,7 @@
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 #ifndef PCI_DEVICE_ID_ARECA_1884
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 #define PCI_DEVICE_ID_ARECA_1884	0x1884
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 #endif
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+#define PCI_DEVICE_ID_ARECA_1886	0x188A
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 #define	ARCMSR_HOURS			(1000 * 60 * 60 * 4)
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 #define	ARCMSR_MINUTES			(1000 * 60 * 60)
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 /*
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@@ -436,6 +437,21 @@
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 #define ARCMSR_HBEMU_DOORBELL_SYNC		0x100
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 #define ARCMSR_ARC188X_RESET_ADAPTER		0x00000004
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 #define ARCMSR_ARC1884_DiagWrite_ENABLE		0x00000080
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+
441
+/*
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+*******************************************************************************
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+**                SPEC. for Areca Type F adapter
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+*******************************************************************************
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+*/
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+#define ARCMSR_SIGNATURE_1886			0x188617D3
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+// Doorbell and interrupt definition are same as Type E adapter
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+/* ARC-1886 doorbell sync */
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+#define ARCMSR_HBFMU_DOORBELL_SYNC		0x100
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+//set host rw buffer physical address at inbound message 0, 1 (low,high)
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+#define ARCMSR_HBFMU_DOORBELL_SYNC1		0x300
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+#define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK	0x80000000
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+#define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE	0x20000000
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+
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 /*
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 *******************************************************************************
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 **    ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
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@@ -720,6 +736,80 @@
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 	uint32_t	msgcode_rwbuffer[256];			/*2200 23FF*/
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 };
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738
 
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+/*
740
+*********************************************************************
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+**     Messaging Unit (MU) of Type F processor(LSI)
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+*********************************************************************
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+*/
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+struct MessageUnit_F {
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+	uint32_t	iobound_doorbell;			/*0000 0003*/
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+	uint32_t	write_sequence_3xxx;			/*0004 0007*/
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+	uint32_t	host_diagnostic_3xxx;			/*0008 000B*/
748
+	uint32_t	posted_outbound_doorbell;		/*000C 000F*/
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+	uint32_t	master_error_attribute;			/*0010 0013*/
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+	uint32_t	master_error_address_low;		/*0014 0017*/
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+	uint32_t	master_error_address_high;		/*0018 001B*/
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+	uint32_t	hcb_size;				/*001C 001F*/
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+	uint32_t	inbound_doorbell;			/*0020 0023*/
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+	uint32_t	diagnostic_rw_data;			/*0024 0027*/
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+	uint32_t	diagnostic_rw_address_low;		/*0028 002B*/
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+	uint32_t	diagnostic_rw_address_high;		/*002C 002F*/
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+	uint32_t	host_int_status;			/*0030 0033*/
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+	uint32_t	host_int_mask;				/*0034 0037*/
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+	uint32_t	dcr_data;				/*0038 003B*/
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+	uint32_t	dcr_address;				/*003C 003F*/
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+	uint32_t	inbound_queueport;			/*0040 0043*/
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+	uint32_t	outbound_queueport;			/*0044 0047*/
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+	uint32_t	hcb_pci_address_low;			/*0048 004B*/
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+	uint32_t	hcb_pci_address_high;			/*004C 004F*/
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+	uint32_t	iop_int_status;				/*0050 0053*/
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+	uint32_t	iop_int_mask;				/*0054 0057*/
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+	uint32_t	iop_inbound_queue_port;			/*0058 005B*/
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+	uint32_t	iop_outbound_queue_port;		/*005C 005F*/
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+	uint32_t	inbound_free_list_index;		/*0060 0063*/
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+	uint32_t	inbound_post_list_index;		/*0064 0067*/
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+	uint32_t	reply_post_producer_index;		/*0068 006B*/
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+	uint32_t	reply_post_consumer_index;		/*006C 006F*/
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+	uint32_t	inbound_doorbell_clear;			/*0070 0073*/
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+	uint32_t	i2o_message_unit_control;		/*0074 0077*/
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+	uint32_t	last_used_message_source_address_low;	/*0078 007B*/
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+	uint32_t	last_used_message_source_address_high;	/*007C 007F*/
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+	uint32_t	pull_mode_data_byte_count[4];		/*0080 008F*/
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+	uint32_t	message_dest_address_index;		/*0090 0093*/
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+	uint32_t	done_queue_not_empty_int_counter_timer;	/*0094 0097*/
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+	uint32_t	utility_A_int_counter_timer;		/*0098 009B*/
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+	uint32_t	outbound_doorbell;			/*009C 009F*/
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+	uint32_t	outbound_doorbell_clear;		/*00A0 00A3*/
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+	uint32_t	message_source_address_index;		/*00A4 00A7*/
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+	uint32_t	message_done_queue_index;		/*00A8 00AB*/
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+	uint32_t	reserved0;				/*00AC 00AF*/
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+	uint32_t	inbound_msgaddr0;			/*00B0 00B3*/
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+	uint32_t	inbound_msgaddr1;			/*00B4 00B7*/
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+	uint32_t	outbound_msgaddr0;			/*00B8 00BB*/
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+	uint32_t	outbound_msgaddr1;			/*00BC 00BF*/
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+	uint32_t	inbound_queueport_low;			/*00C0 00C3*/
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+	uint32_t	inbound_queueport_high;			/*00C4 00C7*/
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+	uint32_t	outbound_queueport_low;			/*00C8 00CB*/
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+	uint32_t	outbound_queueport_high;		/*00CC 00CF*/
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+	uint32_t	iop_inbound_queue_port_low;		/*00D0 00D3*/
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+	uint32_t	iop_inbound_queue_port_high;		/*00D4 00D7*/
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+	uint32_t	iop_outbound_queue_port_low;		/*00D8 00DB*/
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+	uint32_t	iop_outbound_queue_port_high;		/*00DC 00DF*/
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+	uint32_t	message_dest_queue_port_low;		/*00E0 00E3*/
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+	uint32_t	message_dest_queue_port_high;		/*00E4 00E7*/
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+	uint32_t	last_used_message_dest_address_low;	/*00E8 00EB*/
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+	uint32_t	last_used_message_dest_address_high;	/*00EC 00EF*/
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+	uint32_t	message_done_queue_base_address_low;	/*00F0 00F3*/
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+	uint32_t	message_done_queue_base_address_high;	/*00F4 00F7*/
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+	uint32_t	host_diagnostic;			/*00F8 00FB*/
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+	uint32_t	write_sequence;				/*00FC 00FF*/
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+	uint32_t	reserved1[46];				/*0100 01B7*/
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+	uint32_t	reply_post_producer_index1;		/*01B8 01BB*/
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+	uint32_t	reply_post_consumer_index1;		/*01BC 01BF*/
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+};
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+
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+#define	MESG_RW_BUFFER_SIZE	(256 * 3)
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+
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 typedef struct deliver_completeQ {
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 	uint16_t	cmdFlag;
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 	uint16_t	cmdSMID;
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@@ -739,7 +829,8 @@
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 #define ACB_ADAPTER_TYPE_C		0x00000002	/* hbc L IOP */
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 #define ACB_ADAPTER_TYPE_D		0x00000003	/* hbd M IOP */
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 #define ACB_ADAPTER_TYPE_E		0x00000004	/* hba L IOP */
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-	u32			roundup_ccbsize;
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+#define ACB_ADAPTER_TYPE_F		0x00000005	/* hba L IOP */
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+	u32			ioqueue_size;
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 	struct pci_dev *	pdev;
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 	struct Scsi_Host *	host;
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 	unsigned long		vir2phy_offset;
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@@ -747,6 +838,7 @@
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 	uint32_t		outbound_int_enable;
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 	uint32_t		cdb_phyaddr_hi32;
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 	uint32_t		reg_mu_acc_handle0;
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+	uint64_t		cdb_phyadd_hipart;
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 	spinlock_t		eh_lock;
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 	spinlock_t		ccblist_lock;
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 	spinlock_t		postq_lock;
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@@ -759,10 +851,16 @@
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 		struct MessageUnit_C __iomem *pmuC;
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 		struct MessageUnit_D 	*pmuD;
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 		struct MessageUnit_E __iomem *pmuE;
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+		struct MessageUnit_F __iomem *pmuF;
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 	};
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 	/* message unit ATU inbound base address0 */
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 	void __iomem		*mem_base0;
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 	void __iomem		*mem_base1;
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+	//0x000 - COMPORT_IN  (Host sent to ROC)
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+	uint32_t		*message_wbuffer;
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+	//0x100 - COMPORT_OUT (ROC sent to Host)
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+	uint32_t		*message_rbuffer;
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+	uint32_t		*msgcode_rwbuffer;	//0x200 - BIOS_AREA
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 	uint32_t		acb_flags;
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 	u16			dev_id;
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 	uint8_t			adapter_index;
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@@ -835,8 +933,6 @@
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 #define	FW_NORMAL			0x0000
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 #define	FW_BOG				0x0001
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 #define	FW_DEADLOCK			0x0010
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-	atomic_t 		rq_map_token;
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-	atomic_t		ante_token_value;
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 	uint32_t		maxOutstanding;
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 	int			vector_count;
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 	uint32_t		maxFreeCCB;
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@@ -847,6 +943,7 @@
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 	uint32_t		out_doorbell;
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 	uint32_t		completionQ_entry;
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 	pCompletion_Q		pCompletionQ;
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+	uint32_t		completeQ_size;
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 };/* HW_DEVICE_EXTENSION */
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 /*
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 *******************************************************************************
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@@ -855,11 +952,11 @@
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 *******************************************************************************
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 */
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 struct CommandControlBlock{
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-	/*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
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+	/*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
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 	struct list_head		list;		/*x32: 8byte, x64: 16byte*/
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 	struct scsi_cmnd		*pcmd;		/*8 bytes pointer of linux scsi command */
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 	struct AdapterControlBlock	*acb;		/*x32: 4byte, x64: 8byte*/
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-	uint32_t			cdb_phyaddr;	/*x32: 4byte, x64: 4byte*/
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+	unsigned long			cdb_phyaddr;	/*x32: 4byte, x64: 8byte*/
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 	uint32_t			arc_cdb_size;	/*x32:4byte,x64:4byte*/
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 	uint16_t			ccb_flags;	/*x32: 2byte, x64: 2byte*/
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 #define	CCB_FLAG_READ		0x0000
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@@ -875,10 +972,10 @@
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 	uint32_t			smid;
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 #if BITS_PER_LONG == 64
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 	/*  ======================512+64 bytes========================  */
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-		uint32_t		reserved[4];	/*16 byte*/
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+		uint32_t		reserved[3];	/*12 byte*/
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 #else
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 	/*  ======================512+32 bytes========================  */
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-	//	uint32_t		reserved;	/*4  byte*/
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+		uint32_t		reserved[8];	/*32  byte*/
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 #endif
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 	/*  =======================================================   */
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 	struct ARCMSR_CDB		arcmsr_cdb;