add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/reset/reset-simple.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Simple Reset Controller Driver
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  *
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@@ -8,13 +9,9 @@
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  * Copyright 2013 Maxime Ripard
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  *
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  * Maxime Ripard <maxime.ripard@free-electrons.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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13
 
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+#include <linux/delay.h>
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 #include <linux/device.h>
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 #include <linux/err.h>
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 #include <linux/io.h>
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@@ -22,9 +19,8 @@
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 #include <linux/of_device.h>
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 #include <linux/platform_device.h>
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 #include <linux/reset-controller.h>
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+#include <linux/reset/reset-simple.h>
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 #include <linux/spinlock.h>
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-
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-#include "reset-simple.h"
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24
 
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 static inline struct reset_simple_data *
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 to_reset_simple_data(struct reset_controller_dev *rcdev)
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@@ -68,6 +64,24 @@
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 	return reset_simple_update(rcdev, id, false);
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 }
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66
 
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+static int reset_simple_reset(struct reset_controller_dev *rcdev,
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+			      unsigned long id)
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+{
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+	struct reset_simple_data *data = to_reset_simple_data(rcdev);
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+	int ret;
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+
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+	if (!data->reset_us)
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+		return -ENOTSUPP;
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+
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+	ret = reset_simple_assert(rcdev, id);
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+	if (ret)
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+		return ret;
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+
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+	usleep_range(data->reset_us, data->reset_us * 2);
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+
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+	return reset_simple_deassert(rcdev, id);
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+}
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+
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 static int reset_simple_status(struct reset_controller_dev *rcdev,
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 			       unsigned long id)
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 {
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@@ -85,6 +99,7 @@
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 const struct reset_control_ops reset_simple_ops = {
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 	.assert		= reset_simple_assert,
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 	.deassert	= reset_simple_deassert,
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+	.reset		= reset_simple_reset,
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 	.status		= reset_simple_status,
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 };
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 EXPORT_SYMBOL_GPL(reset_simple_ops);
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@@ -109,7 +124,7 @@
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 #define SOCFPGA_NR_BANKS	8
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 static const struct reset_simple_devdata reset_simple_socfpga = {
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-	.reg_offset = 0x10,
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+	.reg_offset = 0x20,
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 	.nr_resets = SOCFPGA_NR_BANKS * 32,
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 	.status_active_low = true,
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 };
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@@ -120,7 +135,8 @@
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 };
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 static const struct of_device_id reset_simple_dt_ids[] = {
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-	{ .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
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+	{ .compatible = "altr,stratix10-rst-mgr",
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+		.data = &reset_simple_socfpga },
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 	{ .compatible = "st,stm32-rcc", },
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 	{ .compatible = "allwinner,sun6i-a31-clock-reset",
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 		.data = &reset_simple_active_low },
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@@ -128,6 +144,11 @@
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 		.data = &reset_simple_active_low },
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 	{ .compatible = "aspeed,ast2400-lpc-reset" },
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 	{ .compatible = "aspeed,ast2500-lpc-reset" },
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+	{ .compatible = "bitmain,bm1880-reset",
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+		.data = &reset_simple_active_low },
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+	{ .compatible = "snps,dw-high-reset" },
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+	{ .compatible = "snps,dw-low-reset",
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+		.data = &reset_simple_active_low },
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 	{ /* sentinel */ },
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 };
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@@ -164,14 +185,6 @@
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 			data->rcdev.nr_resets = devdata->nr_resets;
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 		data->active_low = devdata->active_low;
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 		data->status_active_low = devdata->status_active_low;
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-	}
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-
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-	if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
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-	    of_property_read_u32(dev->of_node, "altr,modrst-offset",
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-				 &reg_offset)) {
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-		dev_warn(dev,
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-			 "missing altr,modrst-offset property, assuming 0x%x!\n",
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-			 reg_offset);
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 	}
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 	data->membase += reg_offset;