forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/pwm/pwm-meson.c
....@@ -1,65 +1,40 @@
1
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
12 /*
2
- * This file is provided under a dual BSD/GPLv2 license.  When using or
3
- * redistributing this file, you may do so under either license.
3
+ * PWM controller driver for Amlogic Meson SoCs.
44  *
5
- * GPL LICENSE SUMMARY
5
+ * This PWM is only a set of Gates, Dividers and Counters:
6
+ * PWM output is achieved by calculating a clock that permits calculating
7
+ * two periods (low and high). The counter then has to be set to switch after
8
+ * N cycles for the first half period.
9
+ * The hardware has no "polarity" setting. This driver reverses the period
10
+ * cycles (the low length is inverted with the high length) for
11
+ * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
12
+ * from the hardware.
13
+ * Setting the duty cycle will disable and re-enable the PWM output.
14
+ * Disabling the PWM stops the output immediately (without waiting for the
15
+ * current period to complete first).
16
+ *
17
+ * The public S912 (GXM) datasheet contains some documentation for this PWM
18
+ * controller starting on page 543:
19
+ * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
20
+ * An updated version of this IP block is found in S922X (G12B) SoCs. The
21
+ * datasheet contains the description for this IP block revision starting at
22
+ * page 1084:
23
+ * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
624  *
725  * Copyright (c) 2016 BayLibre, SAS.
826  * Author: Neil Armstrong <narmstrong@baylibre.com>
927  * Copyright (C) 2014 Amlogic, Inc.
10
- *
11
- * This program is free software; you can redistribute it and/or modify
12
- * it under the terms of version 2 of the GNU General Public License as
13
- * published by the Free Software Foundation.
14
- *
15
- * This program is distributed in the hope that it will be useful, but
16
- * WITHOUT ANY WARRANTY; without even the implied warranty of
17
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18
- * General Public License for more details.
19
- *
20
- * You should have received a copy of the GNU General Public License
21
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
22
- * The full GNU General Public License is included in this distribution
23
- * in the file called COPYING.
24
- *
25
- * BSD LICENSE
26
- *
27
- * Copyright (c) 2016 BayLibre, SAS.
28
- * Author: Neil Armstrong <narmstrong@baylibre.com>
29
- * Copyright (C) 2014 Amlogic, Inc.
30
- *
31
- * Redistribution and use in source and binary forms, with or without
32
- * modification, are permitted provided that the following conditions
33
- * are met:
34
- *
35
- *   * Redistributions of source code must retain the above copyright
36
- *     notice, this list of conditions and the following disclaimer.
37
- *   * Redistributions in binary form must reproduce the above copyright
38
- *     notice, this list of conditions and the following disclaimer in
39
- *     the documentation and/or other materials provided with the
40
- *     distribution.
41
- *   * Neither the name of Intel Corporation nor the names of its
42
- *     contributors may be used to endorse or promote products derived
43
- *     from this software without specific prior written permission.
44
- *
45
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
46
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
47
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
48
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
49
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
50
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
52
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
53
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
54
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
55
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5628  */
5729 
30
+#include <linux/bitfield.h>
31
+#include <linux/bits.h>
5832 #include <linux/clk.h>
5933 #include <linux/clk-provider.h>
6034 #include <linux/err.h>
6135 #include <linux/io.h>
6236 #include <linux/kernel.h>
37
+#include <linux/math64.h>
6338 #include <linux/module.h>
6439 #include <linux/of.h>
6540 #include <linux/of_device.h>
....@@ -70,7 +45,8 @@
7045 
7146 #define REG_PWM_A		0x0
7247 #define REG_PWM_B		0x4
73
-#define PWM_HIGH_SHIFT		16
48
+#define PWM_LOW_MASK		GENMASK(15, 0)
49
+#define PWM_HIGH_MASK		GENMASK(31, 16)
7450 
7551 #define REG_MISC_AB		0x8
7652 #define MISC_B_CLK_EN		BIT(23)
....@@ -80,21 +56,39 @@
8056 #define MISC_A_CLK_DIV_SHIFT	8
8157 #define MISC_B_CLK_SEL_SHIFT	6
8258 #define MISC_A_CLK_SEL_SHIFT	4
83
-#define MISC_CLK_SEL_WIDTH	2
59
+#define MISC_CLK_SEL_MASK	0x3
8460 #define MISC_B_EN		BIT(1)
8561 #define MISC_A_EN		BIT(0)
8662 
87
-static const unsigned int mux_reg_shifts[] = {
88
-	MISC_A_CLK_SEL_SHIFT,
89
-	MISC_B_CLK_SEL_SHIFT
63
+#define MESON_NUM_PWMS		2
64
+
65
+static struct meson_pwm_channel_data {
66
+	u8		reg_offset;
67
+	u8		clk_sel_shift;
68
+	u8		clk_div_shift;
69
+	u32		clk_en_mask;
70
+	u32		pwm_en_mask;
71
+} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
72
+	{
73
+		.reg_offset	= REG_PWM_A,
74
+		.clk_sel_shift	= MISC_A_CLK_SEL_SHIFT,
75
+		.clk_div_shift	= MISC_A_CLK_DIV_SHIFT,
76
+		.clk_en_mask	= MISC_A_CLK_EN,
77
+		.pwm_en_mask	= MISC_A_EN,
78
+	},
79
+	{
80
+		.reg_offset	= REG_PWM_B,
81
+		.clk_sel_shift	= MISC_B_CLK_SEL_SHIFT,
82
+		.clk_div_shift	= MISC_B_CLK_DIV_SHIFT,
83
+		.clk_en_mask	= MISC_B_CLK_EN,
84
+		.pwm_en_mask	= MISC_B_EN,
85
+	}
9086 };
9187 
9288 struct meson_pwm_channel {
9389 	unsigned int hi;
9490 	unsigned int lo;
9591 	u8 pre_div;
96
-
97
-	struct pwm_state state;
9892 
9993 	struct clk *clk_parent;
10094 	struct clk_mux mux;
....@@ -109,8 +103,8 @@
109103 struct meson_pwm {
110104 	struct pwm_chip chip;
111105 	const struct meson_pwm_data *data;
106
+	struct meson_pwm_channel channels[MESON_NUM_PWMS];
112107 	void __iomem *base;
113
-	u8 inverter_mask;
114108 	/*
115109 	 * Protects register (write) access to the REG_MISC_AB register
116110 	 * that is shared between the two PWMs.
....@@ -125,12 +119,16 @@
125119 
126120 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
127121 {
128
-	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
122
+	struct meson_pwm *meson = to_meson_pwm(chip);
123
+	struct meson_pwm_channel *channel;
129124 	struct device *dev = chip->dev;
130125 	int err;
131126 
132
-	if (!channel)
133
-		return -ENODEV;
127
+	channel = pwm_get_chip_data(pwm);
128
+	if (channel)
129
+		return 0;
130
+
131
+	channel = &meson->channels[pwm->hwpwm];
134132 
135133 	if (channel->clk_parent) {
136134 		err = clk_set_parent(channel->clk, channel->clk_parent);
....@@ -138,7 +136,7 @@
138136 			dev_err(dev, "failed to set parent %s for %s: %d\n",
139137 				__clk_get_name(channel->clk_parent),
140138 				__clk_get_name(channel->clk), err);
141
-				return err;
139
+			return err;
142140 		}
143141 	}
144142 
....@@ -149,9 +147,7 @@
149147 		return err;
150148 	}
151149 
152
-	chip->ops->get_state(chip, pwm, &channel->state);
153
-
154
-	return 0;
150
+	return pwm_set_chip_data(pwm, channel);
155151 }
156152 
157153 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
....@@ -162,20 +158,18 @@
162158 		clk_disable_unprepare(channel->clk);
163159 }
164160 
165
-static int meson_pwm_calc(struct meson_pwm *meson,
166
-			  struct meson_pwm_channel *channel, unsigned int id,
167
-			  unsigned int duty, unsigned int period)
161
+static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
162
+			  const struct pwm_state *state)
168163 {
169
-	unsigned int pre_div, cnt, duty_cnt;
170
-	unsigned long fin_freq = -1;
171
-	u64 fin_ps;
164
+	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
165
+	unsigned int duty, period, pre_div, cnt, duty_cnt;
166
+	unsigned long fin_freq;
172167 
173
-	if (~(meson->inverter_mask >> id) & 0x1)
168
+	duty = state->duty_cycle;
169
+	period = state->period;
170
+
171
+	if (state->polarity == PWM_POLARITY_INVERSED)
174172 		duty = period - duty;
175
-
176
-	if (period == channel->state.period &&
177
-	    duty == channel->state.duty_cycle)
178
-		return 0;
179173 
180174 	fin_freq = clk_get_rate(channel->clk);
181175 	if (fin_freq == 0) {
....@@ -184,21 +178,16 @@
184178 	}
185179 
186180 	dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
187
-	fin_ps = (u64)NSEC_PER_SEC * 1000;
188
-	do_div(fin_ps, fin_freq);
189181 
190
-	/* Calc pre_div with the period */
191
-	for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
192
-		cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
193
-					    fin_ps * (pre_div + 1));
194
-		dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
195
-			fin_ps, pre_div, cnt);
196
-		if (cnt <= 0xffff)
197
-			break;
198
-	}
199
-
182
+	pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
200183 	if (pre_div > MISC_CLK_DIV_MASK) {
201184 		dev_err(meson->chip.dev, "unable to get period pre_div\n");
185
+		return -EINVAL;
186
+	}
187
+
188
+	cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
189
+	if (cnt > 0xffff) {
190
+		dev_err(meson->chip.dev, "unable to get period cnt\n");
202191 		return -EINVAL;
203192 	}
204193 
....@@ -215,8 +204,8 @@
215204 		channel->lo = cnt;
216205 	} else {
217206 		/* Then check is we can have the duty with the same pre_div */
218
-		duty_cnt = DIV_ROUND_CLOSEST_ULL((u64)duty * 1000,
219
-						 fin_ps * (pre_div + 1));
207
+		duty_cnt = div64_u64(fin_freq * (u64)duty,
208
+				     NSEC_PER_SEC * (pre_div + 1));
220209 		if (duty_cnt > 0xffff) {
221210 			dev_err(meson->chip.dev, "unable to get duty cycle\n");
222211 			return -EINVAL;
....@@ -233,80 +222,50 @@
233222 	return 0;
234223 }
235224 
236
-static void meson_pwm_enable(struct meson_pwm *meson,
237
-			     struct meson_pwm_channel *channel,
238
-			     unsigned int id)
225
+static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
239226 {
240
-	u32 value, clk_shift, clk_enable, enable;
241
-	unsigned int offset;
227
+	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
228
+	struct meson_pwm_channel_data *channel_data;
242229 	unsigned long flags;
230
+	u32 value;
243231 
244
-	switch (id) {
245
-	case 0:
246
-		clk_shift = MISC_A_CLK_DIV_SHIFT;
247
-		clk_enable = MISC_A_CLK_EN;
248
-		enable = MISC_A_EN;
249
-		offset = REG_PWM_A;
250
-		break;
251
-
252
-	case 1:
253
-		clk_shift = MISC_B_CLK_DIV_SHIFT;
254
-		clk_enable = MISC_B_CLK_EN;
255
-		enable = MISC_B_EN;
256
-		offset = REG_PWM_B;
257
-		break;
258
-
259
-	default:
260
-		return;
261
-	}
232
+	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
262233 
263234 	spin_lock_irqsave(&meson->lock, flags);
264235 
265236 	value = readl(meson->base + REG_MISC_AB);
266
-	value &= ~(MISC_CLK_DIV_MASK << clk_shift);
267
-	value |= channel->pre_div << clk_shift;
268
-	value |= clk_enable;
237
+	value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
238
+	value |= channel->pre_div << channel_data->clk_div_shift;
239
+	value |= channel_data->clk_en_mask;
269240 	writel(value, meson->base + REG_MISC_AB);
270241 
271
-	value = (channel->hi << PWM_HIGH_SHIFT) | channel->lo;
272
-	writel(value, meson->base + offset);
242
+	value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
243
+		FIELD_PREP(PWM_LOW_MASK, channel->lo);
244
+	writel(value, meson->base + channel_data->reg_offset);
273245 
274246 	value = readl(meson->base + REG_MISC_AB);
275
-	value |= enable;
247
+	value |= channel_data->pwm_en_mask;
276248 	writel(value, meson->base + REG_MISC_AB);
277249 
278250 	spin_unlock_irqrestore(&meson->lock, flags);
279251 }
280252 
281
-static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
253
+static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
282254 {
283
-	u32 value, enable;
284255 	unsigned long flags;
285
-
286
-	switch (id) {
287
-	case 0:
288
-		enable = MISC_A_EN;
289
-		break;
290
-
291
-	case 1:
292
-		enable = MISC_B_EN;
293
-		break;
294
-
295
-	default:
296
-		return;
297
-	}
256
+	u32 value;
298257 
299258 	spin_lock_irqsave(&meson->lock, flags);
300259 
301260 	value = readl(meson->base + REG_MISC_AB);
302
-	value &= ~enable;
261
+	value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
303262 	writel(value, meson->base + REG_MISC_AB);
304263 
305264 	spin_unlock_irqrestore(&meson->lock, flags);
306265 }
307266 
308267 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
309
-			   struct pwm_state *state)
268
+			   const struct pwm_state *state)
310269 {
311270 	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
312271 	struct meson_pwm *meson = to_meson_pwm(chip);
....@@ -316,64 +275,97 @@
316275 		return -EINVAL;
317276 
318277 	if (!state->enabled) {
319
-		meson_pwm_disable(meson, pwm->hwpwm);
320
-		channel->state.enabled = false;
278
+		if (state->polarity == PWM_POLARITY_INVERSED) {
279
+			/*
280
+			 * This IP block revision doesn't have an "always high"
281
+			 * setting which we can use for "inverted disabled".
282
+			 * Instead we achieve this using the same settings
283
+			 * that we use a pre_div of 0 (to get the shortest
284
+			 * possible duration for one "count") and
285
+			 * "period == duty_cycle". This results in a signal
286
+			 * which is LOW for one "count", while being HIGH for
287
+			 * the rest of the (so the signal is HIGH for slightly
288
+			 * less than 100% of the period, but this is the best
289
+			 * we can achieve).
290
+			 */
291
+			channel->pre_div = 0;
292
+			channel->hi = ~0;
293
+			channel->lo = 0;
321294 
322
-		return 0;
323
-	}
324
-
325
-	if (state->period != channel->state.period ||
326
-	    state->duty_cycle != channel->state.duty_cycle ||
327
-	    state->polarity != channel->state.polarity) {
328
-		if (state->polarity != channel->state.polarity) {
329
-			if (state->polarity == PWM_POLARITY_NORMAL)
330
-				meson->inverter_mask |= BIT(pwm->hwpwm);
331
-			else
332
-				meson->inverter_mask &= ~BIT(pwm->hwpwm);
295
+			meson_pwm_enable(meson, pwm);
296
+		} else {
297
+			meson_pwm_disable(meson, pwm);
333298 		}
334
-
335
-		err = meson_pwm_calc(meson, channel, pwm->hwpwm,
336
-				     state->duty_cycle, state->period);
299
+	} else {
300
+		err = meson_pwm_calc(meson, pwm, state);
337301 		if (err < 0)
338302 			return err;
339303 
340
-		channel->state.polarity = state->polarity;
341
-		channel->state.period = state->period;
342
-		channel->state.duty_cycle = state->duty_cycle;
343
-	}
344
-
345
-	if (state->enabled && !channel->state.enabled) {
346
-		meson_pwm_enable(meson, channel, pwm->hwpwm);
347
-		channel->state.enabled = true;
304
+		meson_pwm_enable(meson, pwm);
348305 	}
349306 
350307 	return 0;
308
+}
309
+
310
+static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
311
+					struct pwm_device *pwm, u32 cnt)
312
+{
313
+	struct meson_pwm *meson = to_meson_pwm(chip);
314
+	struct meson_pwm_channel *channel;
315
+	unsigned long fin_freq;
316
+	u32 fin_ns;
317
+
318
+	/* to_meson_pwm() can only be used after .get_state() is called */
319
+	channel = &meson->channels[pwm->hwpwm];
320
+
321
+	fin_freq = clk_get_rate(channel->clk);
322
+	if (fin_freq == 0)
323
+		return 0;
324
+
325
+	fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
326
+
327
+	return cnt * fin_ns * (channel->pre_div + 1);
351328 }
352329 
353330 static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
354331 				struct pwm_state *state)
355332 {
356333 	struct meson_pwm *meson = to_meson_pwm(chip);
357
-	u32 value, mask;
334
+	struct meson_pwm_channel_data *channel_data;
335
+	struct meson_pwm_channel *channel;
336
+	u32 value, tmp;
358337 
359338 	if (!state)
360339 		return;
361340 
362
-	switch (pwm->hwpwm) {
363
-	case 0:
364
-		mask = MISC_A_EN;
365
-		break;
366
-
367
-	case 1:
368
-		mask = MISC_B_EN;
369
-		break;
370
-
371
-	default:
372
-		return;
373
-	}
341
+	channel = &meson->channels[pwm->hwpwm];
342
+	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
374343 
375344 	value = readl(meson->base + REG_MISC_AB);
376
-	state->enabled = (value & mask) != 0;
345
+
346
+	tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
347
+	state->enabled = (value & tmp) == tmp;
348
+
349
+	tmp = value >> channel_data->clk_div_shift;
350
+	channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
351
+
352
+	value = readl(meson->base + channel_data->reg_offset);
353
+
354
+	channel->lo = FIELD_GET(PWM_LOW_MASK, value);
355
+	channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
356
+
357
+	if (channel->lo == 0) {
358
+		state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
359
+		state->duty_cycle = state->period;
360
+	} else if (channel->lo >= channel->hi) {
361
+		state->period = meson_pwm_cnt_to_ns(chip, pwm,
362
+						    channel->lo + channel->hi);
363
+		state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
364
+							channel->hi);
365
+	} else {
366
+		state->period = 0;
367
+		state->duty_cycle = 0;
368
+	}
377369 }
378370 
379371 static const struct pwm_ops meson_pwm_ops = {
....@@ -433,6 +425,33 @@
433425 	.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
434426 };
435427 
428
+static const char * const pwm_g12a_ao_ab_parent_names[] = {
429
+	"xtal", "aoclk81", "fclk_div4", "fclk_div5"
430
+};
431
+
432
+static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
433
+	.parent_names = pwm_g12a_ao_ab_parent_names,
434
+	.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
435
+};
436
+
437
+static const char * const pwm_g12a_ao_cd_parent_names[] = {
438
+	"xtal", "aoclk81",
439
+};
440
+
441
+static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
442
+	.parent_names = pwm_g12a_ao_cd_parent_names,
443
+	.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
444
+};
445
+
446
+static const char * const pwm_g12a_ee_parent_names[] = {
447
+	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
448
+};
449
+
450
+static const struct meson_pwm_data pwm_g12a_ee_data = {
451
+	.parent_names = pwm_g12a_ee_parent_names,
452
+	.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
453
+};
454
+
436455 static const struct of_device_id meson_pwm_matches[] = {
437456 	{
438457 		.compatible = "amlogic,meson8b-pwm",
....@@ -454,12 +473,23 @@
454473 		.compatible = "amlogic,meson-axg-ao-pwm",
455474 		.data = &pwm_axg_ao_data
456475 	},
476
+	{
477
+		.compatible = "amlogic,meson-g12a-ee-pwm",
478
+		.data = &pwm_g12a_ee_data
479
+	},
480
+	{
481
+		.compatible = "amlogic,meson-g12a-ao-pwm-ab",
482
+		.data = &pwm_g12a_ao_ab_data
483
+	},
484
+	{
485
+		.compatible = "amlogic,meson-g12a-ao-pwm-cd",
486
+		.data = &pwm_g12a_ao_cd_data
487
+	},
457488 	{},
458489 };
459490 MODULE_DEVICE_TABLE(of, meson_pwm_matches);
460491 
461
-static int meson_pwm_init_channels(struct meson_pwm *meson,
462
-				   struct meson_pwm_channel *channels)
492
+static int meson_pwm_init_channels(struct meson_pwm *meson)
463493 {
464494 	struct device *dev = meson->chip.dev;
465495 	struct clk_init_data init;
....@@ -468,19 +498,20 @@
468498 	int err;
469499 
470500 	for (i = 0; i < meson->chip.npwm; i++) {
471
-		struct meson_pwm_channel *channel = &channels[i];
501
+		struct meson_pwm_channel *channel = &meson->channels[i];
472502 
473503 		snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
474504 
475505 		init.name = name;
476506 		init.ops = &clk_mux_ops;
477
-		init.flags = CLK_IS_BASIC;
507
+		init.flags = 0;
478508 		init.parent_names = meson->data->parent_names;
479509 		init.num_parents = meson->data->num_parents;
480510 
481511 		channel->mux.reg = meson->base + REG_MISC_AB;
482
-		channel->mux.shift = mux_reg_shifts[i];
483
-		channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1;
512
+		channel->mux.shift =
513
+				meson_pwm_per_channel_data[i].clk_sel_shift;
514
+		channel->mux.mask = MISC_CLK_SEL_MASK;
484515 		channel->mux.flags = 0;
485516 		channel->mux.lock = &meson->lock;
486517 		channel->mux.table = NULL;
....@@ -495,31 +526,16 @@
495526 
496527 		snprintf(name, sizeof(name), "clkin%u", i);
497528 
498
-		channel->clk_parent = devm_clk_get(dev, name);
499
-		if (IS_ERR(channel->clk_parent)) {
500
-			err = PTR_ERR(channel->clk_parent);
501
-			if (err == -EPROBE_DEFER)
502
-				return err;
503
-
504
-			channel->clk_parent = NULL;
505
-		}
529
+		channel->clk_parent = devm_clk_get_optional(dev, name);
530
+		if (IS_ERR(channel->clk_parent))
531
+			return PTR_ERR(channel->clk_parent);
506532 	}
507533 
508534 	return 0;
509535 }
510536 
511
-static void meson_pwm_add_channels(struct meson_pwm *meson,
512
-				   struct meson_pwm_channel *channels)
513
-{
514
-	unsigned int i;
515
-
516
-	for (i = 0; i < meson->chip.npwm; i++)
517
-		pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]);
518
-}
519
-
520537 static int meson_pwm_probe(struct platform_device *pdev)
521538 {
522
-	struct meson_pwm_channel *channels;
523539 	struct meson_pwm *meson;
524540 	struct resource *regs;
525541 	int err;
....@@ -537,19 +553,13 @@
537553 	meson->chip.dev = &pdev->dev;
538554 	meson->chip.ops = &meson_pwm_ops;
539555 	meson->chip.base = -1;
540
-	meson->chip.npwm = 2;
556
+	meson->chip.npwm = MESON_NUM_PWMS;
541557 	meson->chip.of_xlate = of_pwm_xlate_with_flags;
542558 	meson->chip.of_pwm_n_cells = 3;
543559 
544560 	meson->data = of_device_get_match_data(&pdev->dev);
545
-	meson->inverter_mask = BIT(meson->chip.npwm) - 1;
546561 
547
-	channels = devm_kcalloc(&pdev->dev, meson->chip.npwm,
548
-				sizeof(*channels), GFP_KERNEL);
549
-	if (!channels)
550
-		return -ENOMEM;
551
-
552
-	err = meson_pwm_init_channels(meson, channels);
562
+	err = meson_pwm_init_channels(meson);
553563 	if (err < 0)
554564 		return err;
555565 
....@@ -558,8 +568,6 @@
558568 		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
559569 		return err;
560570 	}
561
-
562
-	meson_pwm_add_channels(meson, channels);
563571 
564572 	platform_set_drvdata(pdev, meson);
565573