.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Pinctrl data for the NVIDIA Tegra20 pinmux |
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3 | 4 | * |
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.. | .. |
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8 | 9 | * Derived from code: |
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9 | 10 | * Copyright (C) 2010 Google, Inc. |
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10 | 11 | * Copyright (C) 2010 NVIDIA Corporation |
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11 | | - * |
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12 | | - * This program is free software; you can redistribute it and/or modify it |
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13 | | - * under the terms and conditions of the GNU General Public License, |
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14 | | - * version 2, as published by the Free Software Foundation. |
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15 | | - * |
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16 | | - * This program is distributed in the hope it will be useful, but WITHOUT |
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17 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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18 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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19 | | - * more details. |
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20 | 12 | */ |
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21 | 13 | |
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22 | 14 | #include <linux/clk-provider.h> |
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.. | .. |
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1997 | 1989 | .tri_reg = ((tri_r) - TRISTATE_REG_A), \ |
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1998 | 1990 | .tri_bank = 0, \ |
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1999 | 1991 | .tri_bit = tri_b, \ |
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2000 | | - .parked_bit = -1, \ |
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2001 | 1992 | .einput_bit = -1, \ |
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2002 | 1993 | .odrain_bit = -1, \ |
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2003 | 1994 | .lock_bit = -1, \ |
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2004 | 1995 | .ioreset_bit = -1, \ |
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2005 | 1996 | .rcv_sel_bit = -1, \ |
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2006 | 1997 | .drv_reg = -1, \ |
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| 1998 | + .parked_bitmask = 0, \ |
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2007 | 1999 | } |
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2008 | 2000 | |
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2009 | 2001 | /* Pin groups with only pull up and pull down control */ |
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.. | .. |
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2017 | 2009 | .pupd_bank = 2, \ |
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2018 | 2010 | .pupd_bit = pupd_b, \ |
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2019 | 2011 | .drv_reg = -1, \ |
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2020 | | - .parked_bit = -1, \ |
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| 2012 | + .parked_bitmask = 0, \ |
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2021 | 2013 | } |
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2022 | 2014 | |
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2023 | 2015 | /* Pin groups for drive strength registers (configurable version) */ |
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.. | .. |
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2033 | 2025 | .tri_reg = -1, \ |
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2034 | 2026 | .drv_reg = ((r) - PINGROUP_REG_A), \ |
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2035 | 2027 | .drv_bank = 3, \ |
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2036 | | - .parked_bit = -1, \ |
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| 2028 | + .parked_bitmask = 0, \ |
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2037 | 2029 | .hsm_bit = hsm_b, \ |
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2038 | 2030 | .schmitt_bit = schmitt_b, \ |
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2039 | 2031 | .lpmd_bit = lpmd_b, \ |
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